t102xqds.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <netdev.h>
  12. #include <linux/compiler.h>
  13. #include <asm/mmu.h>
  14. #include <asm/processor.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include <hwconfig.h>
  22. #include "../common/qixis.h"
  23. #include "t102xqds.h"
  24. #include "t102xqds_qixis.h"
  25. #include "../common/sleep.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. int checkboard(void)
  28. {
  29. char buf[64];
  30. struct cpu_type *cpu = gd->arch.cpu;
  31. static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  32. int clock;
  33. u8 sw = QIXIS_READ(arch);
  34. printf("Board: %sQDS, ", cpu->name);
  35. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  36. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  37. #ifdef CONFIG_SDCARD
  38. puts("SD/MMC\n");
  39. #elif CONFIG_SPIFLASH
  40. puts("SPI\n");
  41. #else
  42. sw = QIXIS_READ(brdcfg[0]);
  43. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  44. if (sw < 0x8)
  45. printf("vBank: %d\n", sw);
  46. else if (sw == 0x8)
  47. puts("PromJet\n");
  48. else if (sw == 0x9)
  49. puts("NAND\n");
  50. else if (sw == 0x15)
  51. printf("IFC Card\n");
  52. else
  53. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  54. #endif
  55. printf("FPGA: v%d (%s), build %d",
  56. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  57. (int)qixis_read_minor());
  58. /* the timestamp string contains "\n" at the end */
  59. printf(" on %s", qixis_read_time(buf));
  60. puts("SERDES Reference: ");
  61. sw = QIXIS_READ(brdcfg[2]);
  62. clock = (sw >> 6) & 3;
  63. printf("Clock1=%sMHz ", freq[clock]);
  64. clock = (sw >> 4) & 3;
  65. printf("Clock2=%sMHz\n", freq[clock]);
  66. return 0;
  67. }
  68. int select_i2c_ch_pca9547(u8 ch)
  69. {
  70. int ret;
  71. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  72. if (ret) {
  73. puts("PCA: failed to select proper channel\n");
  74. return ret;
  75. }
  76. return 0;
  77. }
  78. static int board_mux_lane_to_slot(void)
  79. {
  80. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  81. u32 srds_prtcl_s1;
  82. u8 brdcfg9;
  83. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  84. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  85. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  86. brdcfg9 = QIXIS_READ(brdcfg[9]);
  87. QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
  88. switch (srds_prtcl_s1) {
  89. case 0:
  90. /* SerDes1 is not enabled */
  91. break;
  92. case 0xd5:
  93. case 0x5b:
  94. case 0x6b:
  95. case 0x77:
  96. case 0x6f:
  97. case 0x7f:
  98. QIXIS_WRITE(brdcfg[12], 0x8c);
  99. break;
  100. case 0x40:
  101. QIXIS_WRITE(brdcfg[12], 0xfc);
  102. break;
  103. case 0xd6:
  104. case 0x5a:
  105. case 0x6a:
  106. case 0x56:
  107. QIXIS_WRITE(brdcfg[12], 0x88);
  108. break;
  109. case 0x47:
  110. QIXIS_WRITE(brdcfg[12], 0xcc);
  111. break;
  112. case 0x46:
  113. QIXIS_WRITE(brdcfg[12], 0xc8);
  114. break;
  115. case 0x95:
  116. case 0x99:
  117. brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
  118. QIXIS_WRITE(brdcfg[9], brdcfg9);
  119. QIXIS_WRITE(brdcfg[12], 0x8c);
  120. break;
  121. case 0x116:
  122. QIXIS_WRITE(brdcfg[12], 0x00);
  123. break;
  124. case 0x115:
  125. case 0x119:
  126. case 0x129:
  127. case 0x12b:
  128. /* Aurora, PCIe, SGMII, SATA */
  129. QIXIS_WRITE(brdcfg[12], 0x04);
  130. break;
  131. default:
  132. printf("WARNING: unsupported for SerDes Protocol %d\n",
  133. srds_prtcl_s1);
  134. return -1;
  135. }
  136. return 0;
  137. }
  138. #ifdef CONFIG_ARCH_T1024
  139. static void board_mux_setup(void)
  140. {
  141. u8 brdcfg15;
  142. brdcfg15 = QIXIS_READ(brdcfg[15]);
  143. brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
  144. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  145. /* Route QE_TDM multiplexed signals to TDM Riser slot */
  146. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
  147. QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
  148. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  149. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
  150. } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
  151. /* to UCC (ProfiBus) interface */
  152. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
  153. } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
  154. /* to DVI (HDMI) encoder */
  155. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
  156. } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
  157. /* to DFP (LCD) encoder */
  158. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
  159. BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
  160. }
  161. if (hwconfig_arg_cmp("adaptor", "sdxc"))
  162. /* Route SPI_CS multiplexed signals to SD slot */
  163. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  164. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
  165. }
  166. #endif
  167. void board_retimer_ds125df111_init(void)
  168. {
  169. u8 reg;
  170. /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
  171. reg = I2C_MUX_CH7;
  172. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
  173. reg = I2C_MUX_CH5;
  174. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  175. /* Access to Control/Shared register */
  176. reg = 0x0;
  177. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  178. /* Read device revision and ID */
  179. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  180. debug("Retimer version id = 0x%x\n", reg);
  181. /* Enable Broadcast */
  182. reg = 0x0c;
  183. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  184. /* Reset Channel Registers */
  185. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  186. reg |= 0x4;
  187. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  188. /* Enable override divider select and Enable Override Output Mux */
  189. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  190. reg |= 0x24;
  191. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  192. /* Select VCO Divider to full rate (000) */
  193. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  194. reg &= 0x8f;
  195. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  196. /* Select active PFD MUX input as re-timed data (001) */
  197. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  198. reg &= 0x3f;
  199. reg |= 0x20;
  200. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  201. /* Set data rate as 10.3125 Gbps */
  202. reg = 0x0;
  203. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  204. reg = 0xb2;
  205. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  206. reg = 0x90;
  207. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  208. reg = 0xb3;
  209. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  210. reg = 0xcd;
  211. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  212. }
  213. int board_early_init_f(void)
  214. {
  215. #if defined(CONFIG_DEEP_SLEEP)
  216. if (is_warm_boot())
  217. fsl_dp_disable_console();
  218. #endif
  219. return 0;
  220. }
  221. int board_early_init_r(void)
  222. {
  223. #ifdef CONFIG_SYS_FLASH_BASE
  224. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  225. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  226. /*
  227. * Remap Boot flash + PROMJET region to caching-inhibited
  228. * so that flash can be erased properly.
  229. */
  230. /* Flush d-cache and invalidate i-cache of any FLASH data */
  231. flush_dcache();
  232. invalidate_icache();
  233. if (flash_esel == -1) {
  234. /* very unlikely unless something is messed up */
  235. puts("Error: Could not find TLB for FLASH BASE\n");
  236. flash_esel = 2; /* give our best effort to continue */
  237. } else {
  238. /* invalidate existing TLB entry for flash + promjet */
  239. disable_tlb(flash_esel);
  240. }
  241. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  242. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  243. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  244. #endif
  245. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  246. board_mux_lane_to_slot();
  247. board_retimer_ds125df111_init();
  248. /* Increase IO drive strength to address FCS error on RGMII */
  249. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
  250. return 0;
  251. }
  252. unsigned long get_board_sys_clk(void)
  253. {
  254. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  255. switch (sysclk_conf & 0x0F) {
  256. case QIXIS_SYSCLK_64:
  257. return 64000000;
  258. case QIXIS_SYSCLK_83:
  259. return 83333333;
  260. case QIXIS_SYSCLK_100:
  261. return 100000000;
  262. case QIXIS_SYSCLK_125:
  263. return 125000000;
  264. case QIXIS_SYSCLK_133:
  265. return 133333333;
  266. case QIXIS_SYSCLK_150:
  267. return 150000000;
  268. case QIXIS_SYSCLK_160:
  269. return 160000000;
  270. case QIXIS_SYSCLK_166:
  271. return 166666666;
  272. }
  273. return 66666666;
  274. }
  275. unsigned long get_board_ddr_clk(void)
  276. {
  277. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  278. switch ((ddrclk_conf & 0x30) >> 4) {
  279. case QIXIS_DDRCLK_100:
  280. return 100000000;
  281. case QIXIS_DDRCLK_125:
  282. return 125000000;
  283. case QIXIS_DDRCLK_133:
  284. return 133333333;
  285. }
  286. return 66666666;
  287. }
  288. #define NUM_SRDS_PLL 2
  289. int misc_init_r(void)
  290. {
  291. #ifdef CONFIG_ARCH_T1024
  292. board_mux_setup();
  293. #endif
  294. return 0;
  295. }
  296. void fdt_fixup_spi_mux(void *blob)
  297. {
  298. int nodeoff = 0;
  299. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  300. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  301. "eon,en25s64")) >= 0) {
  302. fdt_del_node(blob, nodeoff);
  303. }
  304. } else {
  305. /* remove tdm node */
  306. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  307. "maxim,ds26522")) >= 0) {
  308. fdt_del_node(blob, nodeoff);
  309. }
  310. }
  311. }
  312. int ft_board_setup(void *blob, bd_t *bd)
  313. {
  314. phys_addr_t base;
  315. phys_size_t size;
  316. ft_cpu_setup(blob, bd);
  317. base = env_get_bootm_low();
  318. size = env_get_bootm_size();
  319. fdt_fixup_memory(blob, (u64)base, (u64)size);
  320. #ifdef CONFIG_PCI
  321. pci_of_setup(blob, bd);
  322. #endif
  323. fdt_fixup_liodn(blob);
  324. #ifdef CONFIG_HAS_FSL_DR_USB
  325. fsl_fdt_fixup_dr_usb(blob, bd);
  326. #endif
  327. #ifdef CONFIG_SYS_DPAA_FMAN
  328. fdt_fixup_fman_ethernet(blob);
  329. fdt_fixup_board_enet(blob);
  330. #endif
  331. fdt_fixup_spi_mux(blob);
  332. return 0;
  333. }
  334. void qixis_dump_switch(void)
  335. {
  336. int i, nr_of_cfgsw;
  337. QIXIS_WRITE(cms[0], 0x00);
  338. nr_of_cfgsw = QIXIS_READ(cms[1]);
  339. puts("DIP switch settings dump:\n");
  340. for (i = 1; i <= nr_of_cfgsw; i++) {
  341. QIXIS_WRITE(cms[0], i);
  342. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  343. }
  344. }