p2041rdb.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <fm_eth.h>
  20. extern void pci_of_setup(void *blob, bd_t *bd);
  21. #include "cpld.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int checkboard(void)
  24. {
  25. u8 sw;
  26. struct cpu_type *cpu = gd->arch.cpu;
  27. unsigned int i;
  28. printf("Board: %sRDB, ", cpu->name);
  29. printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  30. CPLD_READ(cpld_ver_sub));
  31. sw = CPLD_READ(fbank_sel);
  32. printf("vBank: %d\n", sw & 0x1);
  33. /*
  34. * Display the actual SERDES reference clocks as configured by the
  35. * dip switches on the board. Note that the SWx registers could
  36. * technically be set to force the reference clocks to match the
  37. * values that the SERDES expects (or vice versa). For now, however,
  38. * we just display both values and hope the user notices when they
  39. * don't match.
  40. */
  41. puts("SERDES Reference Clocks: ");
  42. sw = in_8(&CPLD_SW(2)) >> 2;
  43. for (i = 0; i < 2; i++) {
  44. static const char * const freq[][3] = {{"0", "100", "125"},
  45. {"100", "156.25", "125"}
  46. };
  47. unsigned int clock = (sw >> (2 * i)) & 3;
  48. printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  49. }
  50. puts("\n");
  51. return 0;
  52. }
  53. int board_early_init_f(void)
  54. {
  55. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  56. /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  57. setbits_be32(&gur->ddrclkdr, 0x000f000f);
  58. return 0;
  59. }
  60. #define CPLD_LANE_A_SEL 0x1
  61. #define CPLD_LANE_G_SEL 0x2
  62. #define CPLD_LANE_C_SEL 0x4
  63. #define CPLD_LANE_D_SEL 0x8
  64. void board_config_lanes_mux(void)
  65. {
  66. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  67. int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  68. FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  69. u8 mux = 0;
  70. switch (srds_prtcl) {
  71. case 0x2:
  72. case 0x5:
  73. case 0x9:
  74. case 0xa:
  75. case 0xf:
  76. break;
  77. case 0x8:
  78. mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  79. break;
  80. case 0x14:
  81. mux |= CPLD_LANE_A_SEL;
  82. break;
  83. case 0x17:
  84. mux |= CPLD_LANE_G_SEL;
  85. break;
  86. case 0x16:
  87. case 0x19:
  88. case 0x1a:
  89. mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  90. break;
  91. case 0x1c:
  92. mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
  93. break;
  94. default:
  95. printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
  96. break;
  97. }
  98. CPLD_WRITE(serdes_mux, mux);
  99. }
  100. int board_early_init_r(void)
  101. {
  102. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  103. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  104. /*
  105. * Remap Boot flash + PROMJET region to caching-inhibited
  106. * so that flash can be erased properly.
  107. */
  108. /* Flush d-cache and invalidate i-cache of any FLASH data */
  109. flush_dcache();
  110. invalidate_icache();
  111. if (flash_esel == -1) {
  112. /* very unlikely unless something is messed up */
  113. puts("Error: Could not find TLB for FLASH BASE\n");
  114. flash_esel = 2; /* give our best effort to continue */
  115. } else {
  116. /* invalidate existing TLB entry for flash + promjet */
  117. disable_tlb(flash_esel);
  118. }
  119. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  120. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  121. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  122. board_config_lanes_mux();
  123. return 0;
  124. }
  125. unsigned long get_board_sys_clk(unsigned long dummy)
  126. {
  127. u8 sysclk_conf = CPLD_READ(sysclk_sw1);
  128. switch (sysclk_conf & 0x7) {
  129. case CPLD_SYSCLK_83:
  130. return 83333333;
  131. case CPLD_SYSCLK_100:
  132. return 100000000;
  133. default:
  134. return 66666666;
  135. }
  136. }
  137. #define NUM_SRDS_BANKS 2
  138. int misc_init_r(void)
  139. {
  140. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  141. u32 actual[NUM_SRDS_BANKS];
  142. unsigned int i;
  143. u8 sw;
  144. static const int freq[][3] = {
  145. {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
  146. {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
  147. SRDS_PLLCR0_RFCK_SEL_125}
  148. };
  149. sw = in_8(&CPLD_SW(2)) >> 2;
  150. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  151. unsigned int clock = (sw >> (2 * i)) & 3;
  152. if (clock == 0x3) {
  153. printf("Warning: SDREFCLK%u switch setting of '11' is "
  154. "unsupported\n", i + 1);
  155. break;
  156. }
  157. if (i == 0 && clock == 0)
  158. puts("Warning: SDREFCLK1 switch setting of"
  159. "'00' is unsupported\n");
  160. else
  161. actual[i] = freq[i][clock];
  162. /*
  163. * PC board uses a different CPLD with PB board, this CPLD
  164. * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
  165. * board has cpld_ver_sub = 0, and pcba_ver = 4.
  166. */
  167. if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
  168. (CPLD_READ(pcba_ver) == 5)) {
  169. /* PC board bank2 frequency */
  170. actual[i] = freq[i-1][clock];
  171. }
  172. }
  173. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  174. u32 expected = in_be32(&regs->bank[i].pllcr0);
  175. expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
  176. if (expected != actual[i]) {
  177. printf("Warning: SERDES bank %u expects reference clock"
  178. " %sMHz, but actual is %sMHz\n", i + 1,
  179. serdes_clock_to_string(expected),
  180. serdes_clock_to_string(actual[i]));
  181. }
  182. }
  183. return 0;
  184. }
  185. int ft_board_setup(void *blob, bd_t *bd)
  186. {
  187. phys_addr_t base;
  188. phys_size_t size;
  189. ft_cpu_setup(blob, bd);
  190. base = env_get_bootm_low();
  191. size = env_get_bootm_size();
  192. fdt_fixup_memory(blob, (u64)base, (u64)size);
  193. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  194. fsl_fdt_fixup_dr_usb(blob, bd);
  195. #endif
  196. #ifdef CONFIG_PCI
  197. pci_of_setup(blob, bd);
  198. #endif
  199. fdt_fixup_liodn(blob);
  200. #ifdef CONFIG_SYS_DPAA_FMAN
  201. fdt_fixup_fman_ethernet(blob);
  202. #endif
  203. return 0;
  204. }