mpc832xemds.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <fdt_support.h>
  9. #include <init.h>
  10. #include <ioports.h>
  11. #include <mpc83xx.h>
  12. #include <i2c.h>
  13. #include <miiphy.h>
  14. #include <command.h>
  15. #if defined(CONFIG_PCI)
  16. #include <pci.h>
  17. #endif
  18. #include <asm/mmu.h>
  19. #if defined(CONFIG_OF_LIBFDT)
  20. #include <linux/libfdt.h>
  21. #endif
  22. #if defined(CONFIG_PQ_MDS_PIB)
  23. #include "../common/pq-mds-pib.h"
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. const qe_iop_conf_t qe_iop_conf_tab[] = {
  27. /* ETH3 */
  28. {1, 0, 1, 0, 1}, /* TxD0 */
  29. {1, 1, 1, 0, 1}, /* TxD1 */
  30. {1, 2, 1, 0, 1}, /* TxD2 */
  31. {1, 3, 1, 0, 1}, /* TxD3 */
  32. {1, 9, 1, 0, 1}, /* TxER */
  33. {1, 12, 1, 0, 1}, /* TxEN */
  34. {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
  35. {1, 4, 2, 0, 1}, /* RxD0 */
  36. {1, 5, 2, 0, 1}, /* RxD1 */
  37. {1, 6, 2, 0, 1}, /* RxD2 */
  38. {1, 7, 2, 0, 1}, /* RxD3 */
  39. {1, 8, 2, 0, 1}, /* RxER */
  40. {1, 10, 2, 0, 1}, /* RxDV */
  41. {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
  42. {1, 11, 2, 0, 1}, /* COL */
  43. {1, 13, 2, 0, 1}, /* CRS */
  44. /* ETH4 */
  45. {1, 18, 1, 0, 1}, /* TxD0 */
  46. {1, 19, 1, 0, 1}, /* TxD1 */
  47. {1, 20, 1, 0, 1}, /* TxD2 */
  48. {1, 21, 1, 0, 1}, /* TxD3 */
  49. {1, 27, 1, 0, 1}, /* TxER */
  50. {1, 30, 1, 0, 1}, /* TxEN */
  51. {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
  52. {1, 22, 2, 0, 1}, /* RxD0 */
  53. {1, 23, 2, 0, 1}, /* RxD1 */
  54. {1, 24, 2, 0, 1}, /* RxD2 */
  55. {1, 25, 2, 0, 1}, /* RxD3 */
  56. {1, 26, 1, 0, 1}, /* RxER */
  57. {1, 28, 2, 0, 1}, /* Rx_DV */
  58. {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
  59. {1, 29, 2, 0, 1}, /* COL */
  60. {1, 31, 2, 0, 1}, /* CRS */
  61. {3, 4, 3, 0, 2}, /* MDIO */
  62. {3, 5, 1, 0, 2}, /* MDC */
  63. {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  64. };
  65. int board_early_init_f(void)
  66. {
  67. volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
  68. /* Enable flash write */
  69. bcsr[9] &= ~0x08;
  70. return 0;
  71. }
  72. int board_early_init_r(void)
  73. {
  74. #ifdef CONFIG_PQ_MDS_PIB
  75. pib_init();
  76. #endif
  77. return 0;
  78. }
  79. int fixed_sdram(void);
  80. int dram_init(void)
  81. {
  82. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  83. u32 msize = 0;
  84. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  85. return -ENXIO;
  86. /* DDR SDRAM - Main SODIMM */
  87. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  88. msize = fixed_sdram();
  89. /* set total bus SDRAM size(bytes) -- DDR */
  90. gd->ram_size = msize * 1024 * 1024;
  91. return 0;
  92. }
  93. /*************************************************************************
  94. * fixed sdram init -- doesn't use serial presence detect.
  95. ************************************************************************/
  96. int fixed_sdram(void)
  97. {
  98. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  99. u32 msize = 0;
  100. u32 ddr_size;
  101. u32 ddr_size_log2;
  102. msize = CONFIG_SYS_DDR_SIZE;
  103. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  104. (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
  105. if (ddr_size & 1) {
  106. return -1;
  107. }
  108. }
  109. im->sysconf.ddrlaw[0].ar =
  110. LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  111. #if (CONFIG_SYS_DDR_SIZE != 128)
  112. #warning Currenly any ddr size other than 128 is not supported
  113. #endif
  114. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  115. im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  116. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  117. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  118. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  119. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  120. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  121. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  122. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  123. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  124. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  125. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  126. __asm__ __volatile__ ("sync");
  127. udelay(200);
  128. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  129. __asm__ __volatile__ ("sync");
  130. return msize;
  131. }
  132. int checkboard(void)
  133. {
  134. puts("Board: Freescale MPC832XEMDS\n");
  135. return 0;
  136. }
  137. #if defined(CONFIG_OF_BOARD_SETUP)
  138. int ft_board_setup(void *blob, bd_t *bd)
  139. {
  140. ft_cpu_setup(blob, bd);
  141. #ifdef CONFIG_PCI
  142. ft_pci_setup(blob, bd);
  143. #endif
  144. return 0;
  145. }
  146. #endif