mpc8313erdb.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
  4. *
  5. * Author: Scott Wood <scottwood@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <fdt_support.h>
  9. #include <init.h>
  10. #if defined(CONFIG_OF_LIBFDT)
  11. #include <linux/libfdt.h>
  12. #endif
  13. #include <pci.h>
  14. #include <mpc83xx.h>
  15. #include <vsc7385.h>
  16. #include <ns16550.h>
  17. #include <nand.h>
  18. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  19. #include <asm/gpio.h>
  20. #endif
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int board_early_init_f(void)
  23. {
  24. #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
  25. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  26. if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  27. gd->flags |= GD_FLG_SILENT;
  28. #endif
  29. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  30. mpc83xx_gpio_init_f();
  31. #endif
  32. return 0;
  33. }
  34. int board_early_init_r(void)
  35. {
  36. #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
  37. mpc83xx_gpio_init_r();
  38. #endif
  39. return 0;
  40. }
  41. int checkboard(void)
  42. {
  43. puts("Board: Freescale MPC8313ERDB\n");
  44. return 0;
  45. }
  46. #ifndef CONFIG_SPL_BUILD
  47. static struct pci_region pci_regions[] = {
  48. {
  49. .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
  50. .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
  51. .size = CONFIG_SYS_PCI1_MEM_SIZE,
  52. .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
  53. },
  54. {
  55. .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
  56. .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
  57. .size = CONFIG_SYS_PCI1_MMIO_SIZE,
  58. .flags = PCI_REGION_MEM
  59. },
  60. {
  61. .bus_start = CONFIG_SYS_PCI1_IO_BASE,
  62. .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
  63. .size = CONFIG_SYS_PCI1_IO_SIZE,
  64. .flags = PCI_REGION_IO
  65. }
  66. };
  67. void pci_init_board(void)
  68. {
  69. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  70. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  71. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  72. struct pci_region *reg[] = { pci_regions };
  73. /* Enable all 3 PCI_CLK_OUTPUTs. */
  74. clk->occr |= 0xe0000000;
  75. /*
  76. * Configure PCI Local Access Windows
  77. */
  78. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  79. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  80. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  81. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  82. mpc83xx_pci_init(1, reg);
  83. }
  84. /*
  85. * Miscellaneous late-boot configurations
  86. *
  87. * If a VSC7385 microcode image is present, then upload it.
  88. */
  89. int misc_init_r(void)
  90. {
  91. int rc = 0;
  92. #ifdef CONFIG_VSC7385_IMAGE
  93. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  94. CONFIG_VSC7385_IMAGE_SIZE)) {
  95. puts("Failure uploading VSC7385 microcode.\n");
  96. rc = 1;
  97. }
  98. #endif
  99. return rc;
  100. }
  101. #if defined(CONFIG_OF_BOARD_SETUP)
  102. int ft_board_setup(void *blob, bd_t *bd)
  103. {
  104. ft_cpu_setup(blob, bd);
  105. #ifdef CONFIG_PCI
  106. ft_pci_setup(blob, bd);
  107. #endif
  108. return 0;
  109. }
  110. #endif
  111. #else /* CONFIG_SPL_BUILD */
  112. void board_init_f(ulong bootflag)
  113. {
  114. board_early_init_f();
  115. NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
  116. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  117. puts("NAND boot... ");
  118. timer_init();
  119. dram_init();
  120. relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
  121. CONFIG_SYS_NAND_U_BOOT_RELOC);
  122. }
  123. void board_init_r(gd_t *gd, ulong dest_addr)
  124. {
  125. nand_boot();
  126. }
  127. void putc(char c)
  128. {
  129. if (gd->flags & GD_FLG_SILENT)
  130. return;
  131. if (c == '\n')
  132. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
  133. NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
  134. }
  135. #endif