ls1021atwr.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/immap_ls102xa.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/arch/ls102xa_devdis.h>
  14. #include <asm/arch/ls102xa_soc.h>
  15. #include <hwconfig.h>
  16. #include <mmc.h>
  17. #include <fsl_csu.h>
  18. #include <fsl_ifc.h>
  19. #include <fsl_immap.h>
  20. #include <netdev.h>
  21. #include <fsl_mdio.h>
  22. #include <tsec.h>
  23. #include <fsl_sec.h>
  24. #include <fsl_devdis.h>
  25. #include <spl.h>
  26. #include "../common/sleep.h"
  27. #ifdef CONFIG_U_QE
  28. #include <fsl_qe.h>
  29. #endif
  30. #include <fsl_validate.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define VERSION_MASK 0x00FF
  33. #define BANK_MASK 0x0001
  34. #define CONFIG_RESET 0x1
  35. #define INIT_RESET 0x1
  36. #define CPLD_SET_MUX_SERDES 0x20
  37. #define CPLD_SET_BOOT_BANK 0x40
  38. #define BOOT_FROM_UPPER_BANK 0x0
  39. #define BOOT_FROM_LOWER_BANK 0x1
  40. #define LANEB_SATA (0x01)
  41. #define LANEB_SGMII1 (0x02)
  42. #define LANEC_SGMII1 (0x04)
  43. #define LANEC_PCIEX1 (0x08)
  44. #define LANED_PCIEX2 (0x10)
  45. #define LANED_SGMII2 (0x20)
  46. #define MASK_LANE_B 0x1
  47. #define MASK_LANE_C 0x2
  48. #define MASK_LANE_D 0x4
  49. #define MASK_SGMII 0x8
  50. #define KEEP_STATUS 0x0
  51. #define NEED_RESET 0x1
  52. #define SOFT_MUX_ON_I2C3_IFC 0x2
  53. #define SOFT_MUX_ON_CAN3_USB2 0x8
  54. #define SOFT_MUX_ON_QE_LCD 0x10
  55. #define PIN_I2C3_IFC_MUX_I2C3 0x0
  56. #define PIN_I2C3_IFC_MUX_IFC 0x1
  57. #define PIN_CAN3_USB2_MUX_USB2 0x0
  58. #define PIN_CAN3_USB2_MUX_CAN3 0x1
  59. #define PIN_QE_LCD_MUX_LCD 0x0
  60. #define PIN_QE_LCD_MUX_QE 0x1
  61. struct cpld_data {
  62. u8 cpld_ver; /* cpld revision */
  63. u8 cpld_ver_sub; /* cpld sub revision */
  64. u8 pcba_ver; /* pcb revision number */
  65. u8 system_rst; /* reset system by cpld */
  66. u8 soft_mux_on; /* CPLD override physical switches Enable */
  67. u8 cfg_rcw_src1; /* Reset config word 1 */
  68. u8 cfg_rcw_src2; /* Reset config word 2 */
  69. u8 vbank; /* Flash bank selection Control */
  70. u8 gpio; /* GPIO for TWR-ELEV */
  71. u8 i2c3_ifc_mux;
  72. u8 mux_spi2;
  73. u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
  74. u8 qe_lcd_mux; /* QE and LCD Selection */
  75. u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
  76. u8 global_rst; /* reset with init CPLD reg to default */
  77. u8 rev1; /* Reserved */
  78. u8 rev2; /* Reserved */
  79. };
  80. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  81. static void cpld_show(void)
  82. {
  83. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  84. printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
  85. in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  86. in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
  87. in_8(&cpld_data->pcba_ver) & VERSION_MASK,
  88. in_8(&cpld_data->vbank) & BANK_MASK);
  89. #ifdef CONFIG_DEBUG
  90. printf("soft_mux_on =%x\n",
  91. in_8(&cpld_data->soft_mux_on));
  92. printf("cfg_rcw_src1 =%x\n",
  93. in_8(&cpld_data->cfg_rcw_src1));
  94. printf("cfg_rcw_src2 =%x\n",
  95. in_8(&cpld_data->cfg_rcw_src2));
  96. printf("vbank =%x\n",
  97. in_8(&cpld_data->vbank));
  98. printf("gpio =%x\n",
  99. in_8(&cpld_data->gpio));
  100. printf("i2c3_ifc_mux =%x\n",
  101. in_8(&cpld_data->i2c3_ifc_mux));
  102. printf("mux_spi2 =%x\n",
  103. in_8(&cpld_data->mux_spi2));
  104. printf("can3_usb2_mux =%x\n",
  105. in_8(&cpld_data->can3_usb2_mux));
  106. printf("qe_lcd_mux =%x\n",
  107. in_8(&cpld_data->qe_lcd_mux));
  108. printf("serdes_mux =%x\n",
  109. in_8(&cpld_data->serdes_mux));
  110. #endif
  111. }
  112. #endif
  113. int checkboard(void)
  114. {
  115. puts("Board: LS1021ATWR\n");
  116. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  117. cpld_show();
  118. #endif
  119. return 0;
  120. }
  121. void ddrmc_init(void)
  122. {
  123. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  124. u32 temp_sdram_cfg, tmp;
  125. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  126. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  127. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  128. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  129. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  130. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  131. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  132. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  133. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  134. #ifdef CONFIG_DEEP_SLEEP
  135. if (is_warm_boot()) {
  136. out_be32(&ddr->sdram_cfg_2,
  137. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  138. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  139. out_be32(&ddr->init_ext_addr, (1 << 31));
  140. /* DRAM VRef will not be trained */
  141. out_be32(&ddr->ddr_cdr2,
  142. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  143. } else
  144. #endif
  145. {
  146. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  147. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  148. }
  149. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  150. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  151. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  152. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  153. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  154. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  155. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  156. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  157. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  158. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  159. /* DDR erratum A-009942 */
  160. tmp = in_be32(&ddr->debug[28]);
  161. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  162. udelay(1);
  163. #ifdef CONFIG_DEEP_SLEEP
  164. if (is_warm_boot()) {
  165. /* enter self-refresh */
  166. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  167. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  168. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  169. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  170. } else
  171. #endif
  172. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  173. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  174. #ifdef CONFIG_DEEP_SLEEP
  175. if (is_warm_boot()) {
  176. /* exit self-refresh */
  177. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  178. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  179. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  180. }
  181. #endif
  182. }
  183. int dram_init(void)
  184. {
  185. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  186. ddrmc_init();
  187. #endif
  188. erratum_a008850_post();
  189. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  190. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  191. fsl_dp_resume();
  192. #endif
  193. return 0;
  194. }
  195. int board_eth_init(bd_t *bis)
  196. {
  197. return pci_eth_init(bis);
  198. }
  199. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  200. static void convert_serdes_mux(int type, int need_reset)
  201. {
  202. char current_serdes;
  203. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  204. current_serdes = cpld_data->serdes_mux;
  205. switch (type) {
  206. case LANEB_SATA:
  207. current_serdes &= ~MASK_LANE_B;
  208. break;
  209. case LANEB_SGMII1:
  210. current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  211. break;
  212. case LANEC_SGMII1:
  213. current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
  214. break;
  215. case LANED_SGMII2:
  216. current_serdes |= MASK_LANE_D;
  217. break;
  218. case LANEC_PCIEX1:
  219. current_serdes |= MASK_LANE_C;
  220. break;
  221. case (LANED_PCIEX2 | LANEC_PCIEX1):
  222. current_serdes |= MASK_LANE_C;
  223. current_serdes &= ~MASK_LANE_D;
  224. break;
  225. default:
  226. printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
  227. return;
  228. }
  229. cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
  230. cpld_data->serdes_mux = current_serdes;
  231. if (need_reset == 1) {
  232. printf("Reset board to enable configuration\n");
  233. cpld_data->system_rst = CONFIG_RESET;
  234. }
  235. }
  236. int config_serdes_mux(void)
  237. {
  238. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  239. u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  240. protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  241. switch (protocol) {
  242. case 0x10:
  243. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  244. convert_serdes_mux(LANED_PCIEX2 |
  245. LANEC_PCIEX1, KEEP_STATUS);
  246. break;
  247. case 0x20:
  248. convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
  249. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  250. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  251. break;
  252. case 0x30:
  253. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  254. convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
  255. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  256. break;
  257. case 0x70:
  258. convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
  259. convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
  260. convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
  261. break;
  262. }
  263. return 0;
  264. }
  265. #endif
  266. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  267. int config_board_mux(void)
  268. {
  269. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  270. int conflict_flag;
  271. conflict_flag = 0;
  272. if (hwconfig("i2c3")) {
  273. conflict_flag++;
  274. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  275. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
  276. }
  277. if (hwconfig("ifc")) {
  278. conflict_flag++;
  279. /* some signals can not enable simultaneous*/
  280. if (conflict_flag > 1)
  281. goto conflict;
  282. cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
  283. cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
  284. }
  285. conflict_flag = 0;
  286. if (hwconfig("usb2")) {
  287. conflict_flag++;
  288. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  289. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
  290. }
  291. if (hwconfig("can3")) {
  292. conflict_flag++;
  293. /* some signals can not enable simultaneous*/
  294. if (conflict_flag > 1)
  295. goto conflict;
  296. cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
  297. cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
  298. }
  299. conflict_flag = 0;
  300. if (hwconfig("lcd")) {
  301. conflict_flag++;
  302. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  303. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
  304. }
  305. if (hwconfig("qe")) {
  306. conflict_flag++;
  307. /* some signals can not enable simultaneous*/
  308. if (conflict_flag > 1)
  309. goto conflict;
  310. cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
  311. cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
  312. }
  313. return 0;
  314. conflict:
  315. printf("WARNING: pin conflict! MUX setting may failed!\n");
  316. return 0;
  317. }
  318. #endif
  319. int board_early_init_f(void)
  320. {
  321. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  322. #ifdef CONFIG_TSEC_ENET
  323. /* clear BD & FR bits for BE BD's and frame data */
  324. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  325. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  326. #endif
  327. #ifdef CONFIG_FSL_IFC
  328. init_early_memctl_regs();
  329. #endif
  330. arch_soc_init();
  331. #if defined(CONFIG_DEEP_SLEEP)
  332. if (is_warm_boot()) {
  333. timer_init();
  334. dram_init();
  335. }
  336. #endif
  337. return 0;
  338. }
  339. #ifdef CONFIG_SPL_BUILD
  340. void board_init_f(ulong dummy)
  341. {
  342. void (*second_uboot)(void);
  343. /* Clear the BSS */
  344. memset(__bss_start, 0, __bss_end - __bss_start);
  345. get_clocks();
  346. #if defined(CONFIG_DEEP_SLEEP)
  347. if (is_warm_boot())
  348. fsl_dp_disable_console();
  349. #endif
  350. preloader_console_init();
  351. timer_init();
  352. dram_init();
  353. /* Allow OCRAM access permission as R/W */
  354. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  355. enable_layerscape_ns_access();
  356. #endif
  357. /*
  358. * if it is woken up from deep sleep, then jump to second
  359. * stage uboot and continue executing without recopying
  360. * it from SD since it has already been reserved in memeory
  361. * in last boot.
  362. */
  363. if (is_warm_boot()) {
  364. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  365. second_uboot();
  366. }
  367. board_init_r(NULL, 0);
  368. }
  369. #endif
  370. #ifdef CONFIG_DEEP_SLEEP
  371. /* program the regulator (MC34VR500) to support deep sleep */
  372. void ls1twr_program_regulator(void)
  373. {
  374. unsigned int i2c_bus;
  375. u8 i2c_device_id;
  376. #define LS1TWR_I2C_BUS_MC34VR500 1
  377. #define MC34VR500_ADDR 0x8
  378. #define MC34VR500_DEVICEID 0x4
  379. #define MC34VR500_DEVICEID_MASK 0x0f
  380. i2c_bus = i2c_get_bus_num();
  381. i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
  382. i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
  383. MC34VR500_DEVICEID_MASK;
  384. if (i2c_device_id != MC34VR500_DEVICEID) {
  385. printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
  386. return;
  387. }
  388. i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
  389. i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
  390. i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
  391. i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
  392. i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
  393. i2c_set_bus_num(i2c_bus);
  394. }
  395. #endif
  396. int board_init(void)
  397. {
  398. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  399. erratum_a010315();
  400. #endif
  401. #ifndef CONFIG_SYS_FSL_NO_SERDES
  402. fsl_serdes_init();
  403. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  404. config_serdes_mux();
  405. #endif
  406. #endif
  407. ls102xa_smmu_stream_id_init();
  408. #ifdef CONFIG_U_QE
  409. u_qe_init();
  410. #endif
  411. #ifdef CONFIG_DEEP_SLEEP
  412. ls1twr_program_regulator();
  413. #endif
  414. return 0;
  415. }
  416. #if defined(CONFIG_SPL_BUILD)
  417. void spl_board_init(void)
  418. {
  419. ls102xa_smmu_stream_id_init();
  420. }
  421. #endif
  422. #ifdef CONFIG_BOARD_LATE_INIT
  423. int board_late_init(void)
  424. {
  425. #ifdef CONFIG_CHAIN_OF_TRUST
  426. fsl_setenv_chain_of_trust();
  427. #endif
  428. return 0;
  429. }
  430. #endif
  431. #if defined(CONFIG_MISC_INIT_R)
  432. int misc_init_r(void)
  433. {
  434. #ifdef CONFIG_FSL_DEVICE_DISABLE
  435. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  436. #endif
  437. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  438. config_board_mux();
  439. #endif
  440. #ifdef CONFIG_FSL_CAAM
  441. return sec_init();
  442. #endif
  443. }
  444. #endif
  445. #if defined(CONFIG_DEEP_SLEEP)
  446. void board_sleep_prepare(void)
  447. {
  448. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  449. enable_layerscape_ns_access();
  450. #endif
  451. }
  452. #endif
  453. int ft_board_setup(void *blob, bd_t *bd)
  454. {
  455. ft_cpu_setup(blob, bd);
  456. #ifdef CONFIG_PCI
  457. ft_pci_setup(blob, bd);
  458. #endif
  459. return 0;
  460. }
  461. u8 flash_read8(void *addr)
  462. {
  463. return __raw_readb(addr + 1);
  464. }
  465. void flash_write16(u16 val, void *addr)
  466. {
  467. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  468. __raw_writew(shftval, addr);
  469. }
  470. u16 flash_read16(void *addr)
  471. {
  472. u16 val = __raw_readw(addr);
  473. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  474. }
  475. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
  476. && !defined(CONFIG_SPL_BUILD)
  477. static void convert_flash_bank(char bank)
  478. {
  479. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  480. printf("Now switch to boot from flash bank %d.\n", bank);
  481. cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
  482. cpld_data->vbank = bank;
  483. printf("Reset board to enable configuration.\n");
  484. cpld_data->system_rst = CONFIG_RESET;
  485. }
  486. static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  487. char * const argv[])
  488. {
  489. if (argc != 2)
  490. return CMD_RET_USAGE;
  491. if (strcmp(argv[1], "0") == 0)
  492. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  493. else if (strcmp(argv[1], "1") == 0)
  494. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  495. else
  496. return CMD_RET_USAGE;
  497. return 0;
  498. }
  499. U_BOOT_CMD(
  500. boot_bank, 2, 0, flash_bank_cmd,
  501. "Flash bank Selection Control",
  502. "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
  503. );
  504. static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  505. char * const argv[])
  506. {
  507. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  508. if (argc > 2)
  509. return CMD_RET_USAGE;
  510. if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
  511. cpld_data->system_rst = CONFIG_RESET;
  512. else if (strcmp(argv[1], "init") == 0)
  513. cpld_data->global_rst = INIT_RESET;
  514. else
  515. return CMD_RET_USAGE;
  516. return 0;
  517. }
  518. U_BOOT_CMD(
  519. cpld_reset, 2, 0, cpld_reset_cmd,
  520. "Reset via CPLD",
  521. "conf\n"
  522. " -reset with current CPLD configuration\n"
  523. "init\n"
  524. " -reset and initial CPLD configuration with default value"
  525. );
  526. static void print_serdes_mux(void)
  527. {
  528. char current_serdes;
  529. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  530. current_serdes = cpld_data->serdes_mux;
  531. printf("Serdes Lane B: ");
  532. if ((current_serdes & MASK_LANE_B) == 0)
  533. printf("SATA,\n");
  534. else
  535. printf("SGMII 1,\n");
  536. printf("Serdes Lane C: ");
  537. if ((current_serdes & MASK_LANE_C) == 0)
  538. printf("SGMII 1,\n");
  539. else
  540. printf("PCIe,\n");
  541. printf("Serdes Lane D: ");
  542. if ((current_serdes & MASK_LANE_D) == 0)
  543. printf("PCIe,\n");
  544. else
  545. printf("SGMII 2,\n");
  546. printf("SGMII 1 is on lane ");
  547. if ((current_serdes & MASK_SGMII) == 0)
  548. printf("C.\n");
  549. else
  550. printf("B.\n");
  551. }
  552. static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  553. char * const argv[])
  554. {
  555. if (argc != 2)
  556. return CMD_RET_USAGE;
  557. if (strcmp(argv[1], "sata") == 0) {
  558. printf("Set serdes lane B to SATA.\n");
  559. convert_serdes_mux(LANEB_SATA, NEED_RESET);
  560. } else if (strcmp(argv[1], "sgmii1b") == 0) {
  561. printf("Set serdes lane B to SGMII 1.\n");
  562. convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
  563. } else if (strcmp(argv[1], "sgmii1c") == 0) {
  564. printf("Set serdes lane C to SGMII 1.\n");
  565. convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
  566. } else if (strcmp(argv[1], "sgmii2") == 0) {
  567. printf("Set serdes lane D to SGMII 2.\n");
  568. convert_serdes_mux(LANED_SGMII2, NEED_RESET);
  569. } else if (strcmp(argv[1], "pciex1") == 0) {
  570. printf("Set serdes lane C to PCIe X1.\n");
  571. convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
  572. } else if (strcmp(argv[1], "pciex2") == 0) {
  573. printf("Set serdes lane C & lane D to PCIe X2.\n");
  574. convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
  575. } else if (strcmp(argv[1], "show") == 0) {
  576. print_serdes_mux();
  577. } else {
  578. return CMD_RET_USAGE;
  579. }
  580. return 0;
  581. }
  582. U_BOOT_CMD(
  583. lane_bank, 2, 0, serdes_mux_cmd,
  584. "Multiplexed function setting for SerDes Lanes",
  585. "sata\n"
  586. " -change lane B to sata\n"
  587. "lane_bank sgmii1b\n"
  588. " -change lane B to SGMII1\n"
  589. "lane_bank sgmii1c\n"
  590. " -change lane C to SGMII1\n"
  591. "lane_bank sgmii2\n"
  592. " -change lane D to SGMII2\n"
  593. "lane_bank pciex1\n"
  594. " -change lane C to PCIeX1\n"
  595. "lane_bank pciex2\n"
  596. " -change lane C & lane D to PCIeX2\n"
  597. "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
  598. );
  599. #endif