ls1021aqds.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/immap_ls102xa.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/arch/ls102xa_soc.h>
  14. #include <asm/arch/ls102xa_devdis.h>
  15. #include <hwconfig.h>
  16. #include <mmc.h>
  17. #include <fsl_csu.h>
  18. #include <fsl_ifc.h>
  19. #include <fsl_sec.h>
  20. #include <spl.h>
  21. #include <fsl_devdis.h>
  22. #include <fsl_validate.h>
  23. #include <fsl_ddr.h>
  24. #include "../common/sleep.h"
  25. #include "../common/qixis.h"
  26. #include "ls1021aqds_qixis.h"
  27. #ifdef CONFIG_U_QE
  28. #include <fsl_qe.h>
  29. #endif
  30. #define PIN_MUX_SEL_CAN 0x03
  31. #define PIN_MUX_SEL_IIC2 0xa0
  32. #define PIN_MUX_SEL_RGMII 0x00
  33. #define PIN_MUX_SEL_SAI 0x0c
  34. #define PIN_MUX_SEL_SDHC 0x00
  35. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
  36. #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  37. enum {
  38. MUX_TYPE_CAN,
  39. MUX_TYPE_IIC2,
  40. MUX_TYPE_RGMII,
  41. MUX_TYPE_SAI,
  42. MUX_TYPE_SDHC,
  43. MUX_TYPE_SD_PCI4,
  44. MUX_TYPE_SD_PC_SA_SG_SG,
  45. MUX_TYPE_SD_PC_SA_PC_SG,
  46. MUX_TYPE_SD_PC_SG_SG,
  47. };
  48. enum {
  49. GE0_CLK125,
  50. GE2_CLK125,
  51. GE1_CLK125,
  52. };
  53. int checkboard(void)
  54. {
  55. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  56. char buf[64];
  57. #endif
  58. #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  59. u8 sw;
  60. #endif
  61. puts("Board: LS1021AQDS\n");
  62. #ifdef CONFIG_SD_BOOT
  63. puts("SD\n");
  64. #elif CONFIG_QSPI_BOOT
  65. puts("QSPI\n");
  66. #else
  67. sw = QIXIS_READ(brdcfg[0]);
  68. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  69. if (sw < 0x8)
  70. printf("vBank: %d\n", sw);
  71. else if (sw == 0x8)
  72. puts("PromJet\n");
  73. else if (sw == 0x9)
  74. puts("NAND\n");
  75. else if (sw == 0x15)
  76. printf("IFCCard\n");
  77. else
  78. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  79. #endif
  80. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  81. printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  82. QIXIS_READ(id), QIXIS_READ(arch));
  83. printf("FPGA: v%d (%s), build %d\n",
  84. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  85. (int)qixis_read_minor());
  86. #endif
  87. return 0;
  88. }
  89. unsigned long get_board_sys_clk(void)
  90. {
  91. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  92. switch (sysclk_conf & 0x0f) {
  93. case QIXIS_SYSCLK_64:
  94. return 64000000;
  95. case QIXIS_SYSCLK_83:
  96. return 83333333;
  97. case QIXIS_SYSCLK_100:
  98. return 100000000;
  99. case QIXIS_SYSCLK_125:
  100. return 125000000;
  101. case QIXIS_SYSCLK_133:
  102. return 133333333;
  103. case QIXIS_SYSCLK_150:
  104. return 150000000;
  105. case QIXIS_SYSCLK_160:
  106. return 160000000;
  107. case QIXIS_SYSCLK_166:
  108. return 166666666;
  109. }
  110. return 66666666;
  111. }
  112. unsigned long get_board_ddr_clk(void)
  113. {
  114. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  115. switch ((ddrclk_conf & 0x30) >> 4) {
  116. case QIXIS_DDRCLK_100:
  117. return 100000000;
  118. case QIXIS_DDRCLK_125:
  119. return 125000000;
  120. case QIXIS_DDRCLK_133:
  121. return 133333333;
  122. }
  123. return 66666666;
  124. }
  125. int select_i2c_ch_pca9547(u8 ch)
  126. {
  127. int ret;
  128. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  129. if (ret) {
  130. puts("PCA: failed to select proper channel\n");
  131. return ret;
  132. }
  133. return 0;
  134. }
  135. int dram_init(void)
  136. {
  137. /*
  138. * When resuming from deep sleep, the I2C channel may not be
  139. * in the default channel. So, switch to the default channel
  140. * before accessing DDR SPD.
  141. */
  142. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  143. return fsl_initdram();
  144. }
  145. int board_early_init_f(void)
  146. {
  147. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  148. #ifdef CONFIG_TSEC_ENET
  149. /* clear BD & FR bits for BE BD's and frame data */
  150. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  151. #endif
  152. #ifdef CONFIG_FSL_IFC
  153. init_early_memctl_regs();
  154. #endif
  155. arch_soc_init();
  156. #if defined(CONFIG_DEEP_SLEEP)
  157. if (is_warm_boot())
  158. fsl_dp_disable_console();
  159. #endif
  160. return 0;
  161. }
  162. #ifdef CONFIG_SPL_BUILD
  163. void board_init_f(ulong dummy)
  164. {
  165. #ifdef CONFIG_NAND_BOOT
  166. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  167. u32 porsr1, pinctl;
  168. /*
  169. * There is LS1 SoC issue where NOR, FPGA are inaccessible during
  170. * NAND boot because IFC signals > IFC_AD7 are not enabled.
  171. * This workaround changes RCW source to make all signals enabled.
  172. */
  173. porsr1 = in_be32(&gur->porsr1);
  174. pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
  175. DCFG_CCSR_PORSR1_RCW_SRC_I2C);
  176. out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  177. pinctl);
  178. #endif
  179. /* Clear the BSS */
  180. memset(__bss_start, 0, __bss_end - __bss_start);
  181. #ifdef CONFIG_FSL_IFC
  182. init_early_memctl_regs();
  183. #endif
  184. get_clocks();
  185. #if defined(CONFIG_DEEP_SLEEP)
  186. if (is_warm_boot())
  187. fsl_dp_disable_console();
  188. #endif
  189. preloader_console_init();
  190. #ifdef CONFIG_SPL_I2C_SUPPORT
  191. i2c_init_all();
  192. #endif
  193. timer_init();
  194. dram_init();
  195. /* Allow OCRAM access permission as R/W */
  196. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  197. enable_layerscape_ns_access();
  198. #endif
  199. board_init_r(NULL, 0);
  200. }
  201. #endif
  202. void config_etseccm_source(int etsec_gtx_125_mux)
  203. {
  204. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  205. switch (etsec_gtx_125_mux) {
  206. case GE0_CLK125:
  207. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
  208. debug("etseccm set to GE0_CLK125\n");
  209. break;
  210. case GE2_CLK125:
  211. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  212. debug("etseccm set to GE2_CLK125\n");
  213. break;
  214. case GE1_CLK125:
  215. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
  216. debug("etseccm set to GE1_CLK125\n");
  217. break;
  218. default:
  219. printf("Error! trying to set etseccm to invalid value\n");
  220. break;
  221. }
  222. }
  223. int config_board_mux(int ctrl_type)
  224. {
  225. u8 reg12, reg14;
  226. reg12 = QIXIS_READ(brdcfg[12]);
  227. reg14 = QIXIS_READ(brdcfg[14]);
  228. switch (ctrl_type) {
  229. case MUX_TYPE_CAN:
  230. config_etseccm_source(GE2_CLK125);
  231. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
  232. break;
  233. case MUX_TYPE_IIC2:
  234. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
  235. break;
  236. case MUX_TYPE_RGMII:
  237. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
  238. break;
  239. case MUX_TYPE_SAI:
  240. config_etseccm_source(GE2_CLK125);
  241. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
  242. break;
  243. case MUX_TYPE_SDHC:
  244. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
  245. break;
  246. case MUX_TYPE_SD_PCI4:
  247. reg12 = 0x38;
  248. break;
  249. case MUX_TYPE_SD_PC_SA_SG_SG:
  250. reg12 = 0x01;
  251. break;
  252. case MUX_TYPE_SD_PC_SA_PC_SG:
  253. reg12 = 0x01;
  254. break;
  255. case MUX_TYPE_SD_PC_SG_SG:
  256. reg12 = 0x21;
  257. break;
  258. default:
  259. printf("Wrong mux interface type\n");
  260. return -1;
  261. }
  262. QIXIS_WRITE(brdcfg[12], reg12);
  263. QIXIS_WRITE(brdcfg[14], reg14);
  264. return 0;
  265. }
  266. int config_serdes_mux(void)
  267. {
  268. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  269. u32 cfg;
  270. cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  271. cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  272. switch (cfg) {
  273. case 0x0:
  274. config_board_mux(MUX_TYPE_SD_PCI4);
  275. break;
  276. case 0x30:
  277. config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
  278. break;
  279. case 0x60:
  280. config_board_mux(MUX_TYPE_SD_PC_SG_SG);
  281. break;
  282. case 0x70:
  283. config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
  284. break;
  285. default:
  286. printf("SRDS1 prtcl:0x%x\n", cfg);
  287. break;
  288. }
  289. return 0;
  290. }
  291. #ifdef CONFIG_BOARD_LATE_INIT
  292. int board_late_init(void)
  293. {
  294. #ifdef CONFIG_CHAIN_OF_TRUST
  295. fsl_setenv_chain_of_trust();
  296. #endif
  297. return 0;
  298. }
  299. #endif
  300. int misc_init_r(void)
  301. {
  302. int conflict_flag;
  303. /* some signals can not enable simultaneous*/
  304. conflict_flag = 0;
  305. if (hwconfig("sdhc"))
  306. conflict_flag++;
  307. if (hwconfig("iic2"))
  308. conflict_flag++;
  309. if (conflict_flag > 1) {
  310. printf("WARNING: pin conflict !\n");
  311. return 0;
  312. }
  313. conflict_flag = 0;
  314. if (hwconfig("rgmii"))
  315. conflict_flag++;
  316. if (hwconfig("can"))
  317. conflict_flag++;
  318. if (hwconfig("sai"))
  319. conflict_flag++;
  320. if (conflict_flag > 1) {
  321. printf("WARNING: pin conflict !\n");
  322. return 0;
  323. }
  324. if (hwconfig("can"))
  325. config_board_mux(MUX_TYPE_CAN);
  326. else if (hwconfig("rgmii"))
  327. config_board_mux(MUX_TYPE_RGMII);
  328. else if (hwconfig("sai"))
  329. config_board_mux(MUX_TYPE_SAI);
  330. if (hwconfig("iic2"))
  331. config_board_mux(MUX_TYPE_IIC2);
  332. else if (hwconfig("sdhc"))
  333. config_board_mux(MUX_TYPE_SDHC);
  334. #ifdef CONFIG_FSL_DEVICE_DISABLE
  335. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  336. #endif
  337. #ifdef CONFIG_FSL_CAAM
  338. return sec_init();
  339. #endif
  340. return 0;
  341. }
  342. int board_init(void)
  343. {
  344. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  345. erratum_a010315();
  346. #endif
  347. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  348. erratum_a009942_check_cpo();
  349. #endif
  350. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  351. #ifndef CONFIG_SYS_FSL_NO_SERDES
  352. fsl_serdes_init();
  353. config_serdes_mux();
  354. #endif
  355. ls102xa_smmu_stream_id_init();
  356. #ifdef CONFIG_U_QE
  357. u_qe_init();
  358. #endif
  359. return 0;
  360. }
  361. #if defined(CONFIG_DEEP_SLEEP)
  362. void board_sleep_prepare(void)
  363. {
  364. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  365. enable_layerscape_ns_access();
  366. #endif
  367. }
  368. #endif
  369. int ft_board_setup(void *blob, bd_t *bd)
  370. {
  371. ft_cpu_setup(blob, bd);
  372. #ifdef CONFIG_PCI
  373. ft_pci_setup(blob, bd);
  374. #endif
  375. return 0;
  376. }
  377. u8 flash_read8(void *addr)
  378. {
  379. return __raw_readb(addr + 1);
  380. }
  381. void flash_write16(u16 val, void *addr)
  382. {
  383. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  384. __raw_writew(shftval, addr);
  385. }
  386. u16 flash_read16(void *addr)
  387. {
  388. u16 val = __raw_readw(addr);
  389. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  390. }