ls1021aiot.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <asm/arch/immap_ls102xa.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/ls102xa_stream_id.h>
  12. #include <asm/arch/ls102xa_devdis.h>
  13. #include <asm/arch/ls102xa_soc.h>
  14. #include <fsl_csu.h>
  15. #include <fsl_immap.h>
  16. #include <netdev.h>
  17. #include <fsl_mdio.h>
  18. #include <tsec.h>
  19. #include <spl.h>
  20. #include <fsl_validate.h>
  21. #include "../common/sleep.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define DDR_SIZE 0x40000000
  24. int checkboard(void)
  25. {
  26. puts("Board: LS1021AIOT\n");
  27. #ifndef CONFIG_QSPI_BOOT
  28. struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  29. u32 cpldrev;
  30. cpldrev = in_be32(&dcfg->gpporcr1);
  31. printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
  32. 0xf));
  33. #endif
  34. return 0;
  35. }
  36. void ddrmc_init(void)
  37. {
  38. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  39. u32 temp_sdram_cfg, tmp;
  40. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  41. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  42. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  43. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  44. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  45. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  46. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  47. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  48. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  49. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  50. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  51. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  52. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  53. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  54. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  55. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  56. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  57. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  58. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  59. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  60. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  61. /* DDR erratum A-009942 */
  62. tmp = in_be32(&ddr->debug[28]);
  63. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  64. udelay(500);
  65. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  66. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  67. }
  68. int dram_init(void)
  69. {
  70. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  71. ddrmc_init();
  72. #endif
  73. erratum_a008850_post();
  74. gd->ram_size = DDR_SIZE;
  75. return 0;
  76. }
  77. #ifdef CONFIG_TSEC_ENET
  78. int board_eth_init(bd_t *bis)
  79. {
  80. struct fsl_pq_mdio_info mdio_info;
  81. struct tsec_info_struct tsec_info[4];
  82. int num = 0;
  83. #ifdef CONFIG_TSEC1
  84. SET_STD_TSEC_INFO(tsec_info[num], 1);
  85. if (is_serdes_configured(SGMII_TSEC1)) {
  86. puts("eTSEC1 is in sgmii mode.\n");
  87. tsec_info[num].flags |= TSEC_SGMII;
  88. }
  89. num++;
  90. #endif
  91. #ifdef CONFIG_TSEC2
  92. SET_STD_TSEC_INFO(tsec_info[num], 2);
  93. if (is_serdes_configured(SGMII_TSEC2)) {
  94. puts("eTSEC2 is in sgmii mode.\n");
  95. tsec_info[num].flags |= TSEC_SGMII;
  96. }
  97. num++;
  98. #endif
  99. if (!num) {
  100. printf("No TSECs initialized\n");
  101. return 0;
  102. }
  103. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  104. mdio_info.name = DEFAULT_MII_NAME;
  105. fsl_pq_mdio_init(bis, &mdio_info);
  106. tsec_eth_init(bis, tsec_info, num);
  107. return pci_eth_init(bis);
  108. }
  109. #endif
  110. int board_early_init_f(void)
  111. {
  112. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  113. #ifdef CONFIG_TSEC_ENET
  114. /* clear BD & FR bits for BE BD's and frame data */
  115. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  116. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  117. #endif
  118. arch_soc_init();
  119. return 0;
  120. }
  121. #ifdef CONFIG_SPL_BUILD
  122. void board_init_f(ulong dummy)
  123. {
  124. /* Clear the BSS */
  125. memset(__bss_start, 0, __bss_end - __bss_start);
  126. get_clocks();
  127. preloader_console_init();
  128. dram_init();
  129. /* Allow OCRAM access permission as R/W */
  130. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  131. enable_layerscape_ns_access();
  132. #endif
  133. board_init_r(NULL, 0);
  134. }
  135. #endif
  136. int board_init(void)
  137. {
  138. #ifndef CONFIG_SYS_FSL_NO_SERDES
  139. fsl_serdes_init();
  140. #endif
  141. ls102xa_smmu_stream_id_init();
  142. return 0;
  143. }
  144. #ifdef CONFIG_BOARD_LATE_INIT
  145. int board_late_init(void)
  146. {
  147. return 0;
  148. }
  149. #endif
  150. #if defined(CONFIG_MISC_INIT_R)
  151. int misc_init_r(void)
  152. {
  153. #ifdef CONFIG_FSL_DEVICE_DISABLE
  154. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  155. #endif
  156. #ifdef CONFIG_FSL_CAAM
  157. return sec_init();
  158. #endif
  159. }
  160. #endif
  161. int ft_board_setup(void *blob, bd_t *bd)
  162. {
  163. ft_cpu_setup(blob, bd);
  164. #ifdef CONFIG_PCI
  165. ft_pci_setup(blob, bd);
  166. #endif
  167. return 0;
  168. }
  169. void flash_write16(u16 val, void *addr)
  170. {
  171. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  172. __raw_writew(shftval, addr);
  173. }
  174. u16 flash_read16(void *addr)
  175. {
  176. u16 val = __raw_readw(addr);
  177. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  178. }