ls1012ardb.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <i2c.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #ifdef CONFIG_FSL_LS_PPA
  12. #include <asm/arch/ppa.h>
  13. #endif
  14. #include <asm/arch/mmu.h>
  15. #include <asm/arch/soc.h>
  16. #include <hwconfig.h>
  17. #include <ahci.h>
  18. #include <mmc.h>
  19. #include <scsi.h>
  20. #include <fsl_esdhc.h>
  21. #include <env_internal.h>
  22. #include <fsl_mmdc.h>
  23. #include <netdev.h>
  24. #include <fsl_sec.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define BOOT_FROM_UPPER_BANK 0x2
  27. #define BOOT_FROM_LOWER_BANK 0x1
  28. int checkboard(void)
  29. {
  30. #ifdef CONFIG_TARGET_LS1012ARDB
  31. u8 in1;
  32. puts("Board: LS1012ARDB ");
  33. /* Initialize i2c early for Serial flash bank information */
  34. i2c_set_bus_num(0);
  35. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) {
  36. printf("Error reading i2c boot information!\n");
  37. return 0; /* Don't want to hang() on this error */
  38. }
  39. puts("Version");
  40. switch (in1 & SW_REV_MASK) {
  41. case SW_REV_A:
  42. puts(": RevA");
  43. break;
  44. case SW_REV_B:
  45. puts(": RevB");
  46. break;
  47. case SW_REV_C:
  48. puts(": RevC");
  49. break;
  50. case SW_REV_C1:
  51. puts(": RevC1");
  52. break;
  53. case SW_REV_C2:
  54. puts(": RevC2");
  55. break;
  56. case SW_REV_D:
  57. puts(": RevD");
  58. break;
  59. case SW_REV_E:
  60. puts(": RevE");
  61. break;
  62. default:
  63. puts(": unknown");
  64. break;
  65. }
  66. printf(", boot from QSPI");
  67. if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
  68. puts(": emu\n");
  69. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
  70. puts(": bank1\n");
  71. else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
  72. puts(": bank2\n");
  73. else
  74. puts("unknown\n");
  75. #else
  76. puts("Board: LS1012A2G5RDB ");
  77. #endif
  78. return 0;
  79. }
  80. #ifdef CONFIG_TFABOOT
  81. int dram_init(void)
  82. {
  83. gd->ram_size = tfa_get_dram_size();
  84. if (!gd->ram_size)
  85. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  86. return 0;
  87. }
  88. #else
  89. int dram_init(void)
  90. {
  91. #ifndef CONFIG_TFABOOT
  92. static const struct fsl_mmdc_info mparam = {
  93. 0x05180000, /* mdctl */
  94. 0x00030035, /* mdpdc */
  95. 0x12554000, /* mdotc */
  96. 0xbabf7954, /* mdcfg0 */
  97. 0xdb328f64, /* mdcfg1 */
  98. 0x01ff00db, /* mdcfg2 */
  99. 0x00001680, /* mdmisc */
  100. 0x0f3c8000, /* mdref */
  101. 0x00002000, /* mdrwd */
  102. 0x00bf1023, /* mdor */
  103. 0x0000003f, /* mdasp */
  104. 0x0000022a, /* mpodtctrl */
  105. 0xa1390003, /* mpzqhwctrl */
  106. };
  107. mmdc_init(&mparam);
  108. #endif
  109. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  110. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  111. /* This will break-before-make MMU for DDR */
  112. update_early_mmu_table();
  113. #endif
  114. return 0;
  115. }
  116. #endif
  117. int board_early_init_f(void)
  118. {
  119. fsl_lsch2_early_init_f();
  120. return 0;
  121. }
  122. int board_init(void)
  123. {
  124. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  125. CONFIG_SYS_CCI400_OFFSET);
  126. /*
  127. * Set CCI-400 control override register to enable barrier
  128. * transaction
  129. */
  130. if (current_el() == 3)
  131. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  132. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  133. erratum_a010315();
  134. #endif
  135. #ifdef CONFIG_ENV_IS_NOWHERE
  136. gd->env_addr = (ulong)&default_environment[0];
  137. #endif
  138. #ifdef CONFIG_FSL_CAAM
  139. sec_init();
  140. #endif
  141. #ifdef CONFIG_FSL_LS_PPA
  142. ppa_init();
  143. #endif
  144. return 0;
  145. }
  146. #ifdef CONFIG_TARGET_LS1012ARDB
  147. int esdhc_status_fixup(void *blob, const char *compat)
  148. {
  149. char esdhc1_path[] = "/soc/esdhc@1580000";
  150. bool sdhc2_en = false;
  151. u8 mux_sdhc2;
  152. u8 io = 0;
  153. i2c_set_bus_num(0);
  154. /* IO1[7:3] is the field of board revision info. */
  155. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) {
  156. printf("Error reading i2c boot information!\n");
  157. return 0;
  158. }
  159. /* hwconfig method is used for RevD and later versions. */
  160. if ((io & SW_REV_MASK) <= SW_REV_D) {
  161. #ifdef CONFIG_HWCONFIG
  162. if (hwconfig("esdhc1"))
  163. sdhc2_en = true;
  164. #endif
  165. } else {
  166. /*
  167. * The I2C IO-expander for mux select is used to control
  168. * the muxing of various onboard interfaces.
  169. *
  170. * IO0[3:2] indicates SDHC2 interface demultiplexer
  171. * select lines.
  172. * 00 - SDIO wifi
  173. * 01 - GPIO (to Arduino)
  174. * 10 - eMMC Memory
  175. * 11 - SPI
  176. */
  177. if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) {
  178. printf("Error reading i2c boot information!\n");
  179. return 0;
  180. }
  181. mux_sdhc2 = (io & 0x0c) >> 2;
  182. /* Enable SDHC2 only when use SDIO wifi and eMMC */
  183. if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
  184. sdhc2_en = true;
  185. }
  186. if (sdhc2_en)
  187. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  188. sizeof("okay"), 1);
  189. else
  190. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  191. sizeof("disabled"), 1);
  192. return 0;
  193. }
  194. #endif
  195. int ft_board_setup(void *blob, bd_t *bd)
  196. {
  197. arch_fixup_fdt(blob);
  198. ft_cpu_setup(blob, bd);
  199. return 0;
  200. }
  201. static int switch_to_bank1(void)
  202. {
  203. u8 data;
  204. int ret;
  205. i2c_set_bus_num(0);
  206. data = 0xf4;
  207. ret = i2c_write(0x24, 0x3, 1, &data, 1);
  208. if (ret) {
  209. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  210. 0x24, 0x3, data);
  211. }
  212. return ret;
  213. }
  214. static int switch_to_bank2(void)
  215. {
  216. u8 data;
  217. int ret;
  218. i2c_set_bus_num(0);
  219. data = 0xfc;
  220. ret = i2c_write(0x24, 0x7, 1, &data, 1);
  221. if (ret) {
  222. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  223. 0x24, 0x7, data);
  224. goto err;
  225. }
  226. data = 0xf5;
  227. ret = i2c_write(0x24, 0x3, 1, &data, 1);
  228. if (ret) {
  229. printf("i2c write error to chip : %u, addr : %u, data : %u\n",
  230. 0x24, 0x3, data);
  231. }
  232. err:
  233. return ret;
  234. }
  235. static int convert_flash_bank(int bank)
  236. {
  237. int ret = 0;
  238. switch (bank) {
  239. case BOOT_FROM_UPPER_BANK:
  240. ret = switch_to_bank2();
  241. break;
  242. case BOOT_FROM_LOWER_BANK:
  243. ret = switch_to_bank1();
  244. break;
  245. default:
  246. ret = CMD_RET_USAGE;
  247. break;
  248. };
  249. return ret;
  250. }
  251. static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  252. char * const argv[])
  253. {
  254. if (argc != 2)
  255. return CMD_RET_USAGE;
  256. if (strcmp(argv[1], "1") == 0)
  257. convert_flash_bank(BOOT_FROM_LOWER_BANK);
  258. else if (strcmp(argv[1], "2") == 0)
  259. convert_flash_bank(BOOT_FROM_UPPER_BANK);
  260. else
  261. return CMD_RET_USAGE;
  262. return 0;
  263. }
  264. U_BOOT_CMD(
  265. boot_bank, 2, 0, flash_bank_cmd,
  266. "Flash bank Selection Control",
  267. "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
  268. );