corenet_ds.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <fm_eth.h>
  20. #include "../common/ngpixis.h"
  21. #include "corenet_ds.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int checkboard (void)
  24. {
  25. u8 sw;
  26. struct cpu_type *cpu = gd->arch.cpu;
  27. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  28. defined(CONFIG_TARGET_P5040DS)
  29. unsigned int i;
  30. #endif
  31. static const char * const freq[] = {"100", "125", "156.25", "212.5" };
  32. printf("Board: %sDS, ", cpu->name);
  33. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  34. in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  35. sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  36. sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  37. if (sw < 0x8)
  38. printf("vBank: %d\n", sw);
  39. else if (sw == 0x8)
  40. puts("Promjet\n");
  41. else if (sw == 0x9)
  42. puts("NAND\n");
  43. else
  44. printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
  45. /* Display the actual SERDES reference clocks as configured by the
  46. * dip switches on the board. Note that the SWx registers could
  47. * technically be set to force the reference clocks to match the
  48. * values that the SERDES expects (or vice versa). For now, however,
  49. * we just display both values and hope the user notices when they
  50. * don't match.
  51. */
  52. puts("SERDES Reference Clocks: ");
  53. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  54. defined(CONFIG_TARGET_P5040DS)
  55. sw = in_8(&PIXIS_SW(5));
  56. for (i = 0; i < 3; i++) {
  57. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  58. printf("Bank%u=%sMhz ", i+1, freq[clock]);
  59. }
  60. #ifdef CONFIG_TARGET_P5040DS
  61. /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
  62. sw = in_8(&PIXIS_SW(9));
  63. printf("Bank4=%sMhz ", freq[sw & 3]);
  64. #endif
  65. puts("\n");
  66. #else
  67. sw = in_8(&PIXIS_SW(3));
  68. /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
  69. /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
  70. /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
  71. printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
  72. printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
  73. printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
  74. #endif
  75. return 0;
  76. }
  77. int board_early_init_f(void)
  78. {
  79. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  80. /*
  81. * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
  82. * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  83. * the noise introduced by these unterminated and unused clock pairs.
  84. */
  85. setbits_be32(&gur->ddrclkdr, 0x001B001B);
  86. return 0;
  87. }
  88. int board_early_init_r(void)
  89. {
  90. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  91. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  92. /*
  93. * Remap Boot flash + PROMJET region to caching-inhibited
  94. * so that flash can be erased properly.
  95. */
  96. /* Flush d-cache and invalidate i-cache of any FLASH data */
  97. flush_dcache();
  98. invalidate_icache();
  99. if (flash_esel == -1) {
  100. /* very unlikely unless something is messed up */
  101. puts("Error: Could not find TLB for FLASH BASE\n");
  102. flash_esel = 2; /* give our best effort to continue */
  103. } else {
  104. /* invalidate existing TLB entry for flash + promjet */
  105. disable_tlb(flash_esel);
  106. }
  107. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  108. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  109. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  110. return 0;
  111. }
  112. #define NUM_SRDS_BANKS 3
  113. int misc_init_r(void)
  114. {
  115. serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  116. u32 actual[NUM_SRDS_BANKS];
  117. unsigned int i;
  118. u8 sw;
  119. #if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
  120. defined(CONFIG_TARGET_P5040DS)
  121. sw = in_8(&PIXIS_SW(5));
  122. for (i = 0; i < 3; i++) {
  123. unsigned int clock = (sw >> (6 - (2 * i))) & 3;
  124. switch (clock) {
  125. case 0:
  126. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  127. break;
  128. case 1:
  129. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  130. break;
  131. case 2:
  132. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  133. break;
  134. default:
  135. printf("Warning: SDREFCLK%u switch setting of '11' is "
  136. "unsupported\n", i + 1);
  137. break;
  138. }
  139. }
  140. #else
  141. /* Warn if the expected SERDES reference clocks don't match the
  142. * actual reference clocks. This needs to be done after calling
  143. * p4080_erratum_serdes8(), since that function may modify the clocks.
  144. */
  145. sw = in_8(&PIXIS_SW(3));
  146. actual[0] = (sw & 0x40) ?
  147. SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
  148. actual[1] = (sw & 0x20) ?
  149. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  150. actual[2] = (sw & 0x10) ?
  151. SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
  152. #endif
  153. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  154. u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  155. if (expected != actual[i]) {
  156. printf("Warning: SERDES bank %u expects reference clock"
  157. " %sMHz, but actual is %sMHz\n", i + 1,
  158. serdes_clock_to_string(expected),
  159. serdes_clock_to_string(actual[i]));
  160. }
  161. }
  162. return 0;
  163. }
  164. int ft_board_setup(void *blob, bd_t *bd)
  165. {
  166. phys_addr_t base;
  167. phys_size_t size;
  168. ft_cpu_setup(blob, bd);
  169. base = env_get_bootm_low();
  170. size = env_get_bootm_size();
  171. fdt_fixup_memory(blob, (u64)base, (u64)size);
  172. #ifdef CONFIG_PCI
  173. pci_of_setup(blob, bd);
  174. #endif
  175. fdt_fixup_liodn(blob);
  176. fsl_fdt_fixup_dr_usb(blob, bd);
  177. #ifdef CONFIG_SYS_DPAA_FMAN
  178. fdt_fixup_fman_ethernet(blob);
  179. fdt_fixup_board_enet(blob);
  180. #endif
  181. return 0;
  182. }