ufs.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef __UFS_H
  3. #define __UFS_H
  4. #include <asm/io.h>
  5. #include <dm.h>
  6. #include "unipro.h"
  7. #define UFS_CDB_SIZE 16
  8. #define UPIU_TRANSACTION_UIC_CMD 0x1F
  9. #define UIC_CMD_SIZE (sizeof(u32) * 4)
  10. #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
  11. #define UFS_MAX_LUNS 0x7F
  12. enum {
  13. TASK_REQ_UPIU_SIZE_DWORDS = 8,
  14. TASK_RSP_UPIU_SIZE_DWORDS = 8,
  15. ALIGNED_UPIU_SIZE = 512,
  16. };
  17. /* UFS device power modes */
  18. enum ufs_dev_pwr_mode {
  19. UFS_ACTIVE_PWR_MODE = 1,
  20. UFS_SLEEP_PWR_MODE = 2,
  21. UFS_POWERDOWN_PWR_MODE = 3,
  22. };
  23. enum ufs_notify_change_status {
  24. PRE_CHANGE,
  25. POST_CHANGE,
  26. };
  27. struct ufs_pa_layer_attr {
  28. u32 gear_rx;
  29. u32 gear_tx;
  30. u32 lane_rx;
  31. u32 lane_tx;
  32. u32 pwr_rx;
  33. u32 pwr_tx;
  34. u32 hs_rate;
  35. };
  36. struct ufs_pwr_mode_info {
  37. bool is_valid;
  38. struct ufs_pa_layer_attr info;
  39. };
  40. enum ufs_desc_def_size {
  41. QUERY_DESC_DEVICE_DEF_SIZE = 0x40,
  42. QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90,
  43. QUERY_DESC_UNIT_DEF_SIZE = 0x23,
  44. QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06,
  45. QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48,
  46. QUERY_DESC_POWER_DEF_SIZE = 0x62,
  47. QUERY_DESC_HEALTH_DEF_SIZE = 0x25,
  48. };
  49. struct ufs_desc_size {
  50. int dev_desc;
  51. int pwr_desc;
  52. int geom_desc;
  53. int interc_desc;
  54. int unit_desc;
  55. int conf_desc;
  56. int hlth_desc;
  57. };
  58. /*
  59. * Request Descriptor Definitions
  60. */
  61. /* Transfer request command type */
  62. enum {
  63. UTP_CMD_TYPE_SCSI = 0x0,
  64. UTP_CMD_TYPE_UFS = 0x1,
  65. UTP_CMD_TYPE_DEV_MANAGE = 0x2,
  66. };
  67. /* UTP Transfer Request Command Offset */
  68. #define UPIU_COMMAND_TYPE_OFFSET 28
  69. /* Offset of the response code in the UPIU header */
  70. #define UPIU_RSP_CODE_OFFSET 8
  71. /* To accommodate UFS2.0 required Command type */
  72. enum {
  73. UTP_CMD_TYPE_UFS_STORAGE = 0x1,
  74. };
  75. enum {
  76. UTP_SCSI_COMMAND = 0x00000000,
  77. UTP_NATIVE_UFS_COMMAND = 0x10000000,
  78. UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
  79. UTP_REQ_DESC_INT_CMD = 0x01000000,
  80. };
  81. /* UTP Transfer Request Data Direction (DD) */
  82. enum {
  83. UTP_NO_DATA_TRANSFER = 0x00000000,
  84. UTP_HOST_TO_DEVICE = 0x02000000,
  85. UTP_DEVICE_TO_HOST = 0x04000000,
  86. };
  87. /* Overall command status values */
  88. enum {
  89. OCS_SUCCESS = 0x0,
  90. OCS_INVALID_CMD_TABLE_ATTR = 0x1,
  91. OCS_INVALID_PRDT_ATTR = 0x2,
  92. OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
  93. OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
  94. OCS_PEER_COMM_FAILURE = 0x5,
  95. OCS_ABORTED = 0x6,
  96. OCS_FATAL_ERROR = 0x7,
  97. OCS_INVALID_COMMAND_STATUS = 0x0F,
  98. MASK_OCS = 0x0F,
  99. };
  100. /* The maximum length of the data byte count field in the PRDT is 256KB */
  101. #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
  102. /* The granularity of the data byte count field in the PRDT is 32-bit */
  103. #define PRDT_DATA_BYTE_COUNT_PAD 4
  104. #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
  105. #define QUERY_DESC_MAX_SIZE 255
  106. #define QUERY_DESC_MIN_SIZE 2
  107. #define QUERY_DESC_HDR_SIZE 2
  108. #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
  109. (sizeof(struct utp_upiu_header)))
  110. #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
  111. #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
  112. cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
  113. (byte1 << 8) | (byte0))
  114. /*
  115. * UFS Protocol Information Unit related definitions
  116. */
  117. /* Task management functions */
  118. enum {
  119. UFS_ABORT_TASK = 0x01,
  120. UFS_ABORT_TASK_SET = 0x02,
  121. UFS_CLEAR_TASK_SET = 0x04,
  122. UFS_LOGICAL_RESET = 0x08,
  123. UFS_QUERY_TASK = 0x80,
  124. UFS_QUERY_TASK_SET = 0x81,
  125. };
  126. /* UTP UPIU Transaction Codes Initiator to Target */
  127. enum {
  128. UPIU_TRANSACTION_NOP_OUT = 0x00,
  129. UPIU_TRANSACTION_COMMAND = 0x01,
  130. UPIU_TRANSACTION_DATA_OUT = 0x02,
  131. UPIU_TRANSACTION_TASK_REQ = 0x04,
  132. UPIU_TRANSACTION_QUERY_REQ = 0x16,
  133. };
  134. /* UTP UPIU Transaction Codes Target to Initiator */
  135. enum {
  136. UPIU_TRANSACTION_NOP_IN = 0x20,
  137. UPIU_TRANSACTION_RESPONSE = 0x21,
  138. UPIU_TRANSACTION_DATA_IN = 0x22,
  139. UPIU_TRANSACTION_TASK_RSP = 0x24,
  140. UPIU_TRANSACTION_READY_XFER = 0x31,
  141. UPIU_TRANSACTION_QUERY_RSP = 0x36,
  142. UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
  143. };
  144. /* UPIU Read/Write flags */
  145. enum {
  146. UPIU_CMD_FLAGS_NONE = 0x00,
  147. UPIU_CMD_FLAGS_WRITE = 0x20,
  148. UPIU_CMD_FLAGS_READ = 0x40,
  149. };
  150. /* UPIU Task Attributes */
  151. enum {
  152. UPIU_TASK_ATTR_SIMPLE = 0x00,
  153. UPIU_TASK_ATTR_ORDERED = 0x01,
  154. UPIU_TASK_ATTR_HEADQ = 0x02,
  155. UPIU_TASK_ATTR_ACA = 0x03,
  156. };
  157. /* UPIU Query request function */
  158. enum {
  159. UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
  160. UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
  161. };
  162. /* Offset of the response code in the UPIU header */
  163. #define UPIU_RSP_CODE_OFFSET 8
  164. enum {
  165. MASK_SCSI_STATUS = 0xFF,
  166. MASK_TASK_RESPONSE = 0xFF00,
  167. MASK_RSP_UPIU_RESULT = 0xFFFF,
  168. MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
  169. MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
  170. MASK_RSP_EXCEPTION_EVENT = 0x10000,
  171. MASK_TM_SERVICE_RESP = 0xFF,
  172. MASK_TM_FUNC = 0xFF,
  173. };
  174. /* UTP QUERY Transaction Specific Fields OpCode */
  175. enum query_opcode {
  176. UPIU_QUERY_OPCODE_NOP = 0x0,
  177. UPIU_QUERY_OPCODE_READ_DESC = 0x1,
  178. UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
  179. UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
  180. UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
  181. UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
  182. UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
  183. UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
  184. UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
  185. };
  186. /* Query response result code */
  187. enum {
  188. QUERY_RESULT_SUCCESS = 0x00,
  189. QUERY_RESULT_NOT_READABLE = 0xF6,
  190. QUERY_RESULT_NOT_WRITEABLE = 0xF7,
  191. QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
  192. QUERY_RESULT_INVALID_LENGTH = 0xF9,
  193. QUERY_RESULT_INVALID_VALUE = 0xFA,
  194. QUERY_RESULT_INVALID_SELECTOR = 0xFB,
  195. QUERY_RESULT_INVALID_INDEX = 0xFC,
  196. QUERY_RESULT_INVALID_IDN = 0xFD,
  197. QUERY_RESULT_INVALID_OPCODE = 0xFE,
  198. QUERY_RESULT_GENERAL_FAILURE = 0xFF,
  199. };
  200. enum {
  201. UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
  202. UPIU_COMMAND_SET_TYPE_UFS = 0x1,
  203. UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
  204. };
  205. /* Flag idn for Query Requests*/
  206. enum flag_idn {
  207. QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
  208. QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
  209. QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
  210. QUERY_FLAG_IDN_BKOPS_EN = 0x04,
  211. QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
  212. QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
  213. QUERY_FLAG_IDN_RESERVED2 = 0x07,
  214. QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
  215. QUERY_FLAG_IDN_BUSY_RTC = 0x09,
  216. QUERY_FLAG_IDN_RESERVED3 = 0x0A,
  217. QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
  218. };
  219. /* Attribute idn for Query requests */
  220. enum attr_idn {
  221. QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
  222. QUERY_ATTR_IDN_RESERVED = 0x01,
  223. QUERY_ATTR_IDN_POWER_MODE = 0x02,
  224. QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
  225. QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
  226. QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
  227. QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
  228. QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
  229. QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
  230. QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
  231. QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
  232. QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
  233. QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
  234. QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
  235. QUERY_ATTR_IDN_EE_STATUS = 0x0E,
  236. QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
  237. QUERY_ATTR_IDN_CNTX_CONF = 0x10,
  238. QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
  239. QUERY_ATTR_IDN_RESERVED2 = 0x12,
  240. QUERY_ATTR_IDN_RESERVED3 = 0x13,
  241. QUERY_ATTR_IDN_FFU_STATUS = 0x14,
  242. QUERY_ATTR_IDN_PSA_STATE = 0x15,
  243. QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
  244. };
  245. /* Descriptor idn for Query requests */
  246. enum desc_idn {
  247. QUERY_DESC_IDN_DEVICE = 0x0,
  248. QUERY_DESC_IDN_CONFIGURATION = 0x1,
  249. QUERY_DESC_IDN_UNIT = 0x2,
  250. QUERY_DESC_IDN_RFU_0 = 0x3,
  251. QUERY_DESC_IDN_INTERCONNECT = 0x4,
  252. QUERY_DESC_IDN_STRING = 0x5,
  253. QUERY_DESC_IDN_RFU_1 = 0x6,
  254. QUERY_DESC_IDN_GEOMETRY = 0x7,
  255. QUERY_DESC_IDN_POWER = 0x8,
  256. QUERY_DESC_IDN_HEALTH = 0x9,
  257. QUERY_DESC_IDN_MAX,
  258. };
  259. enum desc_header_offset {
  260. QUERY_DESC_LENGTH_OFFSET = 0x00,
  261. QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
  262. };
  263. struct ufshcd_sg_entry {
  264. __le32 base_addr;
  265. __le32 upper_addr;
  266. __le32 reserved;
  267. __le32 size;
  268. };
  269. #define MAX_BUFF 128
  270. /**
  271. * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
  272. * @command_upiu: Command UPIU Frame address
  273. * @response_upiu: Response UPIU Frame address
  274. * @prd_table: Physical Region Descriptor
  275. */
  276. struct utp_transfer_cmd_desc {
  277. u8 command_upiu[ALIGNED_UPIU_SIZE];
  278. u8 response_upiu[ALIGNED_UPIU_SIZE];
  279. struct ufshcd_sg_entry prd_table[MAX_BUFF];
  280. };
  281. /**
  282. * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
  283. * @dword0: Descriptor Header DW0
  284. * @dword1: Descriptor Header DW1
  285. * @dword2: Descriptor Header DW2
  286. * @dword3: Descriptor Header DW3
  287. */
  288. struct request_desc_header {
  289. __le32 dword_0;
  290. __le32 dword_1;
  291. __le32 dword_2;
  292. __le32 dword_3;
  293. };
  294. /**
  295. * struct utp_transfer_req_desc - UTRD structure
  296. * @header: UTRD header DW-0 to DW-3
  297. * @command_desc_base_addr_lo: UCD base address low DW-4
  298. * @command_desc_base_addr_hi: UCD base address high DW-5
  299. * @response_upiu_length: response UPIU length DW-6
  300. * @response_upiu_offset: response UPIU offset DW-6
  301. * @prd_table_length: Physical region descriptor length DW-7
  302. * @prd_table_offset: Physical region descriptor offset DW-7
  303. */
  304. struct utp_transfer_req_desc {
  305. /* DW 0-3 */
  306. struct request_desc_header header;
  307. /* DW 4-5*/
  308. __le32 command_desc_base_addr_lo;
  309. __le32 command_desc_base_addr_hi;
  310. /* DW 6 */
  311. __le16 response_upiu_length;
  312. __le16 response_upiu_offset;
  313. /* DW 7 */
  314. __le16 prd_table_length;
  315. __le16 prd_table_offset;
  316. };
  317. /**
  318. * struct utp_upiu_header - UPIU header structure
  319. * @dword_0: UPIU header DW-0
  320. * @dword_1: UPIU header DW-1
  321. * @dword_2: UPIU header DW-2
  322. */
  323. struct utp_upiu_header {
  324. __be32 dword_0;
  325. __be32 dword_1;
  326. __be32 dword_2;
  327. };
  328. /**
  329. * struct utp_upiu_query - upiu request buffer structure for
  330. * query request.
  331. * @opcode: command to perform B-0
  332. * @idn: a value that indicates the particular type of data B-1
  333. * @index: Index to further identify data B-2
  334. * @selector: Index to further identify data B-3
  335. * @reserved_osf: spec reserved field B-4,5
  336. * @length: number of descriptor bytes to read/write B-6,7
  337. * @value: Attribute value to be written DW-5
  338. * @reserved: spec reserved DW-6,7
  339. */
  340. struct utp_upiu_query {
  341. __u8 opcode;
  342. __u8 idn;
  343. __u8 index;
  344. __u8 selector;
  345. __be16 reserved_osf;
  346. __be16 length;
  347. __be32 value;
  348. __be32 reserved[2];
  349. };
  350. /**
  351. * struct utp_upiu_cmd - Command UPIU structure
  352. * @data_transfer_len: Data Transfer Length DW-3
  353. * @cdb: Command Descriptor Block CDB DW-4 to DW-7
  354. */
  355. struct utp_upiu_cmd {
  356. __be32 exp_data_transfer_len;
  357. u8 cdb[UFS_CDB_SIZE];
  358. };
  359. /*
  360. * UTMRD structure.
  361. */
  362. struct utp_task_req_desc {
  363. /* DW 0-3 */
  364. struct request_desc_header header;
  365. /* DW 4-11 - Task request UPIU structure */
  366. struct utp_upiu_header req_header;
  367. __be32 input_param1;
  368. __be32 input_param2;
  369. __be32 input_param3;
  370. __be32 __reserved1[2];
  371. /* DW 12-19 - Task Management Response UPIU structure */
  372. struct utp_upiu_header rsp_header;
  373. __be32 output_param1;
  374. __be32 output_param2;
  375. __be32 __reserved2[3];
  376. };
  377. /**
  378. * struct utp_upiu_req - general upiu request structure
  379. * @header:UPIU header structure DW-0 to DW-2
  380. * @sc: fields structure for scsi command DW-3 to DW-7
  381. * @qr: fields structure for query request DW-3 to DW-7
  382. */
  383. struct utp_upiu_req {
  384. struct utp_upiu_header header;
  385. union {
  386. struct utp_upiu_cmd sc;
  387. struct utp_upiu_query qr;
  388. struct utp_upiu_query tr;
  389. /* use utp_upiu_query to host the 4 dwords of uic command */
  390. struct utp_upiu_query uc;
  391. };
  392. };
  393. /**
  394. * struct utp_cmd_rsp - Response UPIU structure
  395. * @residual_transfer_count: Residual transfer count DW-3
  396. * @reserved: Reserved double words DW-4 to DW-7
  397. * @sense_data_len: Sense data length DW-8 U16
  398. * @sense_data: Sense data field DW-8 to DW-12
  399. */
  400. struct utp_cmd_rsp {
  401. __be32 residual_transfer_count;
  402. __be32 reserved[4];
  403. __be16 sense_data_len;
  404. u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH];
  405. };
  406. /**
  407. * struct utp_upiu_rsp - general upiu response structure
  408. * @header: UPIU header structure DW-0 to DW-2
  409. * @sr: fields structure for scsi command DW-3 to DW-12
  410. * @qr: fields structure for query request DW-3 to DW-7
  411. */
  412. struct utp_upiu_rsp {
  413. struct utp_upiu_header header;
  414. union {
  415. struct utp_cmd_rsp sr;
  416. struct utp_upiu_query qr;
  417. };
  418. };
  419. #define MAX_MODEL_LEN 16
  420. /**
  421. * ufs_dev_desc - ufs device details from the device descriptor
  422. *
  423. * @wmanufacturerid: card details
  424. * @model: card model
  425. */
  426. struct ufs_dev_desc {
  427. u16 wmanufacturerid;
  428. char model[MAX_MODEL_LEN + 1];
  429. };
  430. /* Device descriptor parameters offsets in bytes*/
  431. enum device_desc_param {
  432. DEVICE_DESC_PARAM_LEN = 0x0,
  433. DEVICE_DESC_PARAM_TYPE = 0x1,
  434. DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
  435. DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
  436. DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
  437. DEVICE_DESC_PARAM_PRTCL = 0x5,
  438. DEVICE_DESC_PARAM_NUM_LU = 0x6,
  439. DEVICE_DESC_PARAM_NUM_WLU = 0x7,
  440. DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
  441. DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
  442. DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
  443. DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
  444. DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
  445. DEVICE_DESC_PARAM_SEC_LU = 0xD,
  446. DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
  447. DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
  448. DEVICE_DESC_PARAM_SPEC_VER = 0x10,
  449. DEVICE_DESC_PARAM_MANF_DATE = 0x12,
  450. DEVICE_DESC_PARAM_MANF_NAME = 0x14,
  451. DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
  452. DEVICE_DESC_PARAM_SN = 0x16,
  453. DEVICE_DESC_PARAM_OEM_ID = 0x17,
  454. DEVICE_DESC_PARAM_MANF_ID = 0x18,
  455. DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
  456. DEVICE_DESC_PARAM_UD_LEN = 0x1B,
  457. DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
  458. DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
  459. DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
  460. DEVICE_DESC_PARAM_FFU_TMT = 0x20,
  461. DEVICE_DESC_PARAM_Q_DPTH = 0x21,
  462. DEVICE_DESC_PARAM_DEV_VER = 0x22,
  463. DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
  464. DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
  465. DEVICE_DESC_PARAM_PSA_TMT = 0x29,
  466. DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
  467. };
  468. struct ufs_hba;
  469. enum {
  470. UFSHCD_MAX_CHANNEL = 0,
  471. UFSHCD_MAX_ID = 1,
  472. };
  473. enum dev_cmd_type {
  474. DEV_CMD_TYPE_NOP = 0x0,
  475. DEV_CMD_TYPE_QUERY = 0x1,
  476. };
  477. /**
  478. * struct uic_command - UIC command structure
  479. * @command: UIC command
  480. * @argument1: UIC command argument 1
  481. * @argument2: UIC command argument 2
  482. * @argument3: UIC command argument 3
  483. * @cmd_active: Indicate if UIC command is outstanding
  484. * @result: UIC command result
  485. * @done: UIC command completion
  486. */
  487. struct uic_command {
  488. u32 command;
  489. u32 argument1;
  490. u32 argument2;
  491. u32 argument3;
  492. int cmd_active;
  493. int result;
  494. };
  495. /* GenSelectorIndex calculation macros for M-PHY attributes */
  496. #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
  497. #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
  498. #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
  499. ((sel) & 0xFFFF))
  500. #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
  501. #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
  502. #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
  503. /* Link Status*/
  504. enum link_status {
  505. UFSHCD_LINK_IS_DOWN = 1,
  506. UFSHCD_LINK_IS_UP = 2,
  507. };
  508. #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
  509. ((sel) & 0xFFFF))
  510. #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
  511. #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
  512. #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
  513. /* UIC Commands */
  514. enum uic_cmd_dme {
  515. UIC_CMD_DME_GET = 0x01,
  516. UIC_CMD_DME_SET = 0x02,
  517. UIC_CMD_DME_PEER_GET = 0x03,
  518. UIC_CMD_DME_PEER_SET = 0x04,
  519. UIC_CMD_DME_POWERON = 0x10,
  520. UIC_CMD_DME_POWEROFF = 0x11,
  521. UIC_CMD_DME_ENABLE = 0x12,
  522. UIC_CMD_DME_RESET = 0x14,
  523. UIC_CMD_DME_END_PT_RST = 0x15,
  524. UIC_CMD_DME_LINK_STARTUP = 0x16,
  525. UIC_CMD_DME_HIBER_ENTER = 0x17,
  526. UIC_CMD_DME_HIBER_EXIT = 0x18,
  527. UIC_CMD_DME_TEST_MODE = 0x1A,
  528. };
  529. /* UIC Config result code / Generic error code */
  530. enum {
  531. UIC_CMD_RESULT_SUCCESS = 0x00,
  532. UIC_CMD_RESULT_INVALID_ATTR = 0x01,
  533. UIC_CMD_RESULT_FAILURE = 0x01,
  534. UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
  535. UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
  536. UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
  537. UIC_CMD_RESULT_BAD_INDEX = 0x05,
  538. UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
  539. UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
  540. UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
  541. UIC_CMD_RESULT_BUSY = 0x09,
  542. UIC_CMD_RESULT_DME_FAILURE = 0x0A,
  543. };
  544. #define MASK_UIC_COMMAND_RESULT 0xFF
  545. /* Host <-> Device UniPro Link state */
  546. enum uic_link_state {
  547. UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
  548. UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
  549. UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
  550. };
  551. /* UIC command interfaces for DME primitives */
  552. #define DME_LOCAL 0
  553. #define DME_PEER 1
  554. #define ATTR_SET_NOR 0 /* NORMAL */
  555. #define ATTR_SET_ST 1 /* STATIC */
  556. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  557. u8 attr_set, u32 mib_val, u8 peer);
  558. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  559. u32 *mib_val, u8 peer);
  560. static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
  561. u32 mib_val)
  562. {
  563. return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
  564. mib_val, DME_LOCAL);
  565. }
  566. static inline int ufshcd_dme_get(struct ufs_hba *hba,
  567. u32 attr_sel, u32 *mib_val)
  568. {
  569. return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
  570. }
  571. static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
  572. u32 attr_sel, u32 *mib_val)
  573. {
  574. return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
  575. }
  576. static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
  577. u32 mib_val)
  578. {
  579. return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
  580. mib_val, DME_PEER);
  581. }
  582. /**
  583. * struct ufs_query_req - parameters for building a query request
  584. * @query_func: UPIU header query function
  585. * @upiu_req: the query request data
  586. */
  587. struct ufs_query_req {
  588. u8 query_func;
  589. struct utp_upiu_query upiu_req;
  590. };
  591. /**
  592. * struct ufs_query_resp - UPIU QUERY
  593. * @response: device response code
  594. * @upiu_res: query response data
  595. */
  596. struct ufs_query_res {
  597. u8 response;
  598. struct utp_upiu_query upiu_res;
  599. };
  600. /**
  601. * struct ufs_query - holds relevant data structures for query request
  602. * @request: request upiu and function
  603. * @descriptor: buffer for sending/receiving descriptor
  604. * @response: response upiu and response
  605. */
  606. struct ufs_query {
  607. struct ufs_query_req request;
  608. u8 *descriptor;
  609. struct ufs_query_res response;
  610. };
  611. /**
  612. * struct ufs_dev_cmd - all assosiated fields with device management commands
  613. * @type: device management command type - Query, NOP OUT
  614. * @tag_wq: wait queue until free command slot is available
  615. */
  616. struct ufs_dev_cmd {
  617. enum dev_cmd_type type;
  618. struct ufs_query query;
  619. };
  620. struct ufs_hba_ops {
  621. int (*init)(struct ufs_hba *hba);
  622. int (*hce_enable_notify)(struct ufs_hba *hba,
  623. enum ufs_notify_change_status);
  624. int (*link_startup_notify)(struct ufs_hba *hba,
  625. enum ufs_notify_change_status);
  626. int (*phy_initialization)(struct ufs_hba *hba);
  627. };
  628. struct ufs_hba {
  629. struct udevice *dev;
  630. void __iomem *mmio_base;
  631. struct ufs_hba_ops *ops;
  632. struct ufs_desc_size desc_size;
  633. u32 capabilities;
  634. u32 version;
  635. u32 intr_mask;
  636. u32 quirks;
  637. /*
  638. * If UFS host controller is having issue in processing LCC (Line
  639. * Control Command) coming from device then enable this quirk.
  640. * When this quirk is enabled, host controller driver should disable
  641. * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
  642. * attribute of device to 0).
  643. */
  644. #define UFSHCD_QUIRK_BROKEN_LCC 0x1
  645. /* Virtual memory reference */
  646. struct utp_transfer_cmd_desc *ucdl;
  647. struct utp_transfer_req_desc *utrdl;
  648. /* TODO: Add Task Manegement Support */
  649. struct utp_task_req_desc *utmrdl;
  650. struct utp_upiu_req *ucd_req_ptr;
  651. struct utp_upiu_rsp *ucd_rsp_ptr;
  652. struct ufshcd_sg_entry *ucd_prdt_ptr;
  653. /* Power Mode information */
  654. enum ufs_dev_pwr_mode curr_dev_pwr_mode;
  655. struct ufs_pa_layer_attr pwr_info;
  656. struct ufs_pwr_mode_info max_pwr_info;
  657. struct ufs_dev_cmd dev_cmd;
  658. };
  659. static inline int ufshcd_ops_init(struct ufs_hba *hba)
  660. {
  661. if (hba->ops && hba->ops->init)
  662. return hba->ops->init(hba);
  663. return 0;
  664. }
  665. static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
  666. bool status)
  667. {
  668. if (hba->ops && hba->ops->hce_enable_notify)
  669. return hba->ops->hce_enable_notify(hba, status);
  670. return 0;
  671. }
  672. static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba,
  673. bool status)
  674. {
  675. if (hba->ops && hba->ops->link_startup_notify)
  676. return hba->ops->link_startup_notify(hba, status);
  677. return 0;
  678. }
  679. /* Controller UFSHCI version */
  680. enum {
  681. UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
  682. UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
  683. UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
  684. UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
  685. };
  686. /* Interrupt disable masks */
  687. enum {
  688. /* Interrupt disable mask for UFSHCI v1.0 */
  689. INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
  690. INTERRUPT_MASK_RW_VER_10 = 0x30000,
  691. /* Interrupt disable mask for UFSHCI v1.1 */
  692. INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
  693. /* Interrupt disable mask for UFSHCI v2.1 */
  694. INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
  695. };
  696. /* UFSHCI Registers */
  697. enum {
  698. REG_CONTROLLER_CAPABILITIES = 0x00,
  699. REG_UFS_VERSION = 0x08,
  700. REG_CONTROLLER_DEV_ID = 0x10,
  701. REG_CONTROLLER_PROD_ID = 0x14,
  702. REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
  703. REG_INTERRUPT_STATUS = 0x20,
  704. REG_INTERRUPT_ENABLE = 0x24,
  705. REG_CONTROLLER_STATUS = 0x30,
  706. REG_CONTROLLER_ENABLE = 0x34,
  707. REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
  708. REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
  709. REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
  710. REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
  711. REG_UIC_ERROR_CODE_DME = 0x48,
  712. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
  713. REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
  714. REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
  715. REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
  716. REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
  717. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
  718. REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
  719. REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
  720. REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
  721. REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
  722. REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
  723. REG_UIC_COMMAND = 0x90,
  724. REG_UIC_COMMAND_ARG_1 = 0x94,
  725. REG_UIC_COMMAND_ARG_2 = 0x98,
  726. REG_UIC_COMMAND_ARG_3 = 0x9C,
  727. UFSHCI_REG_SPACE_SIZE = 0xA0,
  728. REG_UFS_CCAP = 0x100,
  729. REG_UFS_CRYPTOCAP = 0x104,
  730. UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
  731. };
  732. /* Controller capability masks */
  733. enum {
  734. MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
  735. MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
  736. MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
  737. MASK_64_ADDRESSING_SUPPORT = 0x01000000,
  738. MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  739. MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
  740. };
  741. /* Interrupt Status 20h */
  742. #define UTP_TRANSFER_REQ_COMPL 0x1
  743. #define UIC_DME_END_PT_RESET 0x2
  744. #define UIC_ERROR 0x4
  745. #define UIC_TEST_MODE 0x8
  746. #define UIC_POWER_MODE 0x10
  747. #define UIC_HIBERNATE_EXIT 0x20
  748. #define UIC_HIBERNATE_ENTER 0x40
  749. #define UIC_LINK_LOST 0x80
  750. #define UIC_LINK_STARTUP 0x100
  751. #define UTP_TASK_REQ_COMPL 0x200
  752. #define UIC_COMMAND_COMPL 0x400
  753. #define DEVICE_FATAL_ERROR 0x800
  754. #define CONTROLLER_FATAL_ERROR 0x10000
  755. #define SYSTEM_BUS_FATAL_ERROR 0x20000
  756. #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
  757. UIC_HIBERNATE_EXIT |\
  758. UIC_POWER_MODE)
  759. #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
  760. #define UFSHCD_ERROR_MASK (UIC_ERROR |\
  761. DEVICE_FATAL_ERROR |\
  762. CONTROLLER_FATAL_ERROR |\
  763. SYSTEM_BUS_FATAL_ERROR)
  764. #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
  765. CONTROLLER_FATAL_ERROR |\
  766. SYSTEM_BUS_FATAL_ERROR)
  767. /* Host Controller Enable 0x34h */
  768. #define CONTROLLER_ENABLE 0x1
  769. #define CONTROLLER_DISABLE 0x0
  770. /* HCS - Host Controller Status 30h */
  771. #define DEVICE_PRESENT 0x1
  772. #define UTP_TRANSFER_REQ_LIST_READY 0x2
  773. #define UTP_TASK_REQ_LIST_READY 0x4
  774. #define UIC_COMMAND_READY 0x8
  775. #define HOST_ERROR_INDICATOR 0x10
  776. #define DEVICE_ERROR_INDICATOR 0x20
  777. #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
  778. #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
  779. UTP_TASK_REQ_LIST_READY |\
  780. UIC_COMMAND_READY)
  781. enum {
  782. PWR_OK = 0x0,
  783. PWR_LOCAL = 0x01,
  784. PWR_REMOTE = 0x02,
  785. PWR_BUSY = 0x03,
  786. PWR_ERROR_CAP = 0x04,
  787. PWR_FATAL_ERROR = 0x05,
  788. };
  789. /* UICCMD - UIC Command */
  790. #define COMMAND_OPCODE_MASK 0xFF
  791. #define GEN_SELECTOR_INDEX_MASK 0xFFFF
  792. #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
  793. #define RESET_LEVEL 0xFF
  794. #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
  795. #define CONFIG_RESULT_CODE_MASK 0xFF
  796. #define GENERIC_ERROR_CODE_MASK 0xFF
  797. #define ufshcd_writel(hba, val, reg) \
  798. writel((val), (hba)->mmio_base + (reg))
  799. #define ufshcd_readl(hba, reg) \
  800. readl((hba)->mmio_base + (reg))
  801. /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
  802. #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
  803. /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
  804. #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
  805. int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
  806. #endif