sunxi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Allwinner SUNXI "glue layer"
  4. *
  5. * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
  6. * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  7. *
  8. * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
  9. * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
  10. * javen <javen@allwinnertech.com>
  11. *
  12. * Based on the DA8xx "glue layer" code.
  13. * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  14. * Copyright (C) 2005-2006 by Texas Instruments
  15. *
  16. * This file is part of the Inventra Controller Driver for Linux.
  17. */
  18. #include <common.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <generic-phy.h>
  22. #include <log.h>
  23. #include <malloc.h>
  24. #include <phy-sun4i-usb.h>
  25. #include <reset.h>
  26. #include <asm/arch/cpu.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/gpio.h>
  29. #include <asm-generic/gpio.h>
  30. #include <dm/device_compat.h>
  31. #include <dm/lists.h>
  32. #include <dm/root.h>
  33. #include <linux/bitops.h>
  34. #include <linux/delay.h>
  35. #include <linux/usb/musb.h>
  36. #include "linux-compat.h"
  37. #include "musb_core.h"
  38. #include "musb_uboot.h"
  39. /******************************************************************************
  40. ******************************************************************************
  41. * From the Allwinner driver
  42. ******************************************************************************
  43. ******************************************************************************/
  44. /******************************************************************************
  45. * From include/sunxi_usb_bsp.h
  46. ******************************************************************************/
  47. /* reg offsets */
  48. #define USBC_REG_o_ISCR 0x0400
  49. #define USBC_REG_o_PHYCTL 0x0404
  50. #define USBC_REG_o_PHYBIST 0x0408
  51. #define USBC_REG_o_PHYTUNE 0x040c
  52. #define USBC_REG_o_VEND0 0x0043
  53. /* Interface Status and Control */
  54. #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
  55. #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
  56. #define USBC_BP_ISCR_EXT_ID_STATUS 28
  57. #define USBC_BP_ISCR_EXT_DM_STATUS 27
  58. #define USBC_BP_ISCR_EXT_DP_STATUS 26
  59. #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
  60. #define USBC_BP_ISCR_MERGED_ID_STATUS 24
  61. #define USBC_BP_ISCR_ID_PULLUP_EN 17
  62. #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
  63. #define USBC_BP_ISCR_FORCE_ID 14
  64. #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
  65. #define USBC_BP_ISCR_VBUS_VALID_SRC 10
  66. #define USBC_BP_ISCR_HOSC_EN 7
  67. #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
  68. #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
  69. #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
  70. #define USBC_BP_ISCR_IRQ_ENABLE 3
  71. #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
  72. #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
  73. #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
  74. /******************************************************************************
  75. * From usbc/usbc.c
  76. ******************************************************************************/
  77. #define OFF_SUN6I_AHB_RESET0 0x2c0
  78. struct sunxi_musb_config {
  79. struct musb_hdrc_config *config;
  80. };
  81. struct sunxi_glue {
  82. struct musb_host_data mdata;
  83. struct clk clk;
  84. struct reset_ctl rst;
  85. struct sunxi_musb_config *cfg;
  86. struct device dev;
  87. struct phy phy;
  88. };
  89. #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
  90. static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
  91. {
  92. u32 temp = reg_val;
  93. temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
  94. temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
  95. temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
  96. return temp;
  97. }
  98. static void USBC_EnableIdPullUp(__iomem void *base)
  99. {
  100. u32 reg_val;
  101. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  102. reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
  103. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  104. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  105. }
  106. static void USBC_EnableDpDmPullUp(__iomem void *base)
  107. {
  108. u32 reg_val;
  109. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  110. reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
  111. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  112. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  113. }
  114. static void USBC_ForceIdToLow(__iomem void *base)
  115. {
  116. u32 reg_val;
  117. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  118. reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
  119. reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
  120. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  121. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  122. }
  123. static void USBC_ForceIdToHigh(__iomem void *base)
  124. {
  125. u32 reg_val;
  126. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  127. reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
  128. reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
  129. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  130. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  131. }
  132. static void USBC_ForceVbusValidToLow(__iomem void *base)
  133. {
  134. u32 reg_val;
  135. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  136. reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
  137. reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
  138. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  139. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  140. }
  141. static void USBC_ForceVbusValidToHigh(__iomem void *base)
  142. {
  143. u32 reg_val;
  144. reg_val = musb_readl(base, USBC_REG_o_ISCR);
  145. reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
  146. reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
  147. reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
  148. musb_writel(base, USBC_REG_o_ISCR, reg_val);
  149. }
  150. static void USBC_ConfigFIFO_Base(void)
  151. {
  152. u32 reg_value;
  153. /* config usb fifo, 8kb mode */
  154. reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  155. reg_value &= ~(0x03 << 0);
  156. reg_value |= BIT(0);
  157. writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  158. }
  159. /******************************************************************************
  160. * Needed for the DFU polling magic
  161. ******************************************************************************/
  162. static u8 last_int_usb;
  163. bool dfu_usb_get_reset(void)
  164. {
  165. return !!(last_int_usb & MUSB_INTR_RESET);
  166. }
  167. /******************************************************************************
  168. * MUSB Glue code
  169. ******************************************************************************/
  170. static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
  171. {
  172. struct musb *musb = __hci;
  173. irqreturn_t retval = IRQ_NONE;
  174. /* read and flush interrupts */
  175. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  176. last_int_usb = musb->int_usb;
  177. if (musb->int_usb)
  178. musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
  179. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
  180. if (musb->int_tx)
  181. musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
  182. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
  183. if (musb->int_rx)
  184. musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
  185. if (musb->int_usb || musb->int_tx || musb->int_rx)
  186. retval |= musb_interrupt(musb);
  187. return retval;
  188. }
  189. /* musb_core does not call enable / disable in a balanced manner <sigh> */
  190. static bool enabled = false;
  191. static int sunxi_musb_enable(struct musb *musb)
  192. {
  193. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  194. int ret;
  195. pr_debug("%s():\n", __func__);
  196. musb_ep_select(musb->mregs, 0);
  197. musb_writeb(musb->mregs, MUSB_FADDR, 0);
  198. if (enabled)
  199. return 0;
  200. /* select PIO mode */
  201. musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
  202. if (is_host_enabled(musb)) {
  203. ret = sun4i_usb_phy_vbus_detect(&glue->phy);
  204. if (ret == 1) {
  205. printf("A charger is plugged into the OTG: ");
  206. return -ENODEV;
  207. }
  208. ret = sun4i_usb_phy_id_detect(&glue->phy);
  209. if (ret == 1) {
  210. printf("No host cable detected: ");
  211. return -ENODEV;
  212. }
  213. ret = generic_phy_power_on(&glue->phy);
  214. if (ret) {
  215. pr_debug("failed to power on USB PHY\n");
  216. return ret;
  217. }
  218. }
  219. USBC_ForceVbusValidToHigh(musb->mregs);
  220. enabled = true;
  221. return 0;
  222. }
  223. static void sunxi_musb_disable(struct musb *musb)
  224. {
  225. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  226. int ret;
  227. pr_debug("%s():\n", __func__);
  228. if (!enabled)
  229. return;
  230. if (is_host_enabled(musb)) {
  231. ret = generic_phy_power_off(&glue->phy);
  232. if (ret) {
  233. pr_debug("failed to power off USB PHY\n");
  234. return;
  235. }
  236. }
  237. USBC_ForceVbusValidToLow(musb->mregs);
  238. mdelay(200); /* Wait for the current session to timeout */
  239. enabled = false;
  240. }
  241. static int sunxi_musb_init(struct musb *musb)
  242. {
  243. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  244. int ret;
  245. pr_debug("%s():\n", __func__);
  246. ret = clk_enable(&glue->clk);
  247. if (ret) {
  248. dev_err(musb->controller, "failed to enable clock\n");
  249. return ret;
  250. }
  251. if (reset_valid(&glue->rst)) {
  252. ret = reset_deassert(&glue->rst);
  253. if (ret) {
  254. dev_err(musb->controller, "failed to deassert reset\n");
  255. goto err_clk;
  256. }
  257. }
  258. ret = generic_phy_init(&glue->phy);
  259. if (ret) {
  260. dev_dbg(musb->controller, "failed to init USB PHY\n");
  261. goto err_rst;
  262. }
  263. musb->isr = sunxi_musb_interrupt;
  264. USBC_ConfigFIFO_Base();
  265. USBC_EnableDpDmPullUp(musb->mregs);
  266. USBC_EnableIdPullUp(musb->mregs);
  267. if (is_host_enabled(musb)) {
  268. /* Host mode */
  269. USBC_ForceIdToLow(musb->mregs);
  270. } else {
  271. /* Peripheral mode */
  272. USBC_ForceIdToHigh(musb->mregs);
  273. }
  274. USBC_ForceVbusValidToHigh(musb->mregs);
  275. return 0;
  276. err_rst:
  277. if (reset_valid(&glue->rst))
  278. reset_assert(&glue->rst);
  279. err_clk:
  280. clk_disable(&glue->clk);
  281. return ret;
  282. }
  283. static int sunxi_musb_exit(struct musb *musb)
  284. {
  285. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  286. int ret = 0;
  287. if (generic_phy_valid(&glue->phy)) {
  288. ret = generic_phy_exit(&glue->phy);
  289. if (ret) {
  290. dev_dbg(musb->controller,
  291. "failed to power off usb phy\n");
  292. return ret;
  293. }
  294. }
  295. if (reset_valid(&glue->rst))
  296. reset_assert(&glue->rst);
  297. clk_disable(&glue->clk);
  298. return 0;
  299. }
  300. static void sunxi_musb_pre_root_reset_end(struct musb *musb)
  301. {
  302. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  303. sun4i_usb_phy_set_squelch_detect(&glue->phy, false);
  304. }
  305. static void sunxi_musb_post_root_reset_end(struct musb *musb)
  306. {
  307. struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
  308. sun4i_usb_phy_set_squelch_detect(&glue->phy, true);
  309. }
  310. static const struct musb_platform_ops sunxi_musb_ops = {
  311. .init = sunxi_musb_init,
  312. .exit = sunxi_musb_exit,
  313. .enable = sunxi_musb_enable,
  314. .disable = sunxi_musb_disable,
  315. .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
  316. .post_root_reset_end = sunxi_musb_post_root_reset_end,
  317. };
  318. /* Allwinner OTG supports up to 5 endpoints */
  319. #define SUNXI_MUSB_MAX_EP_NUM 6
  320. #define SUNXI_MUSB_RAM_BITS 11
  321. static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
  322. MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
  323. MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
  324. MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
  325. MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
  326. MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
  327. MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
  328. MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
  329. MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
  330. MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
  331. MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
  332. };
  333. /* H3/V3s OTG supports only 4 endpoints */
  334. #define SUNXI_MUSB_MAX_EP_NUM_H3 5
  335. static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
  336. MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
  337. MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
  338. MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
  339. MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
  340. MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
  341. MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
  342. MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
  343. MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
  344. };
  345. static struct musb_hdrc_config musb_config = {
  346. .fifo_cfg = sunxi_musb_mode_cfg,
  347. .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
  348. .multipoint = true,
  349. .dyn_fifo = true,
  350. .num_eps = SUNXI_MUSB_MAX_EP_NUM,
  351. .ram_bits = SUNXI_MUSB_RAM_BITS,
  352. };
  353. static struct musb_hdrc_config musb_config_h3 = {
  354. .fifo_cfg = sunxi_musb_mode_cfg_h3,
  355. .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
  356. .multipoint = true,
  357. .dyn_fifo = true,
  358. .soft_con = true,
  359. .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
  360. .ram_bits = SUNXI_MUSB_RAM_BITS,
  361. };
  362. static int musb_usb_probe(struct udevice *dev)
  363. {
  364. struct sunxi_glue *glue = dev_get_priv(dev);
  365. struct musb_host_data *host = &glue->mdata;
  366. struct musb_hdrc_platform_data pdata;
  367. void *base = dev_read_addr_ptr(dev);
  368. int ret;
  369. #ifdef CONFIG_USB_MUSB_HOST
  370. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  371. #endif
  372. if (!base)
  373. return -EINVAL;
  374. glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
  375. if (!glue->cfg)
  376. return -EINVAL;
  377. ret = clk_get_by_index(dev, 0, &glue->clk);
  378. if (ret) {
  379. dev_err(dev, "failed to get clock\n");
  380. return ret;
  381. }
  382. ret = reset_get_by_index(dev, 0, &glue->rst);
  383. if (ret && ret != -ENOENT) {
  384. dev_err(dev, "failed to get reset\n");
  385. return ret;
  386. }
  387. ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
  388. if (ret) {
  389. pr_err("failed to get usb PHY\n");
  390. return ret;
  391. }
  392. memset(&pdata, 0, sizeof(pdata));
  393. pdata.power = 250;
  394. pdata.platform_ops = &sunxi_musb_ops;
  395. pdata.config = glue->cfg->config;
  396. #ifdef CONFIG_USB_MUSB_HOST
  397. priv->desc_before_addr = true;
  398. pdata.mode = MUSB_HOST;
  399. host->host = musb_init_controller(&pdata, &glue->dev, base);
  400. if (!host->host)
  401. return -EIO;
  402. ret = musb_lowlevel_init(host);
  403. if (!ret)
  404. printf("Allwinner mUSB OTG (Host)\n");
  405. #else
  406. pdata.mode = MUSB_PERIPHERAL;
  407. host->host = musb_register(&pdata, &glue->dev, base);
  408. if (!host->host)
  409. return -EIO;
  410. printf("Allwinner mUSB OTG (Peripheral)\n");
  411. #endif
  412. return ret;
  413. }
  414. static int musb_usb_remove(struct udevice *dev)
  415. {
  416. struct sunxi_glue *glue = dev_get_priv(dev);
  417. struct musb_host_data *host = &glue->mdata;
  418. musb_stop(host->host);
  419. free(host->host);
  420. host->host = NULL;
  421. return 0;
  422. }
  423. static const struct sunxi_musb_config sun4i_a10_cfg = {
  424. .config = &musb_config,
  425. };
  426. static const struct sunxi_musb_config sun6i_a31_cfg = {
  427. .config = &musb_config,
  428. };
  429. static const struct sunxi_musb_config sun8i_h3_cfg = {
  430. .config = &musb_config_h3,
  431. };
  432. static const struct udevice_id sunxi_musb_ids[] = {
  433. { .compatible = "allwinner,sun4i-a10-musb",
  434. .data = (ulong)&sun4i_a10_cfg },
  435. { .compatible = "allwinner,sun6i-a31-musb",
  436. .data = (ulong)&sun6i_a31_cfg },
  437. { .compatible = "allwinner,sun8i-a33-musb",
  438. .data = (ulong)&sun6i_a31_cfg },
  439. { .compatible = "allwinner,sun8i-h3-musb",
  440. .data = (ulong)&sun8i_h3_cfg },
  441. { }
  442. };
  443. U_BOOT_DRIVER(usb_musb) = {
  444. .name = "sunxi-musb",
  445. #ifdef CONFIG_USB_MUSB_HOST
  446. .id = UCLASS_USB,
  447. #else
  448. .id = UCLASS_USB_GADGET_GENERIC,
  449. #endif
  450. .of_match = sunxi_musb_ids,
  451. .probe = musb_usb_probe,
  452. .remove = musb_usb_remove,
  453. #ifdef CONFIG_USB_MUSB_HOST
  454. .ops = &musb_usb_ops,
  455. #endif
  456. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  457. .priv_auto_alloc_size = sizeof(struct sunxi_glue),
  458. };