tsec.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale Three Speed Ethernet Controller driver
  4. *
  5. * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2003, Motorola, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <command.h>
  15. #include <tsec.h>
  16. #include <fsl_mdio.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <miiphy.h>
  21. #include <asm/processor.h>
  22. #include <asm/io.h>
  23. #ifndef CONFIG_DM_ETH
  24. /* Default initializations for TSEC controllers. */
  25. static struct tsec_info_struct tsec_info[] = {
  26. #ifdef CONFIG_TSEC1
  27. STD_TSEC_INFO(1), /* TSEC1 */
  28. #endif
  29. #ifdef CONFIG_TSEC2
  30. STD_TSEC_INFO(2), /* TSEC2 */
  31. #endif
  32. #ifdef CONFIG_MPC85XX_FEC
  33. {
  34. .regs = TSEC_GET_REGS(2, 0x2000),
  35. .devname = CONFIG_MPC85XX_FEC_NAME,
  36. .phyaddr = FEC_PHY_ADDR,
  37. .flags = FEC_FLAGS,
  38. .mii_devname = DEFAULT_MII_NAME
  39. }, /* FEC */
  40. #endif
  41. #ifdef CONFIG_TSEC3
  42. STD_TSEC_INFO(3), /* TSEC3 */
  43. #endif
  44. #ifdef CONFIG_TSEC4
  45. STD_TSEC_INFO(4), /* TSEC4 */
  46. #endif
  47. };
  48. #endif /* CONFIG_DM_ETH */
  49. #define TBIANA_SETTINGS ( \
  50. TBIANA_ASYMMETRIC_PAUSE \
  51. | TBIANA_SYMMETRIC_PAUSE \
  52. | TBIANA_FULL_DUPLEX \
  53. )
  54. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  55. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  56. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  57. TBICR_PHY_RESET \
  58. | TBICR_ANEG_ENABLE \
  59. | TBICR_FULL_DUPLEX \
  60. | TBICR_SPEED1_SET \
  61. )
  62. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  63. /* Configure the TBI for SGMII operation */
  64. static void tsec_configure_serdes(struct tsec_private *priv)
  65. {
  66. /*
  67. * Access TBI PHY registers at given TSEC register offset as opposed
  68. * to the register offset used for external PHY accesses
  69. */
  70. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  71. 0, TBI_ANA, TBIANA_SETTINGS);
  72. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  73. 0, TBI_TBICON, TBICON_CLK_SELECT);
  74. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  75. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  76. }
  77. /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
  78. * and this is the ethernet-crc method needed for TSEC -- and perhaps
  79. * some other adapter -- hash tables
  80. */
  81. #define CRCPOLY_LE 0xedb88320
  82. static u32 ether_crc(size_t len, unsigned char const *p)
  83. {
  84. int i;
  85. u32 crc;
  86. crc = ~0;
  87. while (len--) {
  88. crc ^= *p++;
  89. for (i = 0; i < 8; i++)
  90. crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
  91. }
  92. /* an reverse the bits, cuz of way they arrive -- last-first */
  93. crc = (crc >> 16) | (crc << 16);
  94. crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
  95. crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
  96. crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
  97. crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
  98. return crc;
  99. }
  100. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  101. /* Set the appropriate hash bit for the given addr */
  102. /*
  103. * The algorithm works like so:
  104. * 1) Take the Destination Address (ie the multicast address), and
  105. * do a CRC on it (little endian), and reverse the bits of the
  106. * result.
  107. * 2) Use the 8 most significant bits as a hash into a 256-entry
  108. * table. The table is controlled through 8 32-bit registers:
  109. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  110. * 255. This means that the 3 most significant bits in the
  111. * hash index which gaddr register to use, and the 5 other bits
  112. * indicate which bit (assuming an IBM numbering scheme, which
  113. * for PowerPC (tm) is usually the case) in the register holds
  114. * the entry.
  115. */
  116. #ifndef CONFIG_DM_ETH
  117. static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
  118. int join)
  119. #else
  120. static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
  121. #endif
  122. {
  123. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  124. struct tsec __iomem *regs = priv->regs;
  125. u32 result, value;
  126. u8 whichbit, whichreg;
  127. result = ether_crc(MAC_ADDR_LEN, mcast_mac);
  128. whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
  129. whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
  130. value = BIT(31 - whichbit);
  131. if (join)
  132. setbits_be32(&regs->hash.gaddr0 + whichreg, value);
  133. else
  134. clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
  135. return 0;
  136. }
  137. /*
  138. * Initialized required registers to appropriate values, zeroing
  139. * those we don't care about (unless zero is bad, in which case,
  140. * choose a more appropriate value)
  141. */
  142. static void init_registers(struct tsec __iomem *regs)
  143. {
  144. /* Clear IEVENT */
  145. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  146. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  147. out_be32(&regs->hash.iaddr0, 0);
  148. out_be32(&regs->hash.iaddr1, 0);
  149. out_be32(&regs->hash.iaddr2, 0);
  150. out_be32(&regs->hash.iaddr3, 0);
  151. out_be32(&regs->hash.iaddr4, 0);
  152. out_be32(&regs->hash.iaddr5, 0);
  153. out_be32(&regs->hash.iaddr6, 0);
  154. out_be32(&regs->hash.iaddr7, 0);
  155. out_be32(&regs->hash.gaddr0, 0);
  156. out_be32(&regs->hash.gaddr1, 0);
  157. out_be32(&regs->hash.gaddr2, 0);
  158. out_be32(&regs->hash.gaddr3, 0);
  159. out_be32(&regs->hash.gaddr4, 0);
  160. out_be32(&regs->hash.gaddr5, 0);
  161. out_be32(&regs->hash.gaddr6, 0);
  162. out_be32(&regs->hash.gaddr7, 0);
  163. out_be32(&regs->rctrl, 0x00000000);
  164. /* Init RMON mib registers */
  165. memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
  166. out_be32(&regs->rmon.cam1, 0xffffffff);
  167. out_be32(&regs->rmon.cam2, 0xffffffff);
  168. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  169. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  170. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  171. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  172. }
  173. /*
  174. * Configure maccfg2 based on negotiated speed and duplex
  175. * reported by PHY handling code
  176. */
  177. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  178. {
  179. struct tsec __iomem *regs = priv->regs;
  180. u32 ecntrl, maccfg2;
  181. if (!phydev->link) {
  182. printf("%s: No link.\n", phydev->dev->name);
  183. return;
  184. }
  185. /* clear all bits relative with interface mode */
  186. ecntrl = in_be32(&regs->ecntrl);
  187. ecntrl &= ~ECNTRL_R100;
  188. maccfg2 = in_be32(&regs->maccfg2);
  189. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  190. if (phydev->duplex)
  191. maccfg2 |= MACCFG2_FULL_DUPLEX;
  192. switch (phydev->speed) {
  193. case 1000:
  194. maccfg2 |= MACCFG2_GMII;
  195. break;
  196. case 100:
  197. case 10:
  198. maccfg2 |= MACCFG2_MII;
  199. /*
  200. * Set R100 bit in all modes although
  201. * it is only used in RGMII mode
  202. */
  203. if (phydev->speed == 100)
  204. ecntrl |= ECNTRL_R100;
  205. break;
  206. default:
  207. printf("%s: Speed was bad\n", phydev->dev->name);
  208. break;
  209. }
  210. out_be32(&regs->ecntrl, ecntrl);
  211. out_be32(&regs->maccfg2, maccfg2);
  212. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  213. (phydev->duplex) ? "full" : "half",
  214. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  215. }
  216. /*
  217. * This returns the status bits of the device. The return value
  218. * is never checked, and this is what the 8260 driver did, so we
  219. * do the same. Presumably, this would be zero if there were no
  220. * errors
  221. */
  222. #ifndef CONFIG_DM_ETH
  223. static int tsec_send(struct eth_device *dev, void *packet, int length)
  224. #else
  225. static int tsec_send(struct udevice *dev, void *packet, int length)
  226. #endif
  227. {
  228. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  229. struct tsec __iomem *regs = priv->regs;
  230. int result = 0;
  231. u16 status;
  232. int i;
  233. /* Find an empty buffer descriptor */
  234. for (i = 0;
  235. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  236. i++) {
  237. if (i >= TOUT_LOOP) {
  238. printf("%s: tsec: tx buffers full\n", dev->name);
  239. return result;
  240. }
  241. }
  242. out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
  243. out_be16(&priv->txbd[priv->tx_idx].length, length);
  244. status = in_be16(&priv->txbd[priv->tx_idx].status);
  245. out_be16(&priv->txbd[priv->tx_idx].status, status |
  246. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
  247. /* Tell the DMA to go */
  248. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  249. /* Wait for buffer to be transmitted */
  250. for (i = 0;
  251. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  252. i++) {
  253. if (i >= TOUT_LOOP) {
  254. printf("%s: tsec: tx error\n", dev->name);
  255. return result;
  256. }
  257. }
  258. priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
  259. result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
  260. return result;
  261. }
  262. #ifndef CONFIG_DM_ETH
  263. static int tsec_recv(struct eth_device *dev)
  264. {
  265. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  266. struct tsec __iomem *regs = priv->regs;
  267. while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  268. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  269. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  270. uchar *packet = net_rx_packets[priv->rx_idx];
  271. /* Send the packet up if there were no errors */
  272. if (!(status & RXBD_STATS))
  273. net_process_received_packet(packet, length - 4);
  274. else
  275. printf("Got error %x\n", (status & RXBD_STATS));
  276. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  277. status = RXBD_EMPTY;
  278. /* Set the wrap bit if this is the last element in the list */
  279. if ((priv->rx_idx + 1) == PKTBUFSRX)
  280. status |= RXBD_WRAP;
  281. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  282. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  283. }
  284. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  285. out_be32(&regs->ievent, IEVENT_BSY);
  286. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  287. }
  288. return -1;
  289. }
  290. #else
  291. static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
  292. {
  293. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  294. struct tsec __iomem *regs = priv->regs;
  295. int ret = -1;
  296. if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  297. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  298. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  299. u32 buf;
  300. /* Send the packet up if there were no errors */
  301. if (!(status & RXBD_STATS)) {
  302. buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
  303. *packetp = (uchar *)buf;
  304. ret = length - 4;
  305. } else {
  306. printf("Got error %x\n", (status & RXBD_STATS));
  307. }
  308. }
  309. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  310. out_be32(&regs->ievent, IEVENT_BSY);
  311. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  312. }
  313. return ret;
  314. }
  315. static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
  316. {
  317. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  318. u16 status;
  319. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  320. status = RXBD_EMPTY;
  321. /* Set the wrap bit if this is the last element in the list */
  322. if ((priv->rx_idx + 1) == PKTBUFSRX)
  323. status |= RXBD_WRAP;
  324. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  325. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  326. return 0;
  327. }
  328. #endif
  329. /* Stop the interface */
  330. #ifndef CONFIG_DM_ETH
  331. static void tsec_halt(struct eth_device *dev)
  332. #else
  333. static void tsec_halt(struct udevice *dev)
  334. #endif
  335. {
  336. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  337. struct tsec __iomem *regs = priv->regs;
  338. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  339. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  340. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  341. != (IEVENT_GRSC | IEVENT_GTSC))
  342. ;
  343. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  344. /* Shut down the PHY, as needed */
  345. phy_shutdown(priv->phydev);
  346. }
  347. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  348. /*
  349. * When MACCFG1[Rx_EN] is enabled during system boot as part
  350. * of the eTSEC port initialization sequence,
  351. * the eTSEC Rx logic may not be properly initialized.
  352. */
  353. void redundant_init(struct tsec_private *priv)
  354. {
  355. struct tsec __iomem *regs = priv->regs;
  356. uint t, count = 0;
  357. int fail = 1;
  358. static const u8 pkt[] = {
  359. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  360. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  361. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  362. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  363. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  364. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  365. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  366. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  367. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  368. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  369. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  370. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  371. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  372. 0x71, 0x72};
  373. /* Enable promiscuous mode */
  374. setbits_be32(&regs->rctrl, 0x8);
  375. /* Enable loopback mode */
  376. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  377. /* Enable transmit and receive */
  378. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  379. /* Tell the DMA it is clear to go */
  380. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  381. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  382. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  383. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  384. do {
  385. u16 status;
  386. tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
  387. /* Wait for buffer to be received */
  388. for (t = 0;
  389. in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
  390. t++) {
  391. if (t >= 10 * TOUT_LOOP) {
  392. printf("%s: tsec: rx error\n", priv->dev->name);
  393. break;
  394. }
  395. }
  396. if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
  397. fail = 0;
  398. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  399. status = RXBD_EMPTY;
  400. if ((priv->rx_idx + 1) == PKTBUFSRX)
  401. status |= RXBD_WRAP;
  402. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  403. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  404. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  405. out_be32(&regs->ievent, IEVENT_BSY);
  406. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  407. }
  408. if (fail) {
  409. printf("loopback recv packet error!\n");
  410. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  411. udelay(1000);
  412. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  413. }
  414. } while ((count++ < 4) && (fail == 1));
  415. if (fail)
  416. panic("eTSEC init fail!\n");
  417. /* Disable promiscuous mode */
  418. clrbits_be32(&regs->rctrl, 0x8);
  419. /* Disable loopback mode */
  420. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  421. }
  422. #endif
  423. /*
  424. * Set up the buffers and their descriptors, and bring up the
  425. * interface
  426. */
  427. static void startup_tsec(struct tsec_private *priv)
  428. {
  429. struct tsec __iomem *regs = priv->regs;
  430. u16 status;
  431. int i;
  432. /* reset the indices to zero */
  433. priv->rx_idx = 0;
  434. priv->tx_idx = 0;
  435. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  436. uint svr;
  437. #endif
  438. /* Point to the buffer descriptors */
  439. out_be32(&regs->tbase, (u32)&priv->txbd[0]);
  440. out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
  441. /* Initialize the Rx Buffer descriptors */
  442. for (i = 0; i < PKTBUFSRX; i++) {
  443. out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
  444. out_be16(&priv->rxbd[i].length, 0);
  445. out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
  446. }
  447. status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
  448. out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
  449. /* Initialize the TX Buffer Descriptors */
  450. for (i = 0; i < TX_BUF_CNT; i++) {
  451. out_be16(&priv->txbd[i].status, 0);
  452. out_be16(&priv->txbd[i].length, 0);
  453. out_be32(&priv->txbd[i].bufptr, 0);
  454. }
  455. status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
  456. out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
  457. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  458. svr = get_svr();
  459. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  460. redundant_init(priv);
  461. #endif
  462. /* Enable Transmit and Receive */
  463. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  464. /* Tell the DMA it is clear to go */
  465. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  466. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  467. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  468. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  469. }
  470. /*
  471. * Initializes data structures and registers for the controller,
  472. * and brings the interface up. Returns the link status, meaning
  473. * that it returns success if the link is up, failure otherwise.
  474. * This allows U-Boot to find the first active controller.
  475. */
  476. #ifndef CONFIG_DM_ETH
  477. static int tsec_init(struct eth_device *dev, struct bd_info *bd)
  478. #else
  479. static int tsec_init(struct udevice *dev)
  480. #endif
  481. {
  482. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  483. #ifdef CONFIG_DM_ETH
  484. struct eth_pdata *pdata = dev_get_platdata(dev);
  485. #else
  486. struct eth_device *pdata = dev;
  487. #endif
  488. struct tsec __iomem *regs = priv->regs;
  489. u32 tempval;
  490. int ret;
  491. /* Make sure the controller is stopped */
  492. tsec_halt(dev);
  493. /* Init MACCFG2. Defaults to GMII */
  494. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  495. /* Init ECNTRL */
  496. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  497. /*
  498. * Copy the station address into the address registers.
  499. * For a station address of 0x12345678ABCD in transmission
  500. * order (BE), MACnADDR1 is set to 0xCDAB7856 and
  501. * MACnADDR2 is set to 0x34120000.
  502. */
  503. tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
  504. (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
  505. out_be32(&regs->macstnaddr1, tempval);
  506. tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
  507. out_be32(&regs->macstnaddr2, tempval);
  508. /* Clear out (for the most part) the other registers */
  509. init_registers(regs);
  510. /* Ready the device for tx/rx */
  511. startup_tsec(priv);
  512. /* Start up the PHY */
  513. ret = phy_startup(priv->phydev);
  514. if (ret) {
  515. printf("Could not initialize PHY %s\n",
  516. priv->phydev->dev->name);
  517. return ret;
  518. }
  519. adjust_link(priv, priv->phydev);
  520. /* If there's no link, fail */
  521. return priv->phydev->link ? 0 : -1;
  522. }
  523. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  524. {
  525. struct tsec __iomem *regs = priv->regs;
  526. u32 ecntrl;
  527. ecntrl = in_be32(&regs->ecntrl);
  528. if (ecntrl & ECNTRL_SGMII_MODE)
  529. return PHY_INTERFACE_MODE_SGMII;
  530. if (ecntrl & ECNTRL_TBI_MODE) {
  531. if (ecntrl & ECNTRL_REDUCED_MODE)
  532. return PHY_INTERFACE_MODE_RTBI;
  533. else
  534. return PHY_INTERFACE_MODE_TBI;
  535. }
  536. if (ecntrl & ECNTRL_REDUCED_MODE) {
  537. phy_interface_t interface;
  538. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  539. return PHY_INTERFACE_MODE_RMII;
  540. interface = priv->interface;
  541. /*
  542. * This isn't autodetected, so it must
  543. * be set by the platform code.
  544. */
  545. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  546. interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  547. interface == PHY_INTERFACE_MODE_RGMII_RXID)
  548. return interface;
  549. return PHY_INTERFACE_MODE_RGMII;
  550. }
  551. if (priv->flags & TSEC_GIGABIT)
  552. return PHY_INTERFACE_MODE_GMII;
  553. return PHY_INTERFACE_MODE_MII;
  554. }
  555. /*
  556. * Discover which PHY is attached to the device, and configure it
  557. * properly. If the PHY is not recognized, then return 0
  558. * (failure). Otherwise, return 1
  559. */
  560. static int init_phy(struct tsec_private *priv)
  561. {
  562. struct phy_device *phydev;
  563. struct tsec __iomem *regs = priv->regs;
  564. u32 supported = (SUPPORTED_10baseT_Half |
  565. SUPPORTED_10baseT_Full |
  566. SUPPORTED_100baseT_Half |
  567. SUPPORTED_100baseT_Full);
  568. if (priv->flags & TSEC_GIGABIT)
  569. supported |= SUPPORTED_1000baseT_Full;
  570. /* Assign a Physical address to the TBI */
  571. out_be32(&regs->tbipa, priv->tbiaddr);
  572. priv->interface = tsec_get_interface(priv);
  573. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  574. tsec_configure_serdes(priv);
  575. #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
  576. if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link")))
  577. phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
  578. else
  579. phydev = dm_eth_phy_connect(priv->dev);
  580. #else
  581. phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
  582. priv->interface);
  583. #endif
  584. if (!phydev)
  585. return 0;
  586. phydev->supported &= supported;
  587. phydev->advertising = phydev->supported;
  588. priv->phydev = phydev;
  589. phy_config(phydev);
  590. return 1;
  591. }
  592. #ifndef CONFIG_DM_ETH
  593. /*
  594. * Initialize device structure. Returns success if PHY
  595. * initialization succeeded (i.e. if it recognizes the PHY)
  596. */
  597. static int tsec_initialize(struct bd_info *bis,
  598. struct tsec_info_struct *tsec_info)
  599. {
  600. struct tsec_private *priv;
  601. struct eth_device *dev;
  602. int i;
  603. dev = (struct eth_device *)malloc(sizeof(*dev));
  604. if (!dev)
  605. return 0;
  606. memset(dev, 0, sizeof(*dev));
  607. priv = (struct tsec_private *)malloc(sizeof(*priv));
  608. if (!priv) {
  609. free(dev);
  610. return 0;
  611. }
  612. priv->regs = tsec_info->regs;
  613. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  614. priv->phyaddr = tsec_info->phyaddr;
  615. priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  616. priv->flags = tsec_info->flags;
  617. strcpy(dev->name, tsec_info->devname);
  618. priv->interface = tsec_info->interface;
  619. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  620. priv->dev = dev;
  621. dev->iobase = 0;
  622. dev->priv = priv;
  623. dev->init = tsec_init;
  624. dev->halt = tsec_halt;
  625. dev->send = tsec_send;
  626. dev->recv = tsec_recv;
  627. dev->mcast = tsec_mcast_addr;
  628. /* Tell U-Boot to get the addr from the env */
  629. for (i = 0; i < 6; i++)
  630. dev->enetaddr[i] = 0;
  631. eth_register(dev);
  632. /* Reset the MAC */
  633. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  634. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  635. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  636. /* Try to initialize PHY here, and return */
  637. return init_phy(priv);
  638. }
  639. /*
  640. * Initialize all the TSEC devices
  641. *
  642. * Returns the number of TSEC devices that were initialized
  643. */
  644. int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
  645. int num)
  646. {
  647. int i;
  648. int count = 0;
  649. for (i = 0; i < num; i++) {
  650. int ret = tsec_initialize(bis, &tsecs[i]);
  651. if (ret > 0)
  652. count += ret;
  653. }
  654. return count;
  655. }
  656. int tsec_standard_init(struct bd_info *bis)
  657. {
  658. struct fsl_pq_mdio_info info;
  659. info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  660. info.name = DEFAULT_MII_NAME;
  661. fsl_pq_mdio_init(bis, &info);
  662. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  663. }
  664. #else /* CONFIG_DM_ETH */
  665. int tsec_probe(struct udevice *dev)
  666. {
  667. struct eth_pdata *pdata = dev_get_platdata(dev);
  668. struct tsec_private *priv = dev_get_priv(dev);
  669. struct ofnode_phandle_args phandle_args;
  670. u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  671. struct tsec_data *data;
  672. const char *phy_mode;
  673. fdt_addr_t reg;
  674. ofnode parent;
  675. int ret;
  676. data = (struct tsec_data *)dev_get_driver_data(dev);
  677. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  678. priv->regs = dev_remap_addr(dev);
  679. ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
  680. &phandle_args);
  681. if (ret == 0) {
  682. ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
  683. parent = ofnode_get_parent(phandle_args.node);
  684. if (!ofnode_valid(parent)) {
  685. printf("No parent node for TBI PHY?\n");
  686. return -ENOENT;
  687. }
  688. reg = ofnode_get_addr_index(parent, 0);
  689. if (reg == FDT_ADDR_T_NONE) {
  690. printf("No 'reg' property of MII for TBI PHY\n");
  691. return -ENOENT;
  692. }
  693. priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
  694. 0, MAP_NOCACHE);
  695. }
  696. priv->tbiaddr = tbiaddr;
  697. phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
  698. if (phy_mode)
  699. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  700. if (pdata->phy_interface == -1) {
  701. printf("Invalid PHY interface '%s'\n", phy_mode);
  702. return -EINVAL;
  703. }
  704. priv->interface = pdata->phy_interface;
  705. /* Initialize flags */
  706. priv->flags = TSEC_GIGABIT;
  707. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  708. priv->flags |= TSEC_SGMII;
  709. /* Reset the MAC */
  710. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  711. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  712. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  713. priv->dev = dev;
  714. priv->bus = miiphy_get_dev_by_name(dev->name);
  715. /* Try to initialize PHY here, and return */
  716. return !init_phy(priv);
  717. }
  718. int tsec_remove(struct udevice *dev)
  719. {
  720. struct tsec_private *priv = dev->priv;
  721. free(priv->phydev);
  722. mdio_unregister(priv->bus);
  723. mdio_free(priv->bus);
  724. return 0;
  725. }
  726. static const struct eth_ops tsec_ops = {
  727. .start = tsec_init,
  728. .send = tsec_send,
  729. .recv = tsec_recv,
  730. .free_pkt = tsec_free_pkt,
  731. .stop = tsec_halt,
  732. .mcast = tsec_mcast_addr,
  733. };
  734. static struct tsec_data etsec2_data = {
  735. .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
  736. };
  737. static struct tsec_data gianfar_data = {
  738. .mdio_regs_off = 0x0,
  739. };
  740. static const struct udevice_id tsec_ids[] = {
  741. { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
  742. { .compatible = "gianfar", .data = (ulong)&gianfar_data },
  743. { }
  744. };
  745. U_BOOT_DRIVER(eth_tsec) = {
  746. .name = "tsec",
  747. .id = UCLASS_ETH,
  748. .of_match = tsec_ids,
  749. .probe = tsec_probe,
  750. .remove = tsec_remove,
  751. .ops = &tsec_ops,
  752. .priv_auto_alloc_size = sizeof(struct tsec_private),
  753. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  754. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  755. };
  756. #endif /* CONFIG_DM_ETH */