xpedite550x.h 17 KB

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  1. /*
  2. * Copyright 2010 Extreme Engineering Solutions, Inc.
  3. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * xpedite550x board configuration file
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_SYS_BOARD_NAME "XPedite5500"
  16. #define CONFIG_SYS_FORM_PMC_XMC 1
  17. #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
  18. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  19. #ifndef CONFIG_SYS_TEXT_BASE
  20. #define CONFIG_SYS_TEXT_BASE 0xfff80000
  21. #endif
  22. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  23. #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
  24. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  25. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  26. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  27. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  28. /*
  29. * Multicore config
  30. */
  31. #define CONFIG_MP
  32. #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
  33. #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
  34. /*
  35. * DDR config
  36. */
  37. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  38. #define CONFIG_DDR_SPD
  39. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  40. #define SPD_EEPROM_ADDRESS 0x54
  41. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  42. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  43. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  44. #define CONFIG_DDR_ECC
  45. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  46. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  47. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  48. #define CONFIG_VERY_BIG_RAM
  49. #ifndef __ASSEMBLY__
  50. extern unsigned long get_board_sys_clk(unsigned long dummy);
  51. extern unsigned long get_board_ddr_clk(unsigned long dummy);
  52. #endif
  53. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
  54. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  55. /*
  56. * These can be toggled for performance analysis, otherwise use default.
  57. */
  58. #define CONFIG_L2_CACHE /* toggle L2 cache */
  59. #define CONFIG_BTB /* toggle branch predition */
  60. #define CONFIG_ENABLE_36BIT_PHYS 1
  61. #define CONFIG_SYS_CCSRBAR 0xef000000
  62. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  63. /*
  64. * Diagnostics
  65. */
  66. #define CONFIG_SYS_ALT_MEMTEST
  67. #define CONFIG_SYS_MEMTEST_START 0x10000000
  68. #define CONFIG_SYS_MEMTEST_END 0x20000000
  69. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  70. CONFIG_SYS_POST_I2C)
  71. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
  72. CONFIG_SYS_I2C_LM75_ADDR, \
  73. CONFIG_SYS_I2C_LM90_ADDR, \
  74. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  75. CONFIG_SYS_I2C_PCA953X_ADDR2, \
  76. CONFIG_SYS_I2C_PCA953X_ADDR3, \
  77. CONFIG_SYS_I2C_RTC_ADDR}
  78. /*
  79. * Memory map
  80. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  81. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  82. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  83. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  84. * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
  85. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  86. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  87. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  88. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  89. */
  90. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  91. /*
  92. * NAND flash configuration
  93. */
  94. #define CONFIG_SYS_NAND_BASE 0xef800000
  95. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  96. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
  97. CONFIG_SYS_NAND_BASE2}
  98. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  99. #define CONFIG_NAND_FSL_ELBC
  100. /*
  101. * NOR flash configuration
  102. */
  103. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  104. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  105. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  106. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  107. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  108. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  109. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  110. #define CONFIG_FLASH_CFI_DRIVER
  111. #define CONFIG_SYS_FLASH_CFI
  112. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  113. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  114. {0xf7f40000, 0xc0000} }
  115. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  116. /*
  117. * Chip select configuration
  118. */
  119. /* NOR Flash 0 on CS0 */
  120. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  121. BR_PS_16 | \
  122. BR_V)
  123. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
  124. OR_GPCM_CSNT | \
  125. OR_GPCM_XACS | \
  126. OR_GPCM_ACS_DIV2 | \
  127. OR_GPCM_SCY_8 | \
  128. OR_GPCM_TRLX | \
  129. OR_GPCM_EHTR | \
  130. OR_GPCM_EAD)
  131. /* NOR Flash 1 on CS1 */
  132. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  133. BR_PS_16 | \
  134. BR_V)
  135. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  136. /* NAND flash on CS2 */
  137. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  138. (2<<BR_DECC_SHIFT) | \
  139. BR_PS_8 | \
  140. BR_MS_FCM | \
  141. BR_V)
  142. /* NAND flash on CS2 */
  143. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  144. OR_FCM_PGS | \
  145. OR_FCM_CSCT | \
  146. OR_FCM_CST | \
  147. OR_FCM_CHT | \
  148. OR_FCM_SCY_1 | \
  149. OR_FCM_TRLX | \
  150. OR_FCM_EHTR)
  151. /* NAND flash on CS3 */
  152. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  153. (2<<BR_DECC_SHIFT) | \
  154. BR_PS_8 | \
  155. BR_MS_FCM | \
  156. BR_V)
  157. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  158. /*
  159. * Use L1 as initial stack
  160. */
  161. #define CONFIG_SYS_INIT_RAM_LOCK 1
  162. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  163. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  164. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  165. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  166. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  167. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  168. /*
  169. * Serial Port
  170. */
  171. #define CONFIG_CONS_INDEX 1
  172. #define CONFIG_SYS_NS16550_SERIAL
  173. #define CONFIG_SYS_NS16550_REG_SIZE 1
  174. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  175. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  176. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  177. #define CONFIG_SYS_BAUDRATE_TABLE \
  178. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  179. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  180. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  181. /*
  182. * I2C
  183. */
  184. #define CONFIG_SYS_I2C
  185. #define CONFIG_SYS_I2C_FSL
  186. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  187. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  188. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  189. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  190. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  191. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  192. /* I2C DS7505 temperature sensor */
  193. #define CONFIG_SYS_I2C_LM75_ADDR 0x48
  194. /* I2C ADT7461 temperature sensor */
  195. #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
  196. /* I2C EEPROM - AT24C128B */
  197. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  198. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  199. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  200. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  201. /* I2C RTC */
  202. #define CONFIG_RTC_M41T11 1
  203. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  204. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  205. /* GPIO */
  206. #define CONFIG_PCA953X
  207. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  208. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  209. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  210. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  211. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  212. /*
  213. * GPIO pin definitions, PU = pulled high, PD = pulled low
  214. */
  215. /* PCA9557 @ 0x18*/
  216. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  217. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
  218. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  219. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
  220. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  221. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
  222. /* PCA9557 @ 0x1e*/
  223. #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
  224. #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
  225. #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
  226. #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
  227. #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
  228. #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
  229. #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
  230. /* PCA9557 @ 0x1f */
  231. #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
  232. #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
  233. #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
  234. #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
  235. #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
  236. #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
  237. #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
  238. #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
  239. /*
  240. * General PCI
  241. * Memory space is mapped 1-1, but I/O space must start from 0.
  242. */
  243. /* controller 1 - PEX8112 or XMC, depending on build option */
  244. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  245. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  246. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  247. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  248. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  249. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  250. /*
  251. * Networking options
  252. */
  253. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  254. #define CONFIG_TSEC_TBI
  255. #define CONFIG_MII 1 /* MII PHY management */
  256. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  257. #define CONFIG_ETHPRIME "eTSEC2"
  258. /*
  259. * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
  260. * 1000mbps SGMII link
  261. */
  262. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  263. TBICR_PHY_RESET \
  264. | TBICR_FULL_DUPLEX \
  265. | TBICR_SPEED1_SET \
  266. )
  267. #define CONFIG_TSEC1 1
  268. #define CONFIG_TSEC1_NAME "eTSEC1"
  269. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  270. #define TSEC1_PHY_ADDR 1
  271. #define TSEC1_PHYIDX 0
  272. #define CONFIG_HAS_ETH0
  273. #define CONFIG_TSEC2 1
  274. #define CONFIG_TSEC2_NAME "eTSEC2"
  275. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  276. #define TSEC2_PHY_ADDR 2
  277. #define TSEC2_PHYIDX 0
  278. #define CONFIG_HAS_ETH1
  279. #define CONFIG_TSEC3 1
  280. #define CONFIG_TSEC3_NAME "eTSEC3"
  281. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  282. #define TSEC3_PHY_ADDR 3
  283. #define TSEC3_PHYIDX 0
  284. #define CONFIG_HAS_ETH2
  285. /*
  286. * USB
  287. */
  288. #define CONFIG_USB_EHCI_FSL
  289. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  290. /*
  291. * Miscellaneous configurable options
  292. */
  293. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  294. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  295. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  296. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  297. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  298. #define CONFIG_PREBOOT /* enable preboot variable */
  299. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  300. /*
  301. * For booting Linux, the board info and command line data
  302. * have to be in the first 16 MB of memory, since this is
  303. * the maximum mapped by the Linux kernel during initialization.
  304. */
  305. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  306. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  307. /*
  308. * Environment Configuration
  309. */
  310. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  311. #define CONFIG_ENV_SIZE 0x8000
  312. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
  313. /*
  314. * Flash memory map:
  315. * fff80000 - ffffffff Pri U-Boot (512 KB)
  316. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  317. * fff00000 - fff3ffff Pri FDT (256KB)
  318. * fef00000 - ffefffff Pri OS image (16MB)
  319. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  320. *
  321. * f7f80000 - f7ffffff Sec U-Boot (512 KB)
  322. * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
  323. * f7f00000 - f7f3ffff Sec FDT (256KB)
  324. * f6f00000 - f7efffff Sec OS image (16MB)
  325. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  326. */
  327. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  328. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
  329. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  330. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
  331. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  332. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  333. #define CONFIG_PROG_UBOOT1 \
  334. "$download_cmd $loadaddr $ubootfile; " \
  335. "if test $? -eq 0; then " \
  336. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  337. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  338. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  339. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  340. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  341. "if test $? -ne 0; then " \
  342. "echo PROGRAM FAILED; " \
  343. "else; " \
  344. "echo PROGRAM SUCCEEDED; " \
  345. "fi; " \
  346. "else; " \
  347. "echo DOWNLOAD FAILED; " \
  348. "fi;"
  349. #define CONFIG_PROG_UBOOT2 \
  350. "$download_cmd $loadaddr $ubootfile; " \
  351. "if test $? -eq 0; then " \
  352. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  353. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  354. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  355. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  356. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  357. "if test $? -ne 0; then " \
  358. "echo PROGRAM FAILED; " \
  359. "else; " \
  360. "echo PROGRAM SUCCEEDED; " \
  361. "fi; " \
  362. "else; " \
  363. "echo DOWNLOAD FAILED; " \
  364. "fi;"
  365. #define CONFIG_BOOT_OS_NET \
  366. "$download_cmd $osaddr $osfile; " \
  367. "if test $? -eq 0; then " \
  368. "if test -n $fdtaddr; then " \
  369. "$download_cmd $fdtaddr $fdtfile; " \
  370. "if test $? -eq 0; then " \
  371. "bootm $osaddr - $fdtaddr; " \
  372. "else; " \
  373. "echo FDT DOWNLOAD FAILED; " \
  374. "fi; " \
  375. "else; " \
  376. "bootm $osaddr; " \
  377. "fi; " \
  378. "else; " \
  379. "echo OS DOWNLOAD FAILED; " \
  380. "fi;"
  381. #define CONFIG_PROG_OS1 \
  382. "$download_cmd $osaddr $osfile; " \
  383. "if test $? -eq 0; then " \
  384. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  385. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  386. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  387. "if test $? -ne 0; then " \
  388. "echo OS PROGRAM FAILED; " \
  389. "else; " \
  390. "echo OS PROGRAM SUCCEEDED; " \
  391. "fi; " \
  392. "else; " \
  393. "echo OS DOWNLOAD FAILED; " \
  394. "fi;"
  395. #define CONFIG_PROG_OS2 \
  396. "$download_cmd $osaddr $osfile; " \
  397. "if test $? -eq 0; then " \
  398. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  399. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  400. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  401. "if test $? -ne 0; then " \
  402. "echo OS PROGRAM FAILED; " \
  403. "else; " \
  404. "echo OS PROGRAM SUCCEEDED; " \
  405. "fi; " \
  406. "else; " \
  407. "echo OS DOWNLOAD FAILED; " \
  408. "fi;"
  409. #define CONFIG_PROG_FDT1 \
  410. "$download_cmd $fdtaddr $fdtfile; " \
  411. "if test $? -eq 0; then " \
  412. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  413. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  414. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  415. "if test $? -ne 0; then " \
  416. "echo FDT PROGRAM FAILED; " \
  417. "else; " \
  418. "echo FDT PROGRAM SUCCEEDED; " \
  419. "fi; " \
  420. "else; " \
  421. "echo FDT DOWNLOAD FAILED; " \
  422. "fi;"
  423. #define CONFIG_PROG_FDT2 \
  424. "$download_cmd $fdtaddr $fdtfile; " \
  425. "if test $? -eq 0; then " \
  426. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  427. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  428. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  429. "if test $? -ne 0; then " \
  430. "echo FDT PROGRAM FAILED; " \
  431. "else; " \
  432. "echo FDT PROGRAM SUCCEEDED; " \
  433. "fi; " \
  434. "else; " \
  435. "echo FDT DOWNLOAD FAILED; " \
  436. "fi;"
  437. #define CONFIG_EXTRA_ENV_SETTINGS \
  438. "autoload=yes\0" \
  439. "download_cmd=tftp\0" \
  440. "console_args=console=ttyS0,115200\0" \
  441. "root_args=root=/dev/nfs rw\0" \
  442. "misc_args=ip=on\0" \
  443. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  444. "bootfile=/home/user/file\0" \
  445. "osfile=/home/user/board.uImage\0" \
  446. "fdtfile=/home/user/board.dtb\0" \
  447. "ubootfile=/home/user/u-boot.bin\0" \
  448. "fdtaddr=0x1e00000\0" \
  449. "osaddr=0x1000000\0" \
  450. "loadaddr=0x1000000\0" \
  451. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  452. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  453. "prog_os1="CONFIG_PROG_OS1"\0" \
  454. "prog_os2="CONFIG_PROG_OS2"\0" \
  455. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  456. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  457. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  458. "bootcmd_flash1=run set_bootargs; " \
  459. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  460. "bootcmd_flash2=run set_bootargs; " \
  461. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  462. "bootcmd=run bootcmd_flash1\0"
  463. #endif /* __CONFIG_H */