xpedite520x.h 15 KB

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  1. /*
  2. * Copyright 2008 Extreme Engineering Solutions, Inc.
  3. * Copyright 2004-2008 Freescale Semiconductor, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * xpedite520x board configuration file
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_SYS_BOARD_NAME "XPedite5200"
  16. #define CONFIG_SYS_FORM_PMC_XMC 1
  17. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  18. #ifndef CONFIG_SYS_TEXT_BASE
  19. #define CONFIG_SYS_TEXT_BASE 0xfff80000
  20. #endif
  21. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  22. #define CONFIG_PCI1 1 /* PCI controller 1 */
  23. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  24. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  25. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  26. /*
  27. * DDR config
  28. */
  29. #undef CONFIG_FSL_DDR_INTERACTIVE
  30. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  31. #define CONFIG_DDR_SPD
  32. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  33. #define SPD_EEPROM_ADDRESS 0x54
  34. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  35. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  36. #define CONFIG_DDR_ECC
  37. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  39. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  40. #define CONFIG_VERY_BIG_RAM
  41. #define CONFIG_SYS_CLK_FREQ 66666666
  42. /*
  43. * These can be toggled for performance analysis, otherwise use default.
  44. */
  45. #define CONFIG_L2_CACHE /* toggle L2 cache */
  46. #define CONFIG_BTB /* toggle branch predition */
  47. #define CONFIG_ENABLE_36BIT_PHYS 1
  48. #define CONFIG_SYS_CCSRBAR 0xef000000
  49. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  50. /*
  51. * Diagnostics
  52. */
  53. #define CONFIG_SYS_ALT_MEMTEST
  54. #define CONFIG_SYS_MEMTEST_START 0x10000000
  55. #define CONFIG_SYS_MEMTEST_END 0x20000000
  56. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  57. CONFIG_SYS_POST_I2C)
  58. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
  59. CONFIG_SYS_I2C_EEPROM_ADDR, \
  60. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  61. CONFIG_SYS_I2C_PCA953X_ADDR1, \
  62. CONFIG_SYS_I2C_RTC_ADDR}
  63. /*
  64. * Memory map
  65. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  66. * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
  67. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  68. * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
  69. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  70. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  71. * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
  72. * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
  73. */
  74. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  75. /*
  76. * NAND flash configuration
  77. */
  78. #define CONFIG_SYS_NAND_BASE 0xef800000
  79. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  80. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  81. #define CONFIG_NAND_ACTL
  82. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
  83. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
  84. #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
  85. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  86. /*
  87. * NOR flash configuration
  88. */
  89. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  90. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  91. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  92. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  93. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  94. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  95. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  96. #define CONFIG_FLASH_CFI_DRIVER
  97. #define CONFIG_SYS_FLASH_CFI
  98. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  99. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  100. {0xfbf40000, 0xc0000} }
  101. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  102. /*
  103. * Chip select configuration
  104. */
  105. /* NOR Flash 0 on CS0 */
  106. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  107. BR_PS_16 | \
  108. BR_V)
  109. #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
  110. OR_GPCM_ACS_DIV4 | \
  111. OR_GPCM_SCY_8)
  112. /* NOR Flash 1 on CS1 */
  113. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  114. BR_PS_16 | \
  115. BR_V)
  116. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  117. /* NAND flash on CS2 */
  118. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  119. BR_PS_8 | \
  120. BR_V)
  121. /* NAND flash on CS2 */
  122. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  123. OR_GPCM_BCTLD | \
  124. OR_GPCM_CSNT | \
  125. OR_GPCM_ACS_DIV4 | \
  126. OR_GPCM_SCY_4 | \
  127. OR_GPCM_TRLX | \
  128. OR_GPCM_EHTR)
  129. /* NAND flash on CS3 */
  130. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  131. BR_PS_8 | \
  132. BR_V)
  133. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  134. /*
  135. * Use L1 as initial stack
  136. */
  137. #define CONFIG_SYS_INIT_RAM_LOCK 1
  138. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  139. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
  140. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  141. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  142. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  143. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  144. /*
  145. * Serial Port
  146. */
  147. #define CONFIG_CONS_INDEX 1
  148. #define CONFIG_SYS_NS16550_SERIAL
  149. #define CONFIG_SYS_NS16550_REG_SIZE 1
  150. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  151. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  152. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  153. #define CONFIG_SYS_BAUDRATE_TABLE \
  154. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  155. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  156. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  157. /*
  158. * I2C
  159. */
  160. #define CONFIG_SYS_I2C
  161. #define CONFIG_SYS_I2C_FSL
  162. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  163. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  164. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  165. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  166. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  167. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  168. /* I2C EEPROM */
  169. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  170. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  171. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  172. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  173. /* I2C RTC */
  174. #define CONFIG_RTC_M41T11 1
  175. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  176. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  177. /* GPIO */
  178. #define CONFIG_PCA953X
  179. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  180. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
  181. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  182. /* PCA957 @ 0x18 */
  183. #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
  184. #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
  185. #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
  186. #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
  187. #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
  188. #define CONFIG_SYS_PCA953X_NVM_WP 0x20
  189. #define CONFIG_SYS_PCA953X_MONARCH 0x40
  190. #define CONFIG_SYS_PCA953X_EREADY 0x80
  191. /* PCA957 @ 0x19 */
  192. #define CONFIG_SYS_PCA953X_P14_IO0 0x01
  193. #define CONFIG_SYS_PCA953X_P14_IO1 0x02
  194. #define CONFIG_SYS_PCA953X_P14_IO2 0x04
  195. #define CONFIG_SYS_PCA953X_P14_IO3 0x08
  196. #define CONFIG_SYS_PCA953X_P14_IO4 0x10
  197. #define CONFIG_SYS_PCA953X_P14_IO5 0x20
  198. #define CONFIG_SYS_PCA953X_P14_IO6 0x40
  199. #define CONFIG_SYS_PCA953X_P14_IO7 0x80
  200. /* 12-bit ADC used to measure CPU diode */
  201. #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
  202. /*
  203. * General PCI
  204. * Memory space is mapped 1-1, but I/O space must start from 0.
  205. */
  206. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  207. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  208. #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
  209. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  210. #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
  211. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
  212. /*
  213. * Networking options
  214. */
  215. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  216. #define CONFIG_MII 1 /* MII PHY management */
  217. #define CONFIG_ETHPRIME "eTSEC1"
  218. #define CONFIG_TSEC1 1
  219. #define CONFIG_TSEC1_NAME "eTSEC1"
  220. #define TSEC1_FLAGS TSEC_GIGABIT
  221. #define TSEC1_PHY_ADDR 1
  222. #define TSEC1_PHYIDX 0
  223. #define CONFIG_HAS_ETH0
  224. #define CONFIG_TSEC2 1
  225. #define CONFIG_TSEC2_NAME "eTSEC2"
  226. #define TSEC2_FLAGS TSEC_GIGABIT
  227. #define TSEC2_PHY_ADDR 2
  228. #define TSEC2_PHYIDX 0
  229. #define CONFIG_HAS_ETH1
  230. #define CONFIG_TSEC3 1
  231. #define CONFIG_TSEC3_NAME "eTSEC3"
  232. #define TSEC3_FLAGS TSEC_GIGABIT
  233. #define TSEC3_PHY_ADDR 3
  234. #define TSEC3_PHYIDX 0
  235. #define CONFIG_HAS_ETH2
  236. #define CONFIG_TSEC4 1
  237. #define CONFIG_TSEC4_NAME "eTSEC4"
  238. #define TSEC4_FLAGS TSEC_GIGABIT
  239. #define TSEC4_PHY_ADDR 4
  240. #define TSEC4_PHYIDX 0
  241. #define CONFIG_HAS_ETH3
  242. /*
  243. * BOOTP options
  244. */
  245. #define CONFIG_BOOTP_BOOTFILESIZE
  246. #define CONFIG_BOOTP_BOOTPATH
  247. #define CONFIG_BOOTP_GATEWAY
  248. /*
  249. * Miscellaneous configurable options
  250. */
  251. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  252. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  253. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  254. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  255. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  256. #define CONFIG_PREBOOT /* enable preboot variable */
  257. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  258. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  259. /*
  260. * For booting Linux, the board info and command line data
  261. * have to be in the first 16 MB of memory, since this is
  262. * the maximum mapped by the Linux kernel during initialization.
  263. */
  264. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  265. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  266. /*
  267. * Environment Configuration
  268. */
  269. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  270. #define CONFIG_ENV_SIZE 0x8000
  271. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
  272. /*
  273. * Flash memory map:
  274. * fff80000 - ffffffff Pri U-Boot (512 KB)
  275. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  276. * fff00000 - fff3ffff Pri FDT (256KB)
  277. * fef00000 - ffefffff Pri OS image (16MB)
  278. * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
  279. *
  280. * fbf80000 - fbffffff Sec U-Boot (512 KB)
  281. * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
  282. * fbf00000 - fbf3ffff Sec FDT (256KB)
  283. * faf00000 - fbefffff Sec OS image (16MB)
  284. * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
  285. */
  286. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  287. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
  288. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  289. #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
  290. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  291. #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
  292. #define CONFIG_PROG_UBOOT1 \
  293. "$download_cmd $loadaddr $ubootfile; " \
  294. "if test $? -eq 0; then " \
  295. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  296. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  297. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  298. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  299. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  300. "if test $? -ne 0; then " \
  301. "echo PROGRAM FAILED; " \
  302. "else; " \
  303. "echo PROGRAM SUCCEEDED; " \
  304. "fi; " \
  305. "else; " \
  306. "echo DOWNLOAD FAILED; " \
  307. "fi;"
  308. #define CONFIG_PROG_UBOOT2 \
  309. "$download_cmd $loadaddr $ubootfile; " \
  310. "if test $? -eq 0; then " \
  311. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  312. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  313. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  314. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  315. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  316. "if test $? -ne 0; then " \
  317. "echo PROGRAM FAILED; " \
  318. "else; " \
  319. "echo PROGRAM SUCCEEDED; " \
  320. "fi; " \
  321. "else; " \
  322. "echo DOWNLOAD FAILED; " \
  323. "fi;"
  324. #define CONFIG_BOOT_OS_NET \
  325. "$download_cmd $osaddr $osfile; " \
  326. "if test $? -eq 0; then " \
  327. "if test -n $fdtaddr; then " \
  328. "$download_cmd $fdtaddr $fdtfile; " \
  329. "if test $? -eq 0; then " \
  330. "bootm $osaddr - $fdtaddr; " \
  331. "else; " \
  332. "echo FDT DOWNLOAD FAILED; " \
  333. "fi; " \
  334. "else; " \
  335. "bootm $osaddr; " \
  336. "fi; " \
  337. "else; " \
  338. "echo OS DOWNLOAD FAILED; " \
  339. "fi;"
  340. #define CONFIG_PROG_OS1 \
  341. "$download_cmd $osaddr $osfile; " \
  342. "if test $? -eq 0; then " \
  343. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  344. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  345. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  346. "if test $? -ne 0; then " \
  347. "echo OS PROGRAM FAILED; " \
  348. "else; " \
  349. "echo OS PROGRAM SUCCEEDED; " \
  350. "fi; " \
  351. "else; " \
  352. "echo OS DOWNLOAD FAILED; " \
  353. "fi;"
  354. #define CONFIG_PROG_OS2 \
  355. "$download_cmd $osaddr $osfile; " \
  356. "if test $? -eq 0; then " \
  357. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  358. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  359. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  360. "if test $? -ne 0; then " \
  361. "echo OS PROGRAM FAILED; " \
  362. "else; " \
  363. "echo OS PROGRAM SUCCEEDED; " \
  364. "fi; " \
  365. "else; " \
  366. "echo OS DOWNLOAD FAILED; " \
  367. "fi;"
  368. #define CONFIG_PROG_FDT1 \
  369. "$download_cmd $fdtaddr $fdtfile; " \
  370. "if test $? -eq 0; then " \
  371. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  372. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  373. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  374. "if test $? -ne 0; then " \
  375. "echo FDT PROGRAM FAILED; " \
  376. "else; " \
  377. "echo FDT PROGRAM SUCCEEDED; " \
  378. "fi; " \
  379. "else; " \
  380. "echo FDT DOWNLOAD FAILED; " \
  381. "fi;"
  382. #define CONFIG_PROG_FDT2 \
  383. "$download_cmd $fdtaddr $fdtfile; " \
  384. "if test $? -eq 0; then " \
  385. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  386. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  387. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  388. "if test $? -ne 0; then " \
  389. "echo FDT PROGRAM FAILED; " \
  390. "else; " \
  391. "echo FDT PROGRAM SUCCEEDED; " \
  392. "fi; " \
  393. "else; " \
  394. "echo FDT DOWNLOAD FAILED; " \
  395. "fi;"
  396. #define CONFIG_EXTRA_ENV_SETTINGS \
  397. "autoload=yes\0" \
  398. "download_cmd=tftp\0" \
  399. "console_args=console=ttyS0,115200\0" \
  400. "root_args=root=/dev/nfs rw\0" \
  401. "misc_args=ip=on\0" \
  402. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  403. "bootfile=/home/user/file\0" \
  404. "osfile=/home/user/board.uImage\0" \
  405. "fdtfile=/home/user/board.dtb\0" \
  406. "ubootfile=/home/user/u-boot.bin\0" \
  407. "fdtaddr=0x1e00000\0" \
  408. "osaddr=0x1000000\0" \
  409. "loadaddr=0x1000000\0" \
  410. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  411. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  412. "prog_os1="CONFIG_PROG_OS1"\0" \
  413. "prog_os2="CONFIG_PROG_OS2"\0" \
  414. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  415. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  416. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  417. "bootcmd_flash1=run set_bootargs; " \
  418. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  419. "bootcmd_flash2=run set_bootargs; " \
  420. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  421. "bootcmd=run bootcmd_flash1\0"
  422. #endif /* __CONFIG_H */