xpedite517x.h 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665
  1. /*
  2. * Copyright 2009 Extreme Engineering Solutions, Inc.
  3. * Copyright 2007-2008 Freescale Semiconductor, Inc.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * xpedite517x board configuration file
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_SYS_BOARD_NAME "XPedite5170"
  16. #define CONFIG_SYS_FORM_3U_VPX 1
  17. #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
  18. #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
  19. #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
  20. #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
  21. #define CONFIG_ALTIVEC 1
  22. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  23. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  24. #define CONFIG_PCIE1 1 /* PCIE controller 1 */
  25. #define CONFIG_PCIE2 1 /* PCIE controller 2 */
  26. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  27. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  28. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  29. /*
  30. * DDR config
  31. */
  32. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  33. #define CONFIG_DDR_SPD
  34. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  35. #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
  36. #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
  37. #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
  38. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  39. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  40. #define CONFIG_DDR_ECC
  41. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  42. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  43. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  44. #define CONFIG_VERY_BIG_RAM
  45. #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
  46. /*
  47. * virtual address to be used for temporary mappings. There
  48. * should be 128k free at this VA.
  49. */
  50. #define CONFIG_SYS_SCRATCH_VA 0xe0000000
  51. #ifndef __ASSEMBLY__
  52. extern unsigned long get_board_sys_clk(unsigned long dummy);
  53. #endif
  54. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
  55. /*
  56. * L2CR setup
  57. */
  58. #define CONFIG_SYS_L2
  59. #define L2_INIT 0
  60. #define L2_ENABLE (L2CR_L2E)
  61. /*
  62. * Base addresses -- Note these are effective addresses where the
  63. * actual resources get mapped (not physical addresses)
  64. */
  65. #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
  66. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  67. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  68. #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
  69. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  70. /*
  71. * Diagnostics
  72. */
  73. #define CONFIG_SYS_ALT_MEMTEST
  74. #define CONFIG_SYS_MEMTEST_START 0x10000000
  75. #define CONFIG_SYS_MEMTEST_END 0x20000000
  76. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
  77. CONFIG_SYS_POST_I2C)
  78. /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
  79. #define I2C_ADDR_IGNORE_LIST {0x50}
  80. /*
  81. * Memory map
  82. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  83. * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
  84. * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
  85. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  86. * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
  87. * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
  88. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  89. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  90. * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
  91. * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
  92. */
  93. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
  94. /*
  95. * NAND flash configuration
  96. */
  97. #define CONFIG_SYS_NAND_BASE 0xef800000
  98. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  99. #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
  100. #define CONFIG_SYS_MAX_NAND_DEVICE 2
  101. #define CONFIG_NAND_ACTL
  102. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
  103. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
  104. #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
  105. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  106. #define CONFIG_JFFS2_NAND
  107. /*
  108. * NOR flash configuration
  109. */
  110. #define CONFIG_SYS_FLASH_BASE 0xf8000000
  111. #define CONFIG_SYS_FLASH_BASE2 0xf0000000
  112. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  113. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  114. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  115. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  116. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  117. #define CONFIG_FLASH_CFI_DRIVER
  118. #define CONFIG_SYS_FLASH_CFI
  119. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  120. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
  121. {0xf7f00000, 0xc0000} }
  122. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  123. #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
  124. /*
  125. * Chip select configuration
  126. */
  127. /* NOR Flash 0 on CS0 */
  128. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  129. BR_PS_16 |\
  130. BR_V)
  131. #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
  132. OR_GPCM_CSNT |\
  133. OR_GPCM_XACS |\
  134. OR_GPCM_ACS_DIV2 |\
  135. OR_GPCM_SCY_8 |\
  136. OR_GPCM_TRLX |\
  137. OR_GPCM_EHTR |\
  138. OR_GPCM_EAD)
  139. /* NOR Flash 1 on CS1 */
  140. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
  141. BR_PS_16 |\
  142. BR_V)
  143. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  144. /* NAND flash on CS2 */
  145. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
  146. BR_PS_8 |\
  147. BR_V)
  148. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
  149. OR_GPCM_BCTLD |\
  150. OR_GPCM_CSNT |\
  151. OR_GPCM_ACS_DIV4 |\
  152. OR_GPCM_SCY_4 |\
  153. OR_GPCM_TRLX |\
  154. OR_GPCM_EHTR)
  155. /* Optional NAND flash on CS3 */
  156. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
  157. BR_PS_8 |\
  158. BR_V)
  159. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  160. /*
  161. * Use L1 as initial stack
  162. */
  163. #define CONFIG_SYS_INIT_RAM_LOCK 1
  164. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  165. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  166. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  167. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  168. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  169. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  170. /*
  171. * Serial Port
  172. */
  173. #define CONFIG_CONS_INDEX 1
  174. #define CONFIG_SYS_NS16550_SERIAL
  175. #define CONFIG_SYS_NS16550_REG_SIZE 1
  176. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  177. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  178. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  179. #define CONFIG_SYS_BAUDRATE_TABLE \
  180. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  181. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  182. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  183. /*
  184. * I2C
  185. */
  186. #define CONFIG_SYS_I2C
  187. #define CONFIG_SYS_I2C_FSL
  188. #define CONFIG_SYS_FSL_I2C_SPEED 100000
  189. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  190. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  191. #define CONFIG_SYS_FSL_I2C2_SPEED 100000
  192. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  193. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  194. /* PEX8518 slave I2C interface */
  195. #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
  196. /* I2C DS1631 temperature sensor */
  197. #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
  198. /* I2C EEPROM - AT24C128B */
  199. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  200. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  201. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  202. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  203. /* I2C RTC */
  204. #define CONFIG_RTC_M41T11 1
  205. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  206. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  207. /* GPIO */
  208. #define CONFIG_PCA953X
  209. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  210. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
  211. #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
  212. #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
  213. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  214. #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
  215. /*
  216. * PU = pulled high, PD = pulled low
  217. * I = input, O = output, IO = input/output
  218. */
  219. /* PCA9557 @ 0x18*/
  220. #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
  221. #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
  222. #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
  223. #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
  224. #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
  225. #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
  226. /* PCA9557 @ 0x1c*/
  227. #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
  228. #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
  229. #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
  230. #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
  231. #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
  232. #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
  233. #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
  234. #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
  235. /* PCA9557 @ 0x1e*/
  236. #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
  237. #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
  238. #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
  239. #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
  240. #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
  241. #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
  242. #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
  243. /* PCA9557 @ 0x1f */
  244. #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
  245. #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
  246. #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
  247. #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
  248. /*
  249. * General PCI
  250. * Memory space is mapped 1-1, but I/O space must start from 0.
  251. */
  252. /* PCIE1 - PEX8518 */
  253. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  254. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  255. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
  256. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  257. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
  258. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  259. /* PCIE2 - VPX P1 */
  260. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  261. #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
  262. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  263. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  264. #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
  265. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
  266. /*
  267. * Networking options
  268. */
  269. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  270. #define CONFIG_MII 1 /* MII PHY management */
  271. #define CONFIG_ETHPRIME "eTSEC1"
  272. #define CONFIG_TSEC1 1
  273. #define CONFIG_TSEC1_NAME "eTSEC1"
  274. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  275. #define TSEC1_PHY_ADDR 1
  276. #define TSEC1_PHYIDX 0
  277. #define CONFIG_HAS_ETH0
  278. #define CONFIG_TSEC2 1
  279. #define CONFIG_TSEC2_NAME "eTSEC2"
  280. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  281. #define TSEC2_PHY_ADDR 2
  282. #define TSEC2_PHYIDX 0
  283. #define CONFIG_HAS_ETH1
  284. /*
  285. * BAT mappings
  286. */
  287. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  288. #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  289. BATL_PP_RW |\
  290. BATL_CACHEINHIBIT |\
  291. BATL_GUARDEDSTORAGE)
  292. #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
  293. BATU_BL_1M |\
  294. BATU_VS |\
  295. BATU_VP)
  296. #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
  297. BATL_PP_RW |\
  298. BATL_CACHEINHIBIT)
  299. #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
  300. #endif
  301. /*
  302. * BAT0 2G Cacheable, non-guarded
  303. * 0x0000_0000 2G DDR
  304. */
  305. #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  306. #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
  307. #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
  308. #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
  309. /*
  310. * BAT1 1G Cache-inhibited, guarded
  311. * 0x8000_0000 1G PCI-Express 1 Memory
  312. */
  313. #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  314. BATL_PP_RW |\
  315. BATL_CACHEINHIBIT |\
  316. BATL_GUARDEDSTORAGE)
  317. #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
  318. BATU_BL_1G |\
  319. BATU_VS |\
  320. BATU_VP)
  321. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
  322. BATL_PP_RW |\
  323. BATL_CACHEINHIBIT)
  324. #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
  325. /*
  326. * BAT2 512M Cache-inhibited, guarded
  327. * 0xc000_0000 512M PCI-Express 2 Memory
  328. */
  329. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  330. BATL_PP_RW |\
  331. BATL_CACHEINHIBIT |\
  332. BATL_GUARDEDSTORAGE)
  333. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
  334. BATU_BL_512M |\
  335. BATU_VS |\
  336. BATU_VP)
  337. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
  338. BATL_PP_RW |\
  339. BATL_CACHEINHIBIT)
  340. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  341. /*
  342. * BAT3 1M Cache-inhibited, guarded
  343. * 0xe000_0000 1M CCSR
  344. */
  345. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
  346. BATL_PP_RW |\
  347. BATL_CACHEINHIBIT |\
  348. BATL_GUARDEDSTORAGE)
  349. #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
  350. BATU_BL_1M |\
  351. BATU_VS |\
  352. BATU_VP)
  353. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
  354. BATL_PP_RW |\
  355. BATL_CACHEINHIBIT)
  356. #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
  357. /*
  358. * BAT4 32M Cache-inhibited, guarded
  359. * 0xe200_0000 16M PCI-Express 1 I/O
  360. * 0xe300_0000 16M PCI-Express 2 I/0
  361. */
  362. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  363. BATL_PP_RW |\
  364. BATL_CACHEINHIBIT |\
  365. BATL_GUARDEDSTORAGE)
  366. #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
  367. BATU_BL_32M |\
  368. BATU_VS |\
  369. BATU_VP)
  370. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
  371. BATL_PP_RW |\
  372. BATL_CACHEINHIBIT)
  373. #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
  374. /*
  375. * BAT5 128K Cacheable, non-guarded
  376. * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
  377. */
  378. #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
  379. BATL_PP_RW |\
  380. BATL_MEMCOHERENCE)
  381. #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
  382. BATU_BL_128K |\
  383. BATU_VS |\
  384. BATU_VP)
  385. #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
  386. #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
  387. /*
  388. * BAT6 256M Cache-inhibited, guarded
  389. * 0xf000_0000 256M FLASH
  390. */
  391. #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
  392. BATL_PP_RW |\
  393. BATL_CACHEINHIBIT |\
  394. BATL_GUARDEDSTORAGE)
  395. #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
  396. BATU_BL_256M |\
  397. BATU_VS |\
  398. BATU_VP)
  399. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
  400. BATL_PP_RW |\
  401. BATL_MEMCOHERENCE)
  402. #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
  403. /* Map the last 1M of flash where we're running from reset */
  404. #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  405. BATL_PP_RW |\
  406. BATL_CACHEINHIBIT |\
  407. BATL_GUARDEDSTORAGE)
  408. #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
  409. BATU_BL_1M |\
  410. BATU_VS |\
  411. BATU_VP)
  412. #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
  413. BATL_PP_RW |\
  414. BATL_MEMCOHERENCE)
  415. #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
  416. /*
  417. * BAT7 64M Cache-inhibited, guarded
  418. * 0xe800_0000 64K NAND FLASH
  419. * 0xe804_0000 128K DUART Registers
  420. */
  421. #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
  422. BATL_PP_RW |\
  423. BATL_CACHEINHIBIT |\
  424. BATL_GUARDEDSTORAGE)
  425. #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
  426. BATU_BL_512K |\
  427. BATU_VS |\
  428. BATU_VP)
  429. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
  430. BATL_PP_RW |\
  431. BATL_CACHEINHIBIT)
  432. #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
  433. /*
  434. * Miscellaneous configurable options
  435. */
  436. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  437. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  438. #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
  439. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  440. #define CONFIG_PREBOOT /* enable preboot variable */
  441. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  442. /*
  443. * For booting Linux, the board info and command line data
  444. * have to be in the first 16 MB of memory, since this is
  445. * the maximum mapped by the Linux kernel during initialization.
  446. */
  447. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  448. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  449. /*
  450. * Environment Configuration
  451. */
  452. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
  453. #define CONFIG_ENV_SIZE 0x8000
  454. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  455. /*
  456. * Flash memory map:
  457. * fffc0000 - ffffffff Pri FDT (256KB)
  458. * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
  459. * fff00000 - fff7ffff Pri U-Boot (512 KB)
  460. * fef00000 - ffefffff Pri OS image (16MB)
  461. * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
  462. *
  463. * f7fc0000 - f7ffffff Sec FDT (256KB)
  464. * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
  465. * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
  466. * f6f00000 - f7efffff Sec OS image (16MB)
  467. * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
  468. */
  469. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
  470. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
  471. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
  472. #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
  473. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  474. #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
  475. #define CONFIG_PROG_UBOOT1 \
  476. "$download_cmd $loadaddr $ubootfile; " \
  477. "if test $? -eq 0; then " \
  478. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  479. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  480. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  481. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  482. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  483. "if test $? -ne 0; then " \
  484. "echo PROGRAM FAILED; " \
  485. "else; " \
  486. "echo PROGRAM SUCCEEDED; " \
  487. "fi; " \
  488. "else; " \
  489. "echo DOWNLOAD FAILED; " \
  490. "fi;"
  491. #define CONFIG_PROG_UBOOT2 \
  492. "$download_cmd $loadaddr $ubootfile; " \
  493. "if test $? -eq 0; then " \
  494. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  495. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  496. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  497. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  498. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  499. "if test $? -ne 0; then " \
  500. "echo PROGRAM FAILED; " \
  501. "else; " \
  502. "echo PROGRAM SUCCEEDED; " \
  503. "fi; " \
  504. "else; " \
  505. "echo DOWNLOAD FAILED; " \
  506. "fi;"
  507. #define CONFIG_BOOT_OS_NET \
  508. "$download_cmd $osaddr $osfile; " \
  509. "if test $? -eq 0; then " \
  510. "if test -n $fdtaddr; then " \
  511. "$download_cmd $fdtaddr $fdtfile; " \
  512. "if test $? -eq 0; then " \
  513. "bootm $osaddr - $fdtaddr; " \
  514. "else; " \
  515. "echo FDT DOWNLOAD FAILED; " \
  516. "fi; " \
  517. "else; " \
  518. "bootm $osaddr; " \
  519. "fi; " \
  520. "else; " \
  521. "echo OS DOWNLOAD FAILED; " \
  522. "fi;"
  523. #define CONFIG_PROG_OS1 \
  524. "$download_cmd $osaddr $osfile; " \
  525. "if test $? -eq 0; then " \
  526. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  527. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  528. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  529. "if test $? -ne 0; then " \
  530. "echo OS PROGRAM FAILED; " \
  531. "else; " \
  532. "echo OS PROGRAM SUCCEEDED; " \
  533. "fi; " \
  534. "else; " \
  535. "echo OS DOWNLOAD FAILED; " \
  536. "fi;"
  537. #define CONFIG_PROG_OS2 \
  538. "$download_cmd $osaddr $osfile; " \
  539. "if test $? -eq 0; then " \
  540. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  541. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  542. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  543. "if test $? -ne 0; then " \
  544. "echo OS PROGRAM FAILED; " \
  545. "else; " \
  546. "echo OS PROGRAM SUCCEEDED; " \
  547. "fi; " \
  548. "else; " \
  549. "echo OS DOWNLOAD FAILED; " \
  550. "fi;"
  551. #define CONFIG_PROG_FDT1 \
  552. "$download_cmd $fdtaddr $fdtfile; " \
  553. "if test $? -eq 0; then " \
  554. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  555. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  556. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  557. "if test $? -ne 0; then " \
  558. "echo FDT PROGRAM FAILED; " \
  559. "else; " \
  560. "echo FDT PROGRAM SUCCEEDED; " \
  561. "fi; " \
  562. "else; " \
  563. "echo FDT DOWNLOAD FAILED; " \
  564. "fi;"
  565. #define CONFIG_PROG_FDT2 \
  566. "$download_cmd $fdtaddr $fdtfile; " \
  567. "if test $? -eq 0; then " \
  568. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  569. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  570. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  571. "if test $? -ne 0; then " \
  572. "echo FDT PROGRAM FAILED; " \
  573. "else; " \
  574. "echo FDT PROGRAM SUCCEEDED; " \
  575. "fi; " \
  576. "else; " \
  577. "echo FDT DOWNLOAD FAILED; " \
  578. "fi;"
  579. #define CONFIG_EXTRA_ENV_SETTINGS \
  580. "autoload=yes\0" \
  581. "download_cmd=tftp\0" \
  582. "console_args=console=ttyS0,115200\0" \
  583. "root_args=root=/dev/nfs rw\0" \
  584. "misc_args=ip=on\0" \
  585. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  586. "bootfile=/home/user/file\0" \
  587. "osfile=/home/user/board.uImage\0" \
  588. "fdtfile=/home/user/board.dtb\0" \
  589. "ubootfile=/home/user/u-boot.bin\0" \
  590. "fdtaddr=0x1e00000\0" \
  591. "osaddr=0x1000000\0" \
  592. "loadaddr=0x1000000\0" \
  593. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  594. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  595. "prog_os1="CONFIG_PROG_OS1"\0" \
  596. "prog_os2="CONFIG_PROG_OS2"\0" \
  597. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  598. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  599. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  600. "bootcmd_flash1=run set_bootargs; " \
  601. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  602. "bootcmd_flash2=run set_bootargs; " \
  603. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  604. "bootcmd=run bootcmd_flash1\0"
  605. #endif /* __CONFIG_H */