ve8313.h 13 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  3. *
  4. * (C) Copyright 2010
  5. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /*
  10. * ve8313 board configuration file
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1
  18. #define CONFIG_MPC831x 1
  19. #define CONFIG_MPC8313 1
  20. #ifndef CONFIG_SYS_TEXT_BASE
  21. #define CONFIG_SYS_TEXT_BASE 0xfe000000
  22. #endif
  23. #define CONFIG_PCI_INDIRECT_BRIDGE 1
  24. #define CONFIG_FSL_ELBC 1
  25. /*
  26. * On-board devices
  27. *
  28. */
  29. #define CONFIG_83XX_CLKIN 32000000 /* in Hz */
  30. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  31. #define CONFIG_SYS_IMMR 0xE0000000
  32. #define CONFIG_SYS_MEMTEST_START 0x00001000
  33. #define CONFIG_SYS_MEMTEST_END 0x07000000
  34. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
  35. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
  36. /*
  37. * Device configurations
  38. */
  39. /*
  40. * DDR Setup
  41. */
  42. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  43. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  44. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  45. /*
  46. * Manually set up DDR parameters, as this board does not
  47. * have the SPD connected to I2C.
  48. */
  49. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  50. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  51. | CSCONFIG_AP \
  52. | CSCONFIG_ODT_RD_NEVER \
  53. | CSCONFIG_ODT_WR_ALL \
  54. | CSCONFIG_ROW_BIT_13 \
  55. | CSCONFIG_COL_BIT_10)
  56. /* 0x80840102 */
  57. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  58. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  59. | (0 << TIMING_CFG0_WRT_SHIFT) \
  60. | (3 << TIMING_CFG0_RRT_SHIFT) \
  61. | (2 << TIMING_CFG0_WWT_SHIFT) \
  62. | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  63. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  64. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  65. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  66. /* 0x0e720802 */
  67. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  68. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  69. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  70. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  71. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  72. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  73. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  74. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  75. /* 0x26256222 */
  76. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  77. | (5 << TIMING_CFG2_CPO_SHIFT) \
  78. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  79. | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  80. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  81. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  82. | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  83. /* 0x029028c7 */
  84. #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  85. | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  86. /* 0x03202000 */
  87. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  88. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  89. | SDRAM_CFG_DBW_32)
  90. /* 0x43080000 */
  91. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  92. #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  93. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  94. /* 0x44400232 */
  95. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  96. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  97. /*0x02000000*/
  98. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  99. | DDRCDR_PZ_NOMZ \
  100. | DDRCDR_NZ_NOMZ \
  101. | DDRCDR_M_ODR)
  102. /* 0x73000002 */
  103. /*
  104. * FLASH on the Local Bus
  105. */
  106. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  107. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  108. #define CONFIG_SYS_FLASH_BASE 0xFE000000
  109. #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
  110. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  111. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
  112. #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
  113. | BR_PS_16 /* 16 bit */ \
  114. | BR_MS_GPCM /* MSEL = GPCM */ \
  115. | BR_V) /* valid */
  116. #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  117. | OR_GPCM_CSNT \
  118. | OR_GPCM_ACS_DIV4 \
  119. | OR_GPCM_SCY_5 \
  120. | OR_GPCM_TRLX_SET \
  121. | OR_GPCM_EAD)
  122. /* 0xfe000c55 */
  123. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  124. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
  125. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  126. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
  127. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  128. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  129. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  130. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  131. #define CONFIG_SYS_RAMBOOT
  132. #endif
  133. #define CONFIG_SYS_INIT_RAM_LOCK 1
  134. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
  135. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  136. #define CONFIG_SYS_GBL_DATA_OFFSET \
  137. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  138. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  139. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  140. #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
  141. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  142. /*
  143. * Local Bus LCRR and LBCR regs
  144. */
  145. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
  146. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  147. #define CONFIG_SYS_LBC_LBCR 0x00040000
  148. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  149. /*
  150. * NAND settings
  151. */
  152. #define CONFIG_SYS_NAND_BASE 0x61000000
  153. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  154. #define CONFIG_NAND_FSL_ELBC 1
  155. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  156. #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
  157. | BR_PS_8 \
  158. | BR_DECC_CHK_GEN \
  159. | BR_MS_FCM \
  160. | BR_V) /* valid */
  161. /* 0x61000c21 */
  162. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  163. | OR_FCM_BCTLD \
  164. | OR_FCM_CHT \
  165. | OR_FCM_SCY_2 \
  166. | OR_FCM_RST \
  167. | OR_FCM_TRLX)
  168. /* 0xffff90ac */
  169. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
  170. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
  171. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
  172. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
  173. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  174. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  175. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  176. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  177. /* CS2 NvRAM */
  178. #define CONFIG_SYS_BR2_PRELIM (0x60000000 \
  179. | BR_PS_8 \
  180. | BR_V)
  181. /* 0x60000801 */
  182. #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
  183. | OR_GPCM_CSNT \
  184. | OR_GPCM_XACS \
  185. | OR_GPCM_SCY_3 \
  186. | OR_GPCM_TRLX_SET \
  187. | OR_GPCM_EHTR_SET \
  188. | OR_GPCM_EAD)
  189. /* 0xfffe0937 */
  190. /* local bus read write buffer mapping SRAM@0x64000000 */
  191. #define CONFIG_SYS_BR3_PRELIM (0x62000000 \
  192. | BR_PS_16 \
  193. | BR_V)
  194. /* 0x62001001 */
  195. #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
  196. | OR_GPCM_CSNT \
  197. | OR_GPCM_XACS \
  198. | OR_GPCM_SCY_15 \
  199. | OR_GPCM_TRLX_SET \
  200. | OR_GPCM_EHTR_SET \
  201. | OR_GPCM_EAD)
  202. /* 0xfe0009f7 */
  203. /*
  204. * Serial Port
  205. */
  206. #define CONFIG_CONS_INDEX 1
  207. #define CONFIG_SYS_NS16550_SERIAL
  208. #define CONFIG_SYS_NS16550_REG_SIZE 1
  209. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  210. #define CONFIG_SYS_BAUDRATE_TABLE \
  211. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  212. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  213. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  214. #if defined(CONFIG_PCI)
  215. /*
  216. * General PCI
  217. * Addresses are mapped 1-1.
  218. */
  219. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  220. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  221. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  222. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  223. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  224. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  225. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  226. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  227. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  228. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  229. #endif
  230. /*
  231. * TSEC
  232. */
  233. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  234. #define CONFIG_TSEC1
  235. #ifdef CONFIG_TSEC1
  236. #define CONFIG_HAS_ETH0
  237. #define CONFIG_TSEC1_NAME "TSEC1"
  238. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  239. #define TSEC1_PHY_ADDR 0x01
  240. #define TSEC1_FLAGS 0
  241. #define TSEC1_PHYIDX 0
  242. #endif
  243. /* Options are: TSEC[0-1] */
  244. #define CONFIG_ETHPRIME "TSEC1"
  245. /*
  246. * Environment
  247. */
  248. #define CONFIG_ENV_ADDR \
  249. (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  250. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  251. #define CONFIG_ENV_SIZE 0x4000
  252. /* Address and size of Redundant Environment Sector */
  253. #define CONFIG_ENV_OFFSET_REDUND \
  254. (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
  255. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  256. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  257. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  258. /*
  259. * BOOTP options
  260. */
  261. #define CONFIG_BOOTP_BOOTFILESIZE
  262. #define CONFIG_BOOTP_BOOTPATH
  263. #define CONFIG_BOOTP_GATEWAY
  264. #define CONFIG_BOOTP_HOSTNAME
  265. /*
  266. * Command line configuration.
  267. */
  268. #define CONFIG_CMDLINE_EDITING 1
  269. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  270. /*
  271. * Miscellaneous configurable options
  272. */
  273. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  274. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  275. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  276. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
  277. /*
  278. * For booting Linux, the board info and command line data
  279. * have to be in the first 256 MB of memory, since this is
  280. * the maximum mapped by the Linux kernel during initialization.
  281. */
  282. /* Initial Memory map for Linux*/
  283. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  284. /* 0x64050000 */
  285. #define CONFIG_SYS_HRCW_LOW (\
  286. 0x20000000 /* reserved, must be set */ |\
  287. HRCWL_DDRCM |\
  288. HRCWL_CSB_TO_CLKIN_4X1 | \
  289. HRCWL_CORE_TO_CSB_2_5X1)
  290. /* 0xa0600004 */
  291. #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
  292. HRCWH_PCI_ARBITER_ENABLE | \
  293. HRCWH_CORE_ENABLE | \
  294. HRCWH_FROM_0X00000100 | \
  295. HRCWH_BOOTSEQ_DISABLE |\
  296. HRCWH_SW_WATCHDOG_DISABLE |\
  297. HRCWH_ROM_LOC_LOCAL_16BIT | \
  298. HRCWH_TSEC1M_IN_MII | \
  299. HRCWH_BIG_ENDIAN | \
  300. HRCWH_LALE_EARLY)
  301. /* System IO Config */
  302. #define CONFIG_SYS_SICRH (0x01000000 | \
  303. SICRH_ETSEC2_B | \
  304. SICRH_ETSEC2_C | \
  305. SICRH_ETSEC2_D | \
  306. SICRH_ETSEC2_E | \
  307. SICRH_ETSEC2_F | \
  308. SICRH_ETSEC2_G | \
  309. SICRH_TSOBI1 | \
  310. SICRH_TSOBI2)
  311. /* 0x010fff03 */
  312. #define CONFIG_SYS_SICRL (SICRL_LBC | \
  313. SICRL_SPI_A | \
  314. SICRL_SPI_B | \
  315. SICRL_SPI_C | \
  316. SICRL_SPI_D | \
  317. SICRL_ETSEC2_A)
  318. /* 0x33fc0003) */
  319. #define CONFIG_SYS_HID0_INIT 0x000000000
  320. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  321. HID0_ENABLE_INSTRUCTION_CACHE)
  322. #define CONFIG_SYS_HID2 HID2_HBE
  323. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  324. /* DDR @ 0x00000000 */
  325. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
  326. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  327. | BATU_BL_256M \
  328. | BATU_VS \
  329. | BATU_VP)
  330. #if defined(CONFIG_PCI)
  331. /* PCI @ 0x80000000 */
  332. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
  333. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  334. | BATU_BL_256M \
  335. | BATU_VS \
  336. | BATU_VP)
  337. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  338. | BATL_PP_RW \
  339. | BATL_CACHEINHIBIT \
  340. | BATL_GUARDEDSTORAGE)
  341. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  342. | BATU_BL_256M \
  343. | BATU_VS \
  344. | BATU_VP)
  345. #else
  346. #define CONFIG_SYS_IBAT1L (0)
  347. #define CONFIG_SYS_IBAT1U (0)
  348. #define CONFIG_SYS_IBAT2L (0)
  349. #define CONFIG_SYS_IBAT2U (0)
  350. #endif
  351. /* PCI2 not supported on 8313 */
  352. #define CONFIG_SYS_IBAT3L (0)
  353. #define CONFIG_SYS_IBAT3U (0)
  354. #define CONFIG_SYS_IBAT4L (0)
  355. #define CONFIG_SYS_IBAT4U (0)
  356. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  357. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  358. | BATL_PP_RW \
  359. | BATL_CACHEINHIBIT \
  360. | BATL_GUARDEDSTORAGE)
  361. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  362. | BATU_BL_256M \
  363. | BATU_VS \
  364. | BATU_VP)
  365. /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  366. #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  367. #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  368. /* FPGA, SRAM, NAND @ 0x60000000 */
  369. #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  370. #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  371. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  372. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  373. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  374. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  375. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  376. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  377. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  378. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  379. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  380. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  381. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  382. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  383. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  384. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  385. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  386. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  387. #define CONFIG_NETDEV eth0
  388. #define CONFIG_HOSTNAME ve8313
  389. #define CONFIG_UBOOTPATH ve8313/u-boot.bin
  390. #define CONFIG_EXTRA_ENV_SETTINGS \
  391. "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  392. "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
  393. "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  394. "u-boot_addr_r=100000\0" \
  395. "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
  396. "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
  397. " +${filesize};" \
  398. "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
  399. "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
  400. " ${filesize};" \
  401. "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
  402. #endif /* __CONFIG_H */