sbc8548.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584
  1. /*
  2. * Copyright 2007,2009 Wind River Systems <www.windriver.com>
  3. * Copyright 2007 Embedded Specialties, Inc.
  4. * Copyright 2004, 2007 Freescale Semiconductor.
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. /*
  9. * sbc8548 board configuration file
  10. * Please refer to doc/README.sbc8548 for more info.
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. /*
  15. * Top level Makefile configuration choices
  16. */
  17. #ifdef CONFIG_PCI
  18. #define CONFIG_PCI_INDIRECT_BRIDGE
  19. #define CONFIG_PCI1
  20. #endif
  21. #ifdef CONFIG_66
  22. #define CONFIG_SYS_CLK_DIV 1
  23. #endif
  24. #ifdef CONFIG_33
  25. #define CONFIG_SYS_CLK_DIV 2
  26. #endif
  27. #ifdef CONFIG_PCIE
  28. #define CONFIG_PCIE1
  29. #endif
  30. /*
  31. * High Level Configuration Options
  32. */
  33. /*
  34. * If you want to boot from the SODIMM flash, instead of the soldered
  35. * on flash, set this, and change JP12, SW2:8 accordingly.
  36. */
  37. #undef CONFIG_SYS_ALT_BOOT
  38. #ifndef CONFIG_SYS_TEXT_BASE
  39. #ifdef CONFIG_SYS_ALT_BOOT
  40. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  41. #else
  42. #define CONFIG_SYS_TEXT_BASE 0xfffa0000
  43. #endif
  44. #endif
  45. #undef CONFIG_RIO
  46. #ifdef CONFIG_PCI
  47. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  48. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  49. #endif
  50. #ifdef CONFIG_PCIE1
  51. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  52. #endif
  53. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  54. #define CONFIG_ENV_OVERWRITE
  55. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  56. /*
  57. * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  58. */
  59. #ifndef CONFIG_SYS_CLK_DIV
  60. #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
  61. #endif
  62. #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
  63. /*
  64. * These can be toggled for performance analysis, otherwise use default.
  65. */
  66. #define CONFIG_L2_CACHE /* toggle L2 cache */
  67. #define CONFIG_BTB /* toggle branch predition */
  68. /*
  69. * Only possible on E500 Version 2 or newer cores.
  70. */
  71. #define CONFIG_ENABLE_36BIT_PHYS 1
  72. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  73. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  74. #define CONFIG_SYS_MEMTEST_END 0x00400000
  75. #define CONFIG_SYS_CCSRBAR 0xe0000000
  76. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  77. /* DDR Setup */
  78. #undef CONFIG_FSL_DDR_INTERACTIVE
  79. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  80. /*
  81. * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
  82. * to collide, meaning you couldn't reliably read either. So
  83. * physically remove the LBC PC100 SDRAM module from the board
  84. * before enabling the two SPD options below, or check that you
  85. * have the hardware fix on your board via "i2c probe" and looking
  86. * for a device at 0x53.
  87. */
  88. #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  89. #undef CONFIG_DDR_SPD
  90. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  91. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  92. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  93. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  94. #define CONFIG_VERY_BIG_RAM
  95. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  96. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  97. /*
  98. * The hardware fix for the I2C address collision puts the DDR
  99. * SPD at 0x53, but if we are running on an older board w/o the
  100. * fix, it will still be at 0x51. We check 0x53 1st.
  101. */
  102. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  103. #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
  104. /*
  105. * Make sure required options are set
  106. */
  107. #ifndef CONFIG_SPD_EEPROM
  108. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  109. #define CONFIG_SYS_DDR_CONTROL 0xc300c000
  110. #endif
  111. #undef CONFIG_CLOCKS_IN_MHZ
  112. /*
  113. * FLASH on the Local Bus
  114. * Two banks, one 8MB the other 64MB, using the CFI driver.
  115. * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
  116. * CS0 the 8MB boot flash, and CS6 the 64MB flash.
  117. *
  118. * Default:
  119. * ec00_0000 efff_ffff 64MB SODIMM
  120. * ff80_0000 ffff_ffff 8MB soldered flash
  121. *
  122. * Alternate:
  123. * ef80_0000 efff_ffff 8MB soldered flash
  124. * fc00_0000 ffff_ffff 64MB SODIMM
  125. *
  126. * BR0_8M:
  127. * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
  128. * Port Size = 8 bits = BRx[19:20] = 01
  129. * Use GPCM = BRx[24:26] = 000
  130. * Valid = BRx[31] = 1
  131. *
  132. * BR0_64M:
  133. * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
  134. * Port Size = 32 bits = BRx[19:20] = 11
  135. *
  136. * 0 4 8 12 16 20 24 28
  137. * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
  138. * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
  139. */
  140. #define CONFIG_SYS_BR0_8M 0xff800801
  141. #define CONFIG_SYS_BR0_64M 0xfc001801
  142. /*
  143. * BR6_8M:
  144. * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
  145. * Port Size = 8 bits = BRx[19:20] = 01
  146. * Use GPCM = BRx[24:26] = 000
  147. * Valid = BRx[31] = 1
  148. * BR6_64M:
  149. * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
  150. * Port Size = 32 bits = BRx[19:20] = 11
  151. *
  152. * 0 4 8 12 16 20 24 28
  153. * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
  154. * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
  155. */
  156. #define CONFIG_SYS_BR6_8M 0xef800801
  157. #define CONFIG_SYS_BR6_64M 0xec001801
  158. /*
  159. * OR0_8M:
  160. * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
  161. * XAM = OR0[17:18] = 11
  162. * CSNT = OR0[20] = 1
  163. * ACS = half cycle delay = OR0[21:22] = 11
  164. * SCY = 6 = OR0[24:27] = 0110
  165. * TRLX = use relaxed timing = OR0[29] = 1
  166. * EAD = use external address latch delay = OR0[31] = 1
  167. *
  168. * OR0_64M:
  169. * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
  170. *
  171. *
  172. * 0 4 8 12 16 20 24 28
  173. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
  174. * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
  175. */
  176. #define CONFIG_SYS_OR0_8M 0xff806e65
  177. #define CONFIG_SYS_OR0_64M 0xfc006e65
  178. /*
  179. * OR6_8M:
  180. * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
  181. * XAM = OR6[17:18] = 11
  182. * CSNT = OR6[20] = 1
  183. * ACS = half cycle delay = OR6[21:22] = 11
  184. * SCY = 6 = OR6[24:27] = 0110
  185. * TRLX = use relaxed timing = OR6[29] = 1
  186. * EAD = use external address latch delay = OR6[31] = 1
  187. *
  188. * OR6_64M:
  189. * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
  190. *
  191. * 0 4 8 12 16 20 24 28
  192. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
  193. * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
  194. */
  195. #define CONFIG_SYS_OR6_8M 0xff806e65
  196. #define CONFIG_SYS_OR6_64M 0xfc006e65
  197. #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
  198. #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
  199. #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
  200. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
  201. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
  202. #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
  203. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
  204. #else /* JP12 in alternate position */
  205. #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
  206. #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
  207. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
  208. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
  209. #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
  210. #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
  211. #endif
  212. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
  213. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
  214. CONFIG_SYS_ALT_FLASH}
  215. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  216. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
  217. #undef CONFIG_SYS_FLASH_CHECKSUM
  218. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  219. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  220. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  221. #define CONFIG_FLASH_CFI_DRIVER
  222. #define CONFIG_SYS_FLASH_CFI
  223. #define CONFIG_SYS_FLASH_EMPTY_INFO
  224. /* CS5 = Local bus peripherals controlled by the EPLD */
  225. #define CONFIG_SYS_BR5_PRELIM 0xf8000801
  226. #define CONFIG_SYS_OR5_PRELIM 0xff006e65
  227. #define CONFIG_SYS_EPLD_BASE 0xf8000000
  228. #define CONFIG_SYS_LED_DISP_BASE 0xf8000000
  229. #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
  230. #define CONFIG_SYS_BD_REV 0xf8300000
  231. #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
  232. /*
  233. * SDRAM on the Local Bus (CS3 and CS4)
  234. * Note that most boards have a hardware errata where both the
  235. * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
  236. * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
  237. * A hardware workaround is also available, see README.sbc8548 file.
  238. */
  239. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  240. #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
  241. /*
  242. * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
  243. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  244. *
  245. * For BR3, need:
  246. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  247. * port-size = 32-bits = BR2[19:20] = 11
  248. * no parity checking = BR2[21:22] = 00
  249. * SDRAM for MSEL = BR2[24:26] = 011
  250. * Valid = BR[31] = 1
  251. *
  252. * 0 4 8 12 16 20 24 28
  253. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  254. *
  255. */
  256. #define CONFIG_SYS_BR3_PRELIM 0xf0001861
  257. /*
  258. * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  259. *
  260. * For OR3, need:
  261. * 64MB mask for AM, OR3[0:7] = 1111 1100
  262. * XAM, OR3[17:18] = 11
  263. * 10 columns OR3[19-21] = 011
  264. * 12 rows OR3[23-25] = 011
  265. * EAD set for extra time OR[31] = 0
  266. *
  267. * 0 4 8 12 16 20 24 28
  268. * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
  269. */
  270. #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
  271. /*
  272. * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
  273. * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
  274. *
  275. * For BR4, need:
  276. * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
  277. * port-size = 32-bits = BR2[19:20] = 11
  278. * no parity checking = BR2[21:22] = 00
  279. * SDRAM for MSEL = BR2[24:26] = 011
  280. * Valid = BR[31] = 1
  281. *
  282. * 0 4 8 12 16 20 24 28
  283. * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
  284. *
  285. */
  286. #define CONFIG_SYS_BR4_PRELIM 0xf4001861
  287. /*
  288. * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  289. *
  290. * For OR4, need:
  291. * 64MB mask for AM, OR3[0:7] = 1111 1100
  292. * XAM, OR3[17:18] = 11
  293. * 10 columns OR3[19-21] = 011
  294. * 12 rows OR3[23-25] = 011
  295. * EAD set for extra time OR[31] = 0
  296. *
  297. * 0 4 8 12 16 20 24 28
  298. * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
  299. */
  300. #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
  301. #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
  302. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  303. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  304. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  305. /*
  306. * Common settings for all Local Bus SDRAM commands.
  307. */
  308. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  309. | LSDMR_BSMA1516 \
  310. | LSDMR_PRETOACT3 \
  311. | LSDMR_ACTTORW3 \
  312. | LSDMR_BUFCMD \
  313. | LSDMR_BL8 \
  314. | LSDMR_WRC2 \
  315. | LSDMR_CL3 \
  316. )
  317. #define CONFIG_SYS_LBC_LSDMR_PCHALL \
  318. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  319. #define CONFIG_SYS_LBC_LSDMR_ARFRSH \
  320. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  321. #define CONFIG_SYS_LBC_LSDMR_MRW \
  322. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  323. #define CONFIG_SYS_LBC_LSDMR_RFEN \
  324. (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
  325. #define CONFIG_SYS_INIT_RAM_LOCK 1
  326. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  327. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  328. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
  329. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  330. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  331. /*
  332. * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
  333. * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
  334. * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
  335. * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
  336. * thing for MONITOR_LEN in both cases.
  337. */
  338. #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
  339. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  340. /* Serial Port */
  341. #define CONFIG_CONS_INDEX 1
  342. #define CONFIG_SYS_NS16550_SERIAL
  343. #define CONFIG_SYS_NS16550_REG_SIZE 1
  344. #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
  345. #define CONFIG_SYS_BAUDRATE_TABLE \
  346. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  347. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  348. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  349. /*
  350. * I2C
  351. */
  352. #define CONFIG_SYS_I2C
  353. #define CONFIG_SYS_I2C_FSL
  354. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  355. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  356. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  357. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  358. /*
  359. * General PCI
  360. * Memory space is mapped 1-1, but I/O space must start from 0.
  361. */
  362. #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
  363. #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  364. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  365. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  366. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  367. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  368. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  369. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  370. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  371. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
  372. #ifdef CONFIG_PCIE1
  373. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  374. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  375. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  376. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  377. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
  378. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  379. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
  380. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
  381. #endif
  382. #ifdef CONFIG_RIO
  383. /*
  384. * RapidIO MMU
  385. */
  386. #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
  387. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
  388. #endif
  389. #if defined(CONFIG_PCI)
  390. #undef CONFIG_EEPRO100
  391. #undef CONFIG_TULIP
  392. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  393. #endif /* CONFIG_PCI */
  394. #if defined(CONFIG_TSEC_ENET)
  395. #define CONFIG_MII 1 /* MII PHY management */
  396. #define CONFIG_TSEC1 1
  397. #define CONFIG_TSEC1_NAME "eTSEC0"
  398. #define CONFIG_TSEC2 1
  399. #define CONFIG_TSEC2_NAME "eTSEC1"
  400. #undef CONFIG_MPC85XX_FEC
  401. #define TSEC1_PHY_ADDR 0x19
  402. #define TSEC2_PHY_ADDR 0x1a
  403. #define TSEC1_PHYIDX 0
  404. #define TSEC2_PHYIDX 0
  405. #define TSEC1_FLAGS TSEC_GIGABIT
  406. #define TSEC2_FLAGS TSEC_GIGABIT
  407. /* Options are: eTSEC[0-3] */
  408. #define CONFIG_ETHPRIME "eTSEC0"
  409. #endif /* CONFIG_TSEC_ENET */
  410. /*
  411. * Environment
  412. */
  413. #define CONFIG_ENV_SIZE 0x2000
  414. #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
  415. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
  416. #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
  417. #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
  418. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  419. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  420. #else
  421. #warning undefined environment size/location.
  422. #endif
  423. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  424. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  425. /*
  426. * BOOTP options
  427. */
  428. #define CONFIG_BOOTP_BOOTFILESIZE
  429. #define CONFIG_BOOTP_BOOTPATH
  430. #define CONFIG_BOOTP_GATEWAY
  431. #define CONFIG_BOOTP_HOSTNAME
  432. #undef CONFIG_WATCHDOG /* watchdog disabled */
  433. /*
  434. * Miscellaneous configurable options
  435. */
  436. #define CONFIG_CMDLINE_EDITING /* undef to save memory */
  437. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  438. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  439. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  440. /*
  441. * For booting Linux, the board info and command line data
  442. * have to be in the first 8 MB of memory, since this is
  443. * the maximum mapped by the Linux kernel during initialization.
  444. */
  445. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  446. #if defined(CONFIG_CMD_KGDB)
  447. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  448. #endif
  449. /*
  450. * Environment Configuration
  451. */
  452. #if defined(CONFIG_TSEC_ENET)
  453. #define CONFIG_HAS_ETH0
  454. #define CONFIG_HAS_ETH1
  455. #endif
  456. #define CONFIG_IPADDR 192.168.0.55
  457. #define CONFIG_HOSTNAME sbc8548
  458. #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
  459. #define CONFIG_BOOTFILE "/uImage"
  460. #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
  461. #define CONFIG_SERVERIP 192.168.0.2
  462. #define CONFIG_GATEWAYIP 192.168.0.1
  463. #define CONFIG_NETMASK 255.255.255.0
  464. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  465. #define CONFIG_EXTRA_ENV_SETTINGS \
  466. "netdev=eth0\0" \
  467. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  468. "tftpflash=tftpboot $loadaddr $uboot; " \
  469. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  470. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  471. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  472. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  473. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  474. "consoledev=ttyS0\0" \
  475. "ramdiskaddr=2000000\0" \
  476. "ramdiskfile=uRamdisk\0" \
  477. "fdtaddr=1e00000\0" \
  478. "fdtfile=sbc8548.dtb\0"
  479. #define CONFIG_NFSBOOTCOMMAND \
  480. "setenv bootargs root=/dev/nfs rw " \
  481. "nfsroot=$serverip:$rootpath " \
  482. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  483. "console=$consoledev,$baudrate $othbootargs;" \
  484. "tftp $loadaddr $bootfile;" \
  485. "tftp $fdtaddr $fdtfile;" \
  486. "bootm $loadaddr - $fdtaddr"
  487. #define CONFIG_RAMBOOTCOMMAND \
  488. "setenv bootargs root=/dev/ram rw " \
  489. "console=$consoledev,$baudrate $othbootargs;" \
  490. "tftp $ramdiskaddr $ramdiskfile;" \
  491. "tftp $loadaddr $bootfile;" \
  492. "tftp $fdtaddr $fdtfile;" \
  493. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  494. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  495. #endif /* __CONFIG_H */