sbc8349.h 19 KB

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  1. /*
  2. * WindRiver SBC8349 U-Boot configuration file.
  3. * Copyright (c) 2006, 2007 Wind River Systems, Inc.
  4. *
  5. * Paul Gortmaker <paul.gortmaker@windriver.com>
  6. * Based on the MPC8349EMDS config.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * sbc8349 board configuration file.
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. /*
  16. * High Level Configuration Options
  17. */
  18. #define CONFIG_E300 1 /* E300 Family */
  19. #define CONFIG_MPC834x 1 /* MPC834x family */
  20. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  21. #define CONFIG_SYS_TEXT_BASE 0xFF800000
  22. /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  24. /*
  25. * The default if PCI isn't enabled, or if no PCI clk setting is given
  26. * is 66MHz; this is what the board defaults to when the PCI slot is
  27. * physically empty. The board will automatically (i.e w/o jumpers)
  28. * clock down to 33MHz if you insert a 33MHz PCI card.
  29. */
  30. #ifdef CONFIG_PCI_33M
  31. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  32. #else /* 66M */
  33. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  34. #endif
  35. #ifndef CONFIG_SYS_CLK_FREQ
  36. #ifdef CONFIG_PCI_33M
  37. #define CONFIG_SYS_CLK_FREQ 33000000
  38. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  39. #else /* 66M */
  40. #define CONFIG_SYS_CLK_FREQ 66000000
  41. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  42. #endif
  43. #endif
  44. #define CONFIG_SYS_IMMR 0xE0000000
  45. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  46. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  47. #define CONFIG_SYS_MEMTEST_END 0x00100000
  48. /*
  49. * DDR Setup
  50. */
  51. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  52. #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  53. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  54. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
  55. /*
  56. * 32-bit data path mode.
  57. *
  58. * Please note that using this mode for devices with the real density of 64-bit
  59. * effectively reduces the amount of available memory due to the effect of
  60. * wrapping around while translating address to row/columns, for example in the
  61. * 256MB module the upper 128MB get aliased with contents of the lower
  62. * 128MB); normally this define should be used for devices with real 32-bit
  63. * data path.
  64. */
  65. #undef CONFIG_DDR_32BIT
  66. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  67. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  68. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  69. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
  70. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  71. #define CONFIG_DDR_2T_TIMING
  72. #if defined(CONFIG_SPD_EEPROM)
  73. /*
  74. * Determine DDR configuration from I2C interface.
  75. */
  76. #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
  77. #else
  78. /*
  79. * Manually set up DDR parameters
  80. * NB: manual DDR setup untested on sbc834x
  81. */
  82. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  83. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  84. | CSCONFIG_ROW_BIT_13 \
  85. | CSCONFIG_COL_BIT_10)
  86. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  87. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  88. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  89. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  90. #if defined(CONFIG_DDR_32BIT)
  91. /* set burst length to 8 for 32-bit data path */
  92. /* DLL,normal,seq,4/2.5, 8 burst len */
  93. #define CONFIG_SYS_DDR_MODE 0x00000023
  94. #else
  95. /* the default burst length is 4 - for 64-bit data path */
  96. /* DLL,normal,seq,4/2.5, 4 burst len */
  97. #define CONFIG_SYS_DDR_MODE 0x00000022
  98. #endif
  99. #endif
  100. /*
  101. * SDRAM on the Local Bus
  102. */
  103. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  104. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  105. /*
  106. * FLASH on the Local Bus
  107. */
  108. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  109. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  110. #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
  111. #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
  112. /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
  113. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  114. | BR_PS_16 /* 16 bit port */ \
  115. | BR_MS_GPCM /* MSEL = GPCM */ \
  116. | BR_V) /* valid */
  117. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  118. | OR_GPCM_XAM \
  119. | OR_GPCM_CSNT \
  120. | OR_GPCM_ACS_DIV2 \
  121. | OR_GPCM_XACS \
  122. | OR_GPCM_SCY_15 \
  123. | OR_GPCM_TRLX_SET \
  124. | OR_GPCM_EHTR_SET \
  125. | OR_GPCM_EAD)
  126. /* 0xFF806FF7 */
  127. /* window base at flash base */
  128. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  129. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  130. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  131. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  132. #undef CONFIG_SYS_FLASH_CHECKSUM
  133. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  134. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  135. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  136. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  137. #define CONFIG_SYS_RAMBOOT
  138. #else
  139. #undef CONFIG_SYS_RAMBOOT
  140. #endif
  141. #define CONFIG_SYS_INIT_RAM_LOCK 1
  142. /* Initial RAM address */
  143. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  144. /* Size of used area in RAM*/
  145. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  146. #define CONFIG_SYS_GBL_DATA_OFFSET \
  147. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  148. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  149. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  150. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  151. /*
  152. * Local Bus LCRR and LBCR regs
  153. * LCRR: DLL bypass, Clock divider is 4
  154. * External Local Bus rate is
  155. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  156. */
  157. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  158. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  159. #define CONFIG_SYS_LBC_LBCR 0x00000000
  160. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  161. #ifdef CONFIG_SYS_LB_SDRAM
  162. /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
  163. /*
  164. * Base Register 2 and Option Register 2 configure SDRAM.
  165. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  166. *
  167. * For BR2, need:
  168. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  169. * port-size = 32-bits = BR2[19:20] = 11
  170. * no parity checking = BR2[21:22] = 00
  171. * SDRAM for MSEL = BR2[24:26] = 011
  172. * Valid = BR[31] = 1
  173. *
  174. * 0 4 8 12 16 20 24 28
  175. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  176. */
  177. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  178. | BR_PS_32 \
  179. | BR_MS_SDRAM \
  180. | BR_V)
  181. /* 0xF0001861 */
  182. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  183. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  184. /*
  185. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  186. *
  187. * For OR2, need:
  188. * 64MB mask for AM, OR2[0:7] = 1111 1100
  189. * XAM, OR2[17:18] = 11
  190. * 9 columns OR2[19-21] = 010
  191. * 13 rows OR2[23-25] = 100
  192. * EAD set for extra time OR[31] = 1
  193. *
  194. * 0 4 8 12 16 20 24 28
  195. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  196. */
  197. #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
  198. | OR_SDRAM_XAM \
  199. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  200. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  201. | OR_SDRAM_EAD)
  202. /* 0xFC006901 */
  203. /* LB sdram refresh timer, about 6us */
  204. #define CONFIG_SYS_LBC_LSRT 0x32000000
  205. /* LB refresh timer prescal, 266MHz/32 */
  206. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  207. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  208. | LSDMR_BSMA1516 \
  209. | LSDMR_RFCR8 \
  210. | LSDMR_PRETOACT6 \
  211. | LSDMR_ACTTORW3 \
  212. | LSDMR_BL8 \
  213. | LSDMR_WRC3 \
  214. | LSDMR_CL3)
  215. /*
  216. * SDRAM Controller configuration sequence.
  217. */
  218. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  219. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  220. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  221. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  222. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  223. #endif
  224. /*
  225. * Serial Port
  226. */
  227. #define CONFIG_CONS_INDEX 1
  228. #define CONFIG_SYS_NS16550_SERIAL
  229. #define CONFIG_SYS_NS16550_REG_SIZE 1
  230. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  231. #define CONFIG_SYS_BAUDRATE_TABLE \
  232. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  233. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  234. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  235. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  236. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  237. /* I2C */
  238. #define CONFIG_SYS_I2C
  239. #define CONFIG_SYS_I2C_FSL
  240. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  241. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  242. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  243. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  244. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  245. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  246. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
  247. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  248. /* TSEC */
  249. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  250. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  251. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  252. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  253. /*
  254. * General PCI
  255. * Addresses are mapped 1-1.
  256. */
  257. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  258. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  259. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  260. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  261. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  262. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  263. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  264. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  265. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  266. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  267. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  268. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  269. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  270. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  271. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  272. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  273. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  274. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  275. #if defined(CONFIG_PCI)
  276. #define PCI_64BIT
  277. #define PCI_ONE_PCI1
  278. #if defined(PCI_64BIT)
  279. #undef PCI_ALL_PCI1
  280. #undef PCI_TWO_PCI1
  281. #undef PCI_ONE_PCI1
  282. #endif
  283. #undef CONFIG_EEPRO100
  284. #undef CONFIG_TULIP
  285. #if !defined(CONFIG_PCI_PNP)
  286. #define PCI_ENET0_IOADDR 0xFIXME
  287. #define PCI_ENET0_MEMADDR 0xFIXME
  288. #define PCI_IDSEL_NUMBER 0xFIXME
  289. #endif
  290. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  291. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  292. #endif /* CONFIG_PCI */
  293. /*
  294. * TSEC configuration
  295. */
  296. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  297. #if defined(CONFIG_TSEC_ENET)
  298. #define CONFIG_TSEC1 1
  299. #define CONFIG_TSEC1_NAME "TSEC0"
  300. #define CONFIG_TSEC2 1
  301. #define CONFIG_TSEC2_NAME "TSEC1"
  302. #define CONFIG_PHY_BCM5421S 1
  303. #define TSEC1_PHY_ADDR 0x19
  304. #define TSEC2_PHY_ADDR 0x1a
  305. #define TSEC1_PHYIDX 0
  306. #define TSEC2_PHYIDX 0
  307. #define TSEC1_FLAGS TSEC_GIGABIT
  308. #define TSEC2_FLAGS TSEC_GIGABIT
  309. /* Options are: TSEC[0-1] */
  310. #define CONFIG_ETHPRIME "TSEC0"
  311. #endif /* CONFIG_TSEC_ENET */
  312. /*
  313. * Environment
  314. */
  315. #ifndef CONFIG_SYS_RAMBOOT
  316. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  317. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  318. #define CONFIG_ENV_SIZE 0x2000
  319. /* Address and size of Redundant Environment Sector */
  320. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  321. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  322. #else
  323. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  324. #define CONFIG_ENV_SIZE 0x2000
  325. #endif
  326. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  327. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  328. /*
  329. * BOOTP options
  330. */
  331. #define CONFIG_BOOTP_BOOTFILESIZE
  332. #define CONFIG_BOOTP_BOOTPATH
  333. #define CONFIG_BOOTP_GATEWAY
  334. #define CONFIG_BOOTP_HOSTNAME
  335. /*
  336. * Command line configuration.
  337. */
  338. #undef CONFIG_WATCHDOG /* watchdog disabled */
  339. /*
  340. * Miscellaneous configurable options
  341. */
  342. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  343. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  344. /*
  345. * For booting Linux, the board info and command line data
  346. * have to be in the first 256 MB of memory, since this is
  347. * the maximum mapped by the Linux kernel during initialization.
  348. */
  349. /* Initial Memory map for Linux*/
  350. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  351. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  352. #if 1 /*528/264*/
  353. #define CONFIG_SYS_HRCW_LOW (\
  354. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  355. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  356. HRCWL_CSB_TO_CLKIN |\
  357. HRCWL_VCO_1X2 |\
  358. HRCWL_CORE_TO_CSB_2X1)
  359. #elif 0 /*396/132*/
  360. #define CONFIG_SYS_HRCW_LOW (\
  361. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  362. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  363. HRCWL_CSB_TO_CLKIN |\
  364. HRCWL_VCO_1X4 |\
  365. HRCWL_CORE_TO_CSB_3X1)
  366. #elif 0 /*264/132*/
  367. #define CONFIG_SYS_HRCW_LOW (\
  368. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  369. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  370. HRCWL_CSB_TO_CLKIN |\
  371. HRCWL_VCO_1X4 |\
  372. HRCWL_CORE_TO_CSB_2X1)
  373. #elif 0 /*132/132*/
  374. #define CONFIG_SYS_HRCW_LOW (\
  375. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  376. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  377. HRCWL_CSB_TO_CLKIN |\
  378. HRCWL_VCO_1X4 |\
  379. HRCWL_CORE_TO_CSB_1X1)
  380. #elif 0 /*264/264 */
  381. #define CONFIG_SYS_HRCW_LOW (\
  382. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  383. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  384. HRCWL_CSB_TO_CLKIN |\
  385. HRCWL_VCO_1X4 |\
  386. HRCWL_CORE_TO_CSB_1X1)
  387. #endif
  388. #if defined(PCI_64BIT)
  389. #define CONFIG_SYS_HRCW_HIGH (\
  390. HRCWH_PCI_HOST |\
  391. HRCWH_64_BIT_PCI |\
  392. HRCWH_PCI1_ARBITER_ENABLE |\
  393. HRCWH_PCI2_ARBITER_DISABLE |\
  394. HRCWH_CORE_ENABLE |\
  395. HRCWH_FROM_0X00000100 |\
  396. HRCWH_BOOTSEQ_DISABLE |\
  397. HRCWH_SW_WATCHDOG_DISABLE |\
  398. HRCWH_ROM_LOC_LOCAL_16BIT |\
  399. HRCWH_TSEC1M_IN_GMII |\
  400. HRCWH_TSEC2M_IN_GMII)
  401. #else
  402. #define CONFIG_SYS_HRCW_HIGH (\
  403. HRCWH_PCI_HOST |\
  404. HRCWH_32_BIT_PCI |\
  405. HRCWH_PCI1_ARBITER_ENABLE |\
  406. HRCWH_PCI2_ARBITER_ENABLE |\
  407. HRCWH_CORE_ENABLE |\
  408. HRCWH_FROM_0X00000100 |\
  409. HRCWH_BOOTSEQ_DISABLE |\
  410. HRCWH_SW_WATCHDOG_DISABLE |\
  411. HRCWH_ROM_LOC_LOCAL_16BIT |\
  412. HRCWH_TSEC1M_IN_GMII |\
  413. HRCWH_TSEC2M_IN_GMII)
  414. #endif
  415. /* System IO Config */
  416. #define CONFIG_SYS_SICRH 0
  417. #define CONFIG_SYS_SICRL SICRL_LDP_A
  418. #define CONFIG_SYS_HID0_INIT 0x000000000
  419. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  420. | HID0_ENABLE_INSTRUCTION_CACHE)
  421. /* #define CONFIG_SYS_HID0_FINAL (\
  422. HID0_ENABLE_INSTRUCTION_CACHE |\
  423. HID0_ENABLE_M_BIT |\
  424. HID0_ENABLE_ADDRESS_BROADCAST) */
  425. #define CONFIG_SYS_HID2 HID2_HBE
  426. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  427. /* DDR @ 0x00000000 */
  428. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  429. | BATL_PP_RW \
  430. | BATL_MEMCOHERENCE)
  431. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  432. | BATU_BL_256M \
  433. | BATU_VS \
  434. | BATU_VP)
  435. /* PCI @ 0x80000000 */
  436. #ifdef CONFIG_PCI
  437. #define CONFIG_PCI_INDIRECT_BRIDGE
  438. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  439. | BATL_PP_RW \
  440. | BATL_MEMCOHERENCE)
  441. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  442. | BATU_BL_256M \
  443. | BATU_VS \
  444. | BATU_VP)
  445. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  446. | BATL_PP_RW \
  447. | BATL_CACHEINHIBIT \
  448. | BATL_GUARDEDSTORAGE)
  449. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  450. | BATU_BL_256M \
  451. | BATU_VS \
  452. | BATU_VP)
  453. #else
  454. #define CONFIG_SYS_IBAT1L (0)
  455. #define CONFIG_SYS_IBAT1U (0)
  456. #define CONFIG_SYS_IBAT2L (0)
  457. #define CONFIG_SYS_IBAT2U (0)
  458. #endif
  459. #ifdef CONFIG_MPC83XX_PCI2
  460. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  461. | BATL_PP_RW \
  462. | BATL_MEMCOHERENCE)
  463. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  464. | BATU_BL_256M \
  465. | BATU_VS \
  466. | BATU_VP)
  467. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  468. | BATL_PP_RW \
  469. | BATL_CACHEINHIBIT \
  470. | BATL_GUARDEDSTORAGE)
  471. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  472. | BATU_BL_256M \
  473. | BATU_VS \
  474. | BATU_VP)
  475. #else
  476. #define CONFIG_SYS_IBAT3L (0)
  477. #define CONFIG_SYS_IBAT3U (0)
  478. #define CONFIG_SYS_IBAT4L (0)
  479. #define CONFIG_SYS_IBAT4U (0)
  480. #endif
  481. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
  482. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  483. | BATL_PP_RW \
  484. | BATL_CACHEINHIBIT \
  485. | BATL_GUARDEDSTORAGE)
  486. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  487. | BATU_BL_256M \
  488. | BATU_VS \
  489. | BATU_VP)
  490. /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  491. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
  492. | BATL_PP_RW \
  493. | BATL_MEMCOHERENCE \
  494. | BATL_GUARDEDSTORAGE)
  495. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
  496. | BATU_BL_256M \
  497. | BATU_VS \
  498. | BATU_VP)
  499. #define CONFIG_SYS_IBAT7L (0)
  500. #define CONFIG_SYS_IBAT7U (0)
  501. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  502. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  503. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  504. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  505. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  506. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  507. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  508. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  509. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  510. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  511. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  512. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  513. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  514. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  515. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  516. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  517. #if defined(CONFIG_CMD_KGDB)
  518. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  519. #endif
  520. /*
  521. * Environment Configuration
  522. */
  523. #define CONFIG_ENV_OVERWRITE
  524. #if defined(CONFIG_TSEC_ENET)
  525. #define CONFIG_HAS_ETH0
  526. #define CONFIG_HAS_ETH1
  527. #endif
  528. #define CONFIG_HOSTNAME SBC8349
  529. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  530. #define CONFIG_BOOTFILE "uImage"
  531. /* default location for tftp and bootm */
  532. #define CONFIG_LOADADDR 800000
  533. #define CONFIG_EXTRA_ENV_SETTINGS \
  534. "netdev=eth0\0" \
  535. "hostname=sbc8349\0" \
  536. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  537. "nfsroot=${serverip}:${rootpath}\0" \
  538. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  539. "addip=setenv bootargs ${bootargs} " \
  540. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  541. ":${hostname}:${netdev}:off panic=1\0" \
  542. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  543. "flash_nfs=run nfsargs addip addtty;" \
  544. "bootm ${kernel_addr}\0" \
  545. "flash_self=run ramargs addip addtty;" \
  546. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  547. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  548. "bootm\0" \
  549. "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
  550. "update=protect off ff800000 ff83ffff; " \
  551. "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
  552. "upd=run load update\0" \
  553. "fdtaddr=780000\0" \
  554. "fdtfile=sbc8349.dtb\0" \
  555. ""
  556. #define CONFIG_NFSBOOTCOMMAND \
  557. "setenv bootargs root=/dev/nfs rw " \
  558. "nfsroot=$serverip:$rootpath " \
  559. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  560. "$netdev:off " \
  561. "console=$consoledev,$baudrate $othbootargs;" \
  562. "tftp $loadaddr $bootfile;" \
  563. "tftp $fdtaddr $fdtfile;" \
  564. "bootm $loadaddr - $fdtaddr"
  565. #define CONFIG_RAMBOOTCOMMAND \
  566. "setenv bootargs root=/dev/ram rw " \
  567. "console=$consoledev,$baudrate $othbootargs;" \
  568. "tftp $ramdiskaddr $ramdiskfile;" \
  569. "tftp $loadaddr $bootfile;" \
  570. "tftp $fdtaddr $fdtfile;" \
  571. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  572. #define CONFIG_BOOTCOMMAND "run flash_self"
  573. #endif /* __CONFIG_H */