MPC8349EMDS.h 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754
  1. /*
  2. * (C) Copyright 2006-2010
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * mpc8349emds board configuration file
  9. *
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #define CONFIG_E300 1 /* E300 Family */
  17. #define CONFIG_MPC834x 1 /* MPC834x family */
  18. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  19. #define CONFIG_SYS_TEXT_BASE 0xFE000000
  20. #define CONFIG_PCI_66M
  21. #ifdef CONFIG_PCI_66M
  22. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  23. #else
  24. #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
  25. #endif
  26. #ifdef CONFIG_PCISLAVE
  27. #define CONFIG_83XX_PCICLK 66666666 /* in Hz */
  28. #endif /* CONFIG_PCISLAVE */
  29. #ifndef CONFIG_SYS_CLK_FREQ
  30. #ifdef CONFIG_PCI_66M
  31. #define CONFIG_SYS_CLK_FREQ 66000000
  32. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
  33. #else
  34. #define CONFIG_SYS_CLK_FREQ 33000000
  35. #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
  36. #endif
  37. #endif
  38. #define CONFIG_SYS_IMMR 0xE0000000
  39. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  40. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  41. #define CONFIG_SYS_MEMTEST_END 0x00100000
  42. /*
  43. * DDR Setup
  44. */
  45. #define CONFIG_DDR_ECC /* support DDR ECC function */
  46. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  47. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  48. /*
  49. * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  50. * unselect it to use old spd_sdram.c
  51. */
  52. #define CONFIG_SYS_SPD_BUS_NUM 0
  53. #define SPD_EEPROM_ADDRESS1 0x52
  54. #define SPD_EEPROM_ADDRESS2 0x51
  55. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  56. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  57. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  58. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  59. /*
  60. * 32-bit data path mode.
  61. *
  62. * Please note that using this mode for devices with the real density of 64-bit
  63. * effectively reduces the amount of available memory due to the effect of
  64. * wrapping around while translating address to row/columns, for example in the
  65. * 256MB module the upper 128MB get aliased with contents of the lower
  66. * 128MB); normally this define should be used for devices with real 32-bit
  67. * data path.
  68. */
  69. #undef CONFIG_DDR_32BIT
  70. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  71. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  72. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  73. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  74. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  75. #undef CONFIG_DDR_2T_TIMING
  76. /*
  77. * DDRCDR - DDR Control Driver Register
  78. */
  79. #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  80. #if defined(CONFIG_SPD_EEPROM)
  81. /*
  82. * Determine DDR configuration from I2C interface.
  83. */
  84. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  85. #else
  86. /*
  87. * Manually set up DDR parameters
  88. */
  89. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  90. #if defined(CONFIG_DDR_II)
  91. #define CONFIG_SYS_DDRCDR 0x80080001
  92. #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
  93. #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
  94. #define CONFIG_SYS_DDR_TIMING_0 0x00220802
  95. #define CONFIG_SYS_DDR_TIMING_1 0x38357322
  96. #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
  97. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  98. #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
  99. #define CONFIG_SYS_DDR_MODE 0x47d00432
  100. #define CONFIG_SYS_DDR_MODE2 0x8000c000
  101. #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
  102. #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
  103. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  104. #else
  105. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  106. | CSCONFIG_ROW_BIT_13 \
  107. | CSCONFIG_COL_BIT_10)
  108. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  109. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  110. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  111. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  112. #if defined(CONFIG_DDR_32BIT)
  113. /* set burst length to 8 for 32-bit data path */
  114. /* DLL,normal,seq,4/2.5, 8 burst len */
  115. #define CONFIG_SYS_DDR_MODE 0x00000023
  116. #else
  117. /* the default burst length is 4 - for 64-bit data path */
  118. /* DLL,normal,seq,4/2.5, 4 burst len */
  119. #define CONFIG_SYS_DDR_MODE 0x00000022
  120. #endif
  121. #endif
  122. #endif
  123. /*
  124. * SDRAM on the Local Bus
  125. */
  126. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  127. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  128. /*
  129. * FLASH on the Local Bus
  130. */
  131. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  132. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  133. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  134. #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
  135. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  136. /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
  137. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  138. | BR_PS_16 /* 16 bit port */ \
  139. | BR_MS_GPCM /* MSEL = GPCM */ \
  140. | BR_V) /* valid */
  141. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  142. | OR_UPM_XAM \
  143. | OR_GPCM_CSNT \
  144. | OR_GPCM_ACS_DIV2 \
  145. | OR_GPCM_XACS \
  146. | OR_GPCM_SCY_15 \
  147. | OR_GPCM_TRLX_SET \
  148. | OR_GPCM_EHTR_SET \
  149. | OR_GPCM_EAD)
  150. /* window base at flash base */
  151. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  152. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
  153. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  154. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  155. #undef CONFIG_SYS_FLASH_CHECKSUM
  156. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  157. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  158. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  159. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  160. #define CONFIG_SYS_RAMBOOT
  161. #else
  162. #undef CONFIG_SYS_RAMBOOT
  163. #endif
  164. /*
  165. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  166. */
  167. #define CONFIG_SYS_BCSR 0xE2400000
  168. /* Access window base at BCSR base */
  169. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
  170. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  171. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
  172. | BR_PS_8 \
  173. | BR_MS_GPCM \
  174. | BR_V)
  175. /* 0x00000801 */
  176. #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
  177. | OR_GPCM_XAM \
  178. | OR_GPCM_CSNT \
  179. | OR_GPCM_SCY_15 \
  180. | OR_GPCM_TRLX_CLEAR \
  181. | OR_GPCM_EHTR_CLEAR)
  182. /* 0xFFFFE8F0 */
  183. #define CONFIG_SYS_INIT_RAM_LOCK 1
  184. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  185. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  186. #define CONFIG_SYS_GBL_DATA_OFFSET \
  187. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  188. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  189. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  190. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  191. /*
  192. * Local Bus LCRR and LBCR regs
  193. * LCRR: DLL bypass, Clock divider is 4
  194. * External Local Bus rate is
  195. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  196. */
  197. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  198. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
  199. #define CONFIG_SYS_LBC_LBCR 0x00000000
  200. /*
  201. * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  202. * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
  203. */
  204. #undef CONFIG_SYS_LB_SDRAM
  205. #ifdef CONFIG_SYS_LB_SDRAM
  206. /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
  207. /*
  208. * Base Register 2 and Option Register 2 configure SDRAM.
  209. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  210. *
  211. * For BR2, need:
  212. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  213. * port-size = 32-bits = BR2[19:20] = 11
  214. * no parity checking = BR2[21:22] = 00
  215. * SDRAM for MSEL = BR2[24:26] = 011
  216. * Valid = BR[31] = 1
  217. *
  218. * 0 4 8 12 16 20 24 28
  219. * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  220. */
  221. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
  222. | BR_PS_32 /* 32-bit port */ \
  223. | BR_MS_SDRAM /* MSEL = SDRAM */ \
  224. | BR_V) /* Valid */
  225. /* 0xF0001861 */
  226. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
  227. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
  228. /*
  229. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  230. *
  231. * For OR2, need:
  232. * 64MB mask for AM, OR2[0:7] = 1111 1100
  233. * XAM, OR2[17:18] = 11
  234. * 9 columns OR2[19-21] = 010
  235. * 13 rows OR2[23-25] = 100
  236. * EAD set for extra time OR[31] = 1
  237. *
  238. * 0 4 8 12 16 20 24 28
  239. * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  240. */
  241. #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
  242. | OR_SDRAM_XAM \
  243. | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
  244. | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
  245. | OR_SDRAM_EAD)
  246. /* 0xFC006901 */
  247. /* LB sdram refresh timer, about 6us */
  248. #define CONFIG_SYS_LBC_LSRT 0x32000000
  249. /* LB refresh timer prescal, 266MHz/32 */
  250. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  251. #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
  252. | LSDMR_BSMA1516 \
  253. | LSDMR_RFCR8 \
  254. | LSDMR_PRETOACT6 \
  255. | LSDMR_ACTTORW3 \
  256. | LSDMR_BL8 \
  257. | LSDMR_WRC3 \
  258. | LSDMR_CL3)
  259. /*
  260. * SDRAM Controller configuration sequence.
  261. */
  262. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  263. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  264. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  265. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  266. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  267. #endif
  268. /*
  269. * Serial Port
  270. */
  271. #define CONFIG_CONS_INDEX 1
  272. #define CONFIG_SYS_NS16550_SERIAL
  273. #define CONFIG_SYS_NS16550_REG_SIZE 1
  274. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  275. #define CONFIG_SYS_BAUDRATE_TABLE \
  276. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  277. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  278. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  279. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  280. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  281. /* I2C */
  282. #define CONFIG_SYS_I2C
  283. #define CONFIG_SYS_I2C_FSL
  284. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  285. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  286. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  287. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  288. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  289. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  290. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  291. /* SPI */
  292. #define CONFIG_MPC8XXX_SPI
  293. #undef CONFIG_SOFT_SPI /* SPI bit-banged */
  294. /* GPIOs. Used as SPI chip selects */
  295. #define CONFIG_SYS_GPIO1_PRELIM
  296. #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
  297. #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
  298. /* TSEC */
  299. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  300. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  301. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  302. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  303. /* USB */
  304. #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
  305. /*
  306. * General PCI
  307. * Addresses are mapped 1-1.
  308. */
  309. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  310. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  311. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  312. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  313. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  314. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  315. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  316. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  317. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  318. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  319. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  320. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  321. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  322. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  323. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  324. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  325. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  326. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  327. #if defined(CONFIG_PCI)
  328. #define PCI_ONE_PCI1
  329. #if defined(PCI_64BIT)
  330. #undef PCI_ALL_PCI1
  331. #undef PCI_TWO_PCI1
  332. #undef PCI_ONE_PCI1
  333. #endif
  334. #define CONFIG_83XX_PCI_STREAMING
  335. #undef CONFIG_EEPRO100
  336. #undef CONFIG_TULIP
  337. #if !defined(CONFIG_PCI_PNP)
  338. #define PCI_ENET0_IOADDR 0xFIXME
  339. #define PCI_ENET0_MEMADDR 0xFIXME
  340. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  341. #endif
  342. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  343. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  344. #endif /* CONFIG_PCI */
  345. /*
  346. * TSEC configuration
  347. */
  348. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  349. #if defined(CONFIG_TSEC_ENET)
  350. #define CONFIG_GMII 1 /* MII PHY management */
  351. #define CONFIG_TSEC1 1
  352. #define CONFIG_TSEC1_NAME "TSEC0"
  353. #define CONFIG_TSEC2 1
  354. #define CONFIG_TSEC2_NAME "TSEC1"
  355. #define TSEC1_PHY_ADDR 0
  356. #define TSEC2_PHY_ADDR 1
  357. #define TSEC1_PHYIDX 0
  358. #define TSEC2_PHYIDX 0
  359. #define TSEC1_FLAGS TSEC_GIGABIT
  360. #define TSEC2_FLAGS TSEC_GIGABIT
  361. /* Options are: TSEC[0-1] */
  362. #define CONFIG_ETHPRIME "TSEC0"
  363. #endif /* CONFIG_TSEC_ENET */
  364. /*
  365. * Configure on-board RTC
  366. */
  367. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  368. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  369. /*
  370. * Environment
  371. */
  372. #ifndef CONFIG_SYS_RAMBOOT
  373. #define CONFIG_ENV_ADDR \
  374. (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  375. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
  376. #define CONFIG_ENV_SIZE 0x2000
  377. /* Address and size of Redundant Environment Sector */
  378. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  379. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  380. #else
  381. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  382. #define CONFIG_ENV_SIZE 0x2000
  383. #endif
  384. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  385. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  386. /*
  387. * BOOTP options
  388. */
  389. #define CONFIG_BOOTP_BOOTFILESIZE
  390. #define CONFIG_BOOTP_BOOTPATH
  391. #define CONFIG_BOOTP_GATEWAY
  392. #define CONFIG_BOOTP_HOSTNAME
  393. /*
  394. * Command line configuration.
  395. */
  396. #undef CONFIG_WATCHDOG /* watchdog disabled */
  397. /*
  398. * Miscellaneous configurable options
  399. */
  400. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  401. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  402. /*
  403. * For booting Linux, the board info and command line data
  404. * have to be in the first 256 MB of memory, since this is
  405. * the maximum mapped by the Linux kernel during initialization.
  406. */
  407. /* Initial Memory map for Linux*/
  408. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  409. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  410. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  411. #if 1 /*528/264*/
  412. #define CONFIG_SYS_HRCW_LOW (\
  413. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  414. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  415. HRCWL_CSB_TO_CLKIN |\
  416. HRCWL_VCO_1X2 |\
  417. HRCWL_CORE_TO_CSB_2X1)
  418. #elif 0 /*396/132*/
  419. #define CONFIG_SYS_HRCW_LOW (\
  420. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  421. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  422. HRCWL_CSB_TO_CLKIN |\
  423. HRCWL_VCO_1X4 |\
  424. HRCWL_CORE_TO_CSB_3X1)
  425. #elif 0 /*264/132*/
  426. #define CONFIG_SYS_HRCW_LOW (\
  427. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  428. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  429. HRCWL_CSB_TO_CLKIN |\
  430. HRCWL_VCO_1X4 |\
  431. HRCWL_CORE_TO_CSB_2X1)
  432. #elif 0 /*132/132*/
  433. #define CONFIG_SYS_HRCW_LOW (\
  434. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  435. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  436. HRCWL_CSB_TO_CLKIN |\
  437. HRCWL_VCO_1X4 |\
  438. HRCWL_CORE_TO_CSB_1X1)
  439. #elif 0 /*264/264 */
  440. #define CONFIG_SYS_HRCW_LOW (\
  441. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  442. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  443. HRCWL_CSB_TO_CLKIN |\
  444. HRCWL_VCO_1X4 |\
  445. HRCWL_CORE_TO_CSB_1X1)
  446. #endif
  447. #ifdef CONFIG_PCISLAVE
  448. #define CONFIG_SYS_HRCW_HIGH (\
  449. HRCWH_PCI_AGENT |\
  450. HRCWH_64_BIT_PCI |\
  451. HRCWH_PCI1_ARBITER_DISABLE |\
  452. HRCWH_PCI2_ARBITER_DISABLE |\
  453. HRCWH_CORE_ENABLE |\
  454. HRCWH_FROM_0X00000100 |\
  455. HRCWH_BOOTSEQ_DISABLE |\
  456. HRCWH_SW_WATCHDOG_DISABLE |\
  457. HRCWH_ROM_LOC_LOCAL_16BIT |\
  458. HRCWH_TSEC1M_IN_GMII |\
  459. HRCWH_TSEC2M_IN_GMII)
  460. #else
  461. #if defined(PCI_64BIT)
  462. #define CONFIG_SYS_HRCW_HIGH (\
  463. HRCWH_PCI_HOST |\
  464. HRCWH_64_BIT_PCI |\
  465. HRCWH_PCI1_ARBITER_ENABLE |\
  466. HRCWH_PCI2_ARBITER_DISABLE |\
  467. HRCWH_CORE_ENABLE |\
  468. HRCWH_FROM_0X00000100 |\
  469. HRCWH_BOOTSEQ_DISABLE |\
  470. HRCWH_SW_WATCHDOG_DISABLE |\
  471. HRCWH_ROM_LOC_LOCAL_16BIT |\
  472. HRCWH_TSEC1M_IN_GMII |\
  473. HRCWH_TSEC2M_IN_GMII)
  474. #else
  475. #define CONFIG_SYS_HRCW_HIGH (\
  476. HRCWH_PCI_HOST |\
  477. HRCWH_32_BIT_PCI |\
  478. HRCWH_PCI1_ARBITER_ENABLE |\
  479. HRCWH_PCI2_ARBITER_ENABLE |\
  480. HRCWH_CORE_ENABLE |\
  481. HRCWH_FROM_0X00000100 |\
  482. HRCWH_BOOTSEQ_DISABLE |\
  483. HRCWH_SW_WATCHDOG_DISABLE |\
  484. HRCWH_ROM_LOC_LOCAL_16BIT |\
  485. HRCWH_TSEC1M_IN_GMII |\
  486. HRCWH_TSEC2M_IN_GMII)
  487. #endif /* PCI_64BIT */
  488. #endif /* CONFIG_PCISLAVE */
  489. /*
  490. * System performance
  491. */
  492. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  493. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  494. #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
  495. #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
  496. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  497. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  498. /* System IO Config */
  499. #define CONFIG_SYS_SICRH 0
  500. #define CONFIG_SYS_SICRL SICRL_LDP_A
  501. #define CONFIG_SYS_HID0_INIT 0x000000000
  502. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
  503. | HID0_ENABLE_INSTRUCTION_CACHE)
  504. /* #define CONFIG_SYS_HID0_FINAL (\
  505. HID0_ENABLE_INSTRUCTION_CACHE |\
  506. HID0_ENABLE_M_BIT |\
  507. HID0_ENABLE_ADDRESS_BROADCAST) */
  508. #define CONFIG_SYS_HID2 HID2_HBE
  509. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  510. /* DDR @ 0x00000000 */
  511. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
  512. | BATL_PP_RW \
  513. | BATL_MEMCOHERENCE)
  514. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
  515. | BATU_BL_256M \
  516. | BATU_VS \
  517. | BATU_VP)
  518. /* PCI @ 0x80000000 */
  519. #ifdef CONFIG_PCI
  520. #define CONFIG_PCI_INDIRECT_BRIDGE
  521. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
  522. | BATL_PP_RW \
  523. | BATL_MEMCOHERENCE)
  524. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
  525. | BATU_BL_256M \
  526. | BATU_VS \
  527. | BATU_VP)
  528. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
  529. | BATL_PP_RW \
  530. | BATL_CACHEINHIBIT \
  531. | BATL_GUARDEDSTORAGE)
  532. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
  533. | BATU_BL_256M \
  534. | BATU_VS \
  535. | BATU_VP)
  536. #else
  537. #define CONFIG_SYS_IBAT1L (0)
  538. #define CONFIG_SYS_IBAT1U (0)
  539. #define CONFIG_SYS_IBAT2L (0)
  540. #define CONFIG_SYS_IBAT2U (0)
  541. #endif
  542. #ifdef CONFIG_MPC83XX_PCI2
  543. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
  544. | BATL_PP_RW \
  545. | BATL_MEMCOHERENCE)
  546. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
  547. | BATU_BL_256M \
  548. | BATU_VS \
  549. | BATU_VP)
  550. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
  551. | BATL_PP_RW \
  552. | BATL_CACHEINHIBIT \
  553. | BATL_GUARDEDSTORAGE)
  554. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
  555. | BATU_BL_256M \
  556. | BATU_VS \
  557. | BATU_VP)
  558. #else
  559. #define CONFIG_SYS_IBAT3L (0)
  560. #define CONFIG_SYS_IBAT3U (0)
  561. #define CONFIG_SYS_IBAT4L (0)
  562. #define CONFIG_SYS_IBAT4U (0)
  563. #endif
  564. /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
  565. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
  566. | BATL_PP_RW \
  567. | BATL_CACHEINHIBIT \
  568. | BATL_GUARDEDSTORAGE)
  569. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
  570. | BATU_BL_256M \
  571. | BATU_VS \
  572. | BATU_VP)
  573. /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
  574. #define CONFIG_SYS_IBAT6L (0xF0000000 \
  575. | BATL_PP_RW \
  576. | BATL_MEMCOHERENCE \
  577. | BATL_GUARDEDSTORAGE)
  578. #define CONFIG_SYS_IBAT6U (0xF0000000 \
  579. | BATU_BL_256M \
  580. | BATU_VS \
  581. | BATU_VP)
  582. #define CONFIG_SYS_IBAT7L (0)
  583. #define CONFIG_SYS_IBAT7U (0)
  584. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  585. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  586. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  587. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  588. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  589. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  590. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  591. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  592. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  593. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  594. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  595. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  596. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  597. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  598. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  599. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  600. #if defined(CONFIG_CMD_KGDB)
  601. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  602. #endif
  603. /*
  604. * Environment Configuration
  605. */
  606. #define CONFIG_ENV_OVERWRITE
  607. #if defined(CONFIG_TSEC_ENET)
  608. #define CONFIG_HAS_ETH1
  609. #define CONFIG_HAS_ETH0
  610. #endif
  611. #define CONFIG_HOSTNAME mpc8349emds
  612. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  613. #define CONFIG_BOOTFILE "uImage"
  614. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  615. #define CONFIG_PREBOOT "echo;" \
  616. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  617. "echo"
  618. #define CONFIG_EXTRA_ENV_SETTINGS \
  619. "netdev=eth0\0" \
  620. "hostname=mpc8349emds\0" \
  621. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  622. "nfsroot=${serverip}:${rootpath}\0" \
  623. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  624. "addip=setenv bootargs ${bootargs} " \
  625. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  626. ":${hostname}:${netdev}:off panic=1\0" \
  627. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  628. "flash_nfs=run nfsargs addip addtty;" \
  629. "bootm ${kernel_addr}\0" \
  630. "flash_self=run ramargs addip addtty;" \
  631. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  632. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  633. "bootm\0" \
  634. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  635. "update=protect off fe000000 fe03ffff; " \
  636. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
  637. "upd=run load update\0" \
  638. "fdtaddr=780000\0" \
  639. "fdtfile=mpc834x_mds.dtb\0" \
  640. ""
  641. #define CONFIG_NFSBOOTCOMMAND \
  642. "setenv bootargs root=/dev/nfs rw " \
  643. "nfsroot=$serverip:$rootpath " \
  644. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  645. "$netdev:off " \
  646. "console=$consoledev,$baudrate $othbootargs;" \
  647. "tftp $loadaddr $bootfile;" \
  648. "tftp $fdtaddr $fdtfile;" \
  649. "bootm $loadaddr - $fdtaddr"
  650. #define CONFIG_RAMBOOTCOMMAND \
  651. "setenv bootargs root=/dev/ram rw " \
  652. "console=$consoledev,$baudrate $othbootargs;" \
  653. "tftp $ramdiskaddr $ramdiskfile;" \
  654. "tftp $loadaddr $bootfile;" \
  655. "tftp $fdtaddr $fdtfile;" \
  656. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  657. #define CONFIG_BOOTCOMMAND "run flash_self"
  658. #endif /* __CONFIG_H */