MPC8308RDB.h 16 KB

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  1. /*
  2. * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
  3. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  4. *
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. /*
  11. * High Level Configuration Options
  12. */
  13. #define CONFIG_E300 1 /* E300 family */
  14. #define CONFIG_MPC830x 1 /* MPC830x family */
  15. #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
  16. #define CONFIG_SYS_TEXT_BASE 0xFE000000
  17. #define CONFIG_MISC_INIT_R
  18. #ifdef CONFIG_MMC
  19. #define CONFIG_FSL_ESDHC
  20. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
  21. #define CONFIG_SYS_FSL_ESDHC_USE_PIO
  22. #endif
  23. /*
  24. * On-board devices
  25. *
  26. * TSEC1 is SoC TSEC
  27. * TSEC2 is VSC switch
  28. */
  29. #define CONFIG_TSEC1
  30. #define CONFIG_VSC7385_ENET
  31. /*
  32. * System Clock Setup
  33. */
  34. #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
  35. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  36. /*
  37. * Hardware Reset Configuration Word
  38. * if CLKIN is 66.66MHz, then
  39. * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  40. * We choose the A type silicon as default, so the core is 400Mhz.
  41. */
  42. #define CONFIG_SYS_HRCW_LOW (\
  43. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  44. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  45. HRCWL_SVCOD_DIV_2 |\
  46. HRCWL_CSB_TO_CLKIN_4X1 |\
  47. HRCWL_CORE_TO_CSB_3X1)
  48. /*
  49. * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  50. * in 8308's HRCWH according to the manual, but original Freescale's
  51. * code has them and I've expirienced some problems using the board
  52. * with BDI3000 attached when I've tried to set these bits to zero
  53. * (UART doesn't work after the 'reset run' command).
  54. */
  55. #define CONFIG_SYS_HRCW_HIGH (\
  56. HRCWH_PCI_HOST |\
  57. HRCWH_PCI1_ARBITER_ENABLE |\
  58. HRCWH_CORE_ENABLE |\
  59. HRCWH_FROM_0X00000100 |\
  60. HRCWH_BOOTSEQ_DISABLE |\
  61. HRCWH_SW_WATCHDOG_DISABLE |\
  62. HRCWH_ROM_LOC_LOCAL_16BIT |\
  63. HRCWH_RL_EXT_LEGACY |\
  64. HRCWH_TSEC1M_IN_RGMII |\
  65. HRCWH_TSEC2M_IN_RGMII |\
  66. HRCWH_BIG_ENDIAN)
  67. /*
  68. * System IO Config
  69. */
  70. #define CONFIG_SYS_SICRH (\
  71. SICRH_ESDHC_A_SD |\
  72. SICRH_ESDHC_B_SD |\
  73. SICRH_ESDHC_C_SD |\
  74. SICRH_GPIO_A_TSEC2 |\
  75. SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
  76. SICRH_IEEE1588_A_GPIO |\
  77. SICRH_USB |\
  78. SICRH_GTM_GPIO |\
  79. SICRH_IEEE1588_B_GPIO |\
  80. SICRH_ETSEC2_CRS |\
  81. SICRH_GPIOSEL_1 |\
  82. SICRH_TMROBI_V3P3 |\
  83. SICRH_TSOBI1_V2P5 |\
  84. SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
  85. #define CONFIG_SYS_SICRL (\
  86. SICRL_SPI_PF0 |\
  87. SICRL_UART_PF0 |\
  88. SICRL_IRQ_PF0 |\
  89. SICRL_I2C2_PF0 |\
  90. SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
  91. /*
  92. * IMMR new address
  93. */
  94. #define CONFIG_SYS_IMMR 0xE0000000
  95. /*
  96. * SERDES
  97. */
  98. #define CONFIG_FSL_SERDES
  99. #define CONFIG_FSL_SERDES1 0xe3000
  100. /*
  101. * Arbiter Setup
  102. */
  103. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  104. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
  105. #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
  106. /*
  107. * DDR Setup
  108. */
  109. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
  110. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  111. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  112. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  113. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  114. | DDRCDR_PZ_LOZ \
  115. | DDRCDR_NZ_LOZ \
  116. | DDRCDR_ODT \
  117. | DDRCDR_Q_DRN)
  118. /* 0x7b880001 */
  119. /*
  120. * Manually set up DDR parameters
  121. * consist of two chips HY5PS12621BFP-C4 from HYNIX
  122. */
  123. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  124. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  125. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  126. | CSCONFIG_ODT_RD_NEVER \
  127. | CSCONFIG_ODT_WR_ONLY_CURRENT \
  128. | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  129. /* 0x80010102 */
  130. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  131. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  132. | (0 << TIMING_CFG0_WRT_SHIFT) \
  133. | (0 << TIMING_CFG0_RRT_SHIFT) \
  134. | (0 << TIMING_CFG0_WWT_SHIFT) \
  135. | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  136. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  137. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  138. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  139. /* 0x00220802 */
  140. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  141. | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  142. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  143. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  144. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  145. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  146. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  147. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  148. /* 0x27256222 */
  149. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  150. | (4 << TIMING_CFG2_CPO_SHIFT) \
  151. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  152. | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  153. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  154. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  155. | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  156. /* 0x121048c5 */
  157. #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  158. | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  159. /* 0x03600100 */
  160. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
  161. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  162. | SDRAM_CFG_DBW_32)
  163. /* 0x43080000 */
  164. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
  165. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
  166. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  167. /* ODT 150ohm CL=3, AL=1 on SDRAM */
  168. #define CONFIG_SYS_DDR_MODE2 0x00000000
  169. /*
  170. * Memory test
  171. */
  172. #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
  173. #define CONFIG_SYS_MEMTEST_END 0x07f00000
  174. /*
  175. * The reserved memory
  176. */
  177. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  178. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  179. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
  180. /*
  181. * Initial RAM Base Address Setup
  182. */
  183. #define CONFIG_SYS_INIT_RAM_LOCK 1
  184. #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
  185. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
  186. #define CONFIG_SYS_GBL_DATA_OFFSET \
  187. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  188. /*
  189. * Local Bus Configuration & Clock Setup
  190. */
  191. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  192. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  193. #define CONFIG_SYS_LBC_LBCR 0x00040000
  194. /*
  195. * FLASH on the Local Bus
  196. */
  197. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  198. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  199. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  200. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
  201. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
  202. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
  203. /* Window base at flash base */
  204. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  205. #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
  206. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
  207. | BR_PS_16 /* 16 bit port */ \
  208. | BR_MS_GPCM /* MSEL = GPCM */ \
  209. | BR_V) /* valid */
  210. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  211. | OR_UPM_XAM \
  212. | OR_GPCM_CSNT \
  213. | OR_GPCM_ACS_DIV2 \
  214. | OR_GPCM_XACS \
  215. | OR_GPCM_SCY_15 \
  216. | OR_GPCM_TRLX_SET \
  217. | OR_GPCM_EHTR_SET)
  218. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  219. /* 127 64KB sectors and 8 8KB top sectors per device */
  220. #define CONFIG_SYS_MAX_FLASH_SECT 135
  221. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  222. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  223. /*
  224. * NAND Flash on the Local Bus
  225. */
  226. #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
  227. #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
  228. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
  229. | BR_DECC_CHK_GEN /* Use HW ECC */ \
  230. | BR_PS_8 /* 8 bit Port */ \
  231. | BR_MS_FCM /* MSEL = FCM */ \
  232. | BR_V) /* valid */
  233. #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
  234. | OR_FCM_CSCT \
  235. | OR_FCM_CST \
  236. | OR_FCM_CHT \
  237. | OR_FCM_SCY_1 \
  238. | OR_FCM_TRLX \
  239. | OR_FCM_EHTR)
  240. /* 0xFFFF8396 */
  241. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  242. #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
  243. #ifdef CONFIG_VSC7385_ENET
  244. #define CONFIG_TSEC2
  245. /* VSC7385 Base address on CS2 */
  246. #define CONFIG_SYS_VSC7385_BASE 0xF0000000
  247. #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
  248. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
  249. | BR_PS_8 /* 8-bit port */ \
  250. | BR_MS_GPCM /* MSEL = GPCM */ \
  251. | BR_V) /* valid */
  252. /* 0xF0000801 */
  253. #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
  254. | OR_GPCM_CSNT \
  255. | OR_GPCM_XACS \
  256. | OR_GPCM_SCY_15 \
  257. | OR_GPCM_SETA \
  258. | OR_GPCM_TRLX_SET \
  259. | OR_GPCM_EHTR_SET)
  260. /* 0xFFFE09FF */
  261. /* Access window base at VSC7385 base */
  262. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
  263. /* Access window size 128K */
  264. #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
  265. /* The flash address and size of the VSC7385 firmware image */
  266. #define CONFIG_VSC7385_IMAGE 0xFE7FE000
  267. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  268. #endif
  269. /*
  270. * Serial Port
  271. */
  272. #define CONFIG_CONS_INDEX 1
  273. #define CONFIG_SYS_NS16550_SERIAL
  274. #define CONFIG_SYS_NS16550_REG_SIZE 1
  275. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  276. #define CONFIG_SYS_BAUDRATE_TABLE \
  277. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  278. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  279. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  280. /* I2C */
  281. #define CONFIG_SYS_I2C
  282. #define CONFIG_SYS_I2C_FSL
  283. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  284. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  285. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  286. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  287. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  288. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  289. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
  290. /*
  291. * SPI on header J8
  292. *
  293. * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
  294. * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
  295. */
  296. #ifdef CONFIG_MPC8XXX_SPI
  297. #define CONFIG_USE_SPIFLASH
  298. #endif
  299. /*
  300. * Board info - revision and where boot from
  301. */
  302. #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
  303. /*
  304. * Config on-board RTC
  305. */
  306. #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
  307. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  308. /*
  309. * General PCI
  310. * Addresses are mapped 1-1.
  311. */
  312. #define CONFIG_SYS_PCIE1_BASE 0xA0000000
  313. #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
  314. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
  315. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
  316. #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
  317. #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
  318. #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
  319. #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
  320. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
  321. /* enable PCIE clock */
  322. #define CONFIG_SYS_SCCR_PCIEXP1CM 1
  323. #define CONFIG_PCI_INDIRECT_BRIDGE
  324. #define CONFIG_PCIE
  325. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  326. #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
  327. /*
  328. * TSEC
  329. */
  330. #define CONFIG_TSEC_ENET /* TSEC ethernet support */
  331. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  332. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  333. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  334. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  335. /*
  336. * TSEC ethernet configuration
  337. */
  338. #define CONFIG_MII 1 /* MII PHY management */
  339. #define CONFIG_TSEC1_NAME "eTSEC0"
  340. #define CONFIG_TSEC2_NAME "eTSEC1"
  341. #define TSEC1_PHY_ADDR 2
  342. #define TSEC2_PHY_ADDR 1
  343. #define TSEC1_PHYIDX 0
  344. #define TSEC2_PHYIDX 0
  345. #define TSEC1_FLAGS TSEC_GIGABIT
  346. #define TSEC2_FLAGS TSEC_GIGABIT
  347. /* Options are: eTSEC[0-1] */
  348. #define CONFIG_ETHPRIME "eTSEC0"
  349. /*
  350. * Environment
  351. */
  352. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  353. CONFIG_SYS_MONITOR_LEN)
  354. #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
  355. #define CONFIG_ENV_SIZE 0x2000
  356. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  357. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  358. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  359. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  360. /*
  361. * BOOTP options
  362. */
  363. #define CONFIG_BOOTP_BOOTFILESIZE
  364. #define CONFIG_BOOTP_BOOTPATH
  365. #define CONFIG_BOOTP_GATEWAY
  366. #define CONFIG_BOOTP_HOSTNAME
  367. /*
  368. * Command line configuration.
  369. */
  370. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  371. /*
  372. * Miscellaneous configurable options
  373. */
  374. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  375. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  376. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  377. /* Boot Argument Buffer Size */
  378. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  379. /*
  380. * For booting Linux, the board info and command line data
  381. * have to be in the first 256 MB of memory, since this is
  382. * the maximum mapped by the Linux kernel during initialization.
  383. */
  384. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
  385. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  386. /*
  387. * Core HID Setup
  388. */
  389. #define CONFIG_SYS_HID0_INIT 0x000000000
  390. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
  391. HID0_ENABLE_INSTRUCTION_CACHE | \
  392. HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
  393. #define CONFIG_SYS_HID2 HID2_HBE
  394. /*
  395. * MMU Setup
  396. */
  397. /* DDR: cache cacheable */
  398. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
  399. BATL_MEMCOHERENCE)
  400. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
  401. BATU_VS | BATU_VP)
  402. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  403. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  404. /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
  405. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
  406. BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  407. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
  408. BATU_VP)
  409. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  410. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  411. /* FLASH: icache cacheable, but dcache-inhibit and guarded */
  412. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  413. BATL_MEMCOHERENCE)
  414. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
  415. BATU_VS | BATU_VP)
  416. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
  417. BATL_CACHEINHIBIT | \
  418. BATL_GUARDEDSTORAGE)
  419. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  420. /* Stack in dcache: cacheable, no memory coherence */
  421. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
  422. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
  423. BATU_VS | BATU_VP)
  424. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  425. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  426. /*
  427. * Environment Configuration
  428. */
  429. #define CONFIG_ENV_OVERWRITE
  430. #if defined(CONFIG_TSEC_ENET)
  431. #define CONFIG_HAS_ETH0
  432. #define CONFIG_HAS_ETH1
  433. #endif
  434. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  435. #define CONFIG_EXTRA_ENV_SETTINGS \
  436. "netdev=eth0\0" \
  437. "consoledev=ttyS0\0" \
  438. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  439. "nfsroot=${serverip}:${rootpath}\0" \
  440. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  441. "addip=setenv bootargs ${bootargs} " \
  442. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  443. ":${hostname}:${netdev}:off panic=1\0" \
  444. "addtty=setenv bootargs ${bootargs}" \
  445. " console=${consoledev},${baudrate}\0" \
  446. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  447. "addmisc=setenv bootargs ${bootargs}\0" \
  448. "kernel_addr=FE080000\0" \
  449. "fdt_addr=FE280000\0" \
  450. "ramdisk_addr=FE290000\0" \
  451. "u-boot=mpc8308rdb/u-boot.bin\0" \
  452. "kernel_addr_r=1000000\0" \
  453. "fdt_addr_r=C00000\0" \
  454. "hostname=mpc8308rdb\0" \
  455. "bootfile=mpc8308rdb/uImage\0" \
  456. "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
  457. "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
  458. "flash_self=run ramargs addip addtty addmtd addmisc;" \
  459. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  460. "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
  461. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  462. "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
  463. "tftp ${fdt_addr_r} ${fdtfile};" \
  464. "run nfsargs addip addtty addmtd addmisc;" \
  465. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  466. "bootcmd=run flash_self\0" \
  467. "load=tftp ${loadaddr} ${u-boot}\0" \
  468. "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
  469. " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
  470. " +${filesize};cp.b ${fileaddr} " \
  471. __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
  472. "upd=run load update\0" \
  473. #endif /* __CONFIG_H */