cortina.c 8.9 KB

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  1. /*
  2. * Cortina CS4315/CS4340 10G PHY drivers
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Copyright 2014 Freescale Semiconductor, Inc.
  7. *
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <linux/ctype.h>
  13. #include <linux/string.h>
  14. #include <linux/err.h>
  15. #include <phy.h>
  16. #include <cortina.h>
  17. #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
  18. #include <nand.h>
  19. #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
  20. #include <spi_flash.h>
  21. #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
  22. #include <mmc.h>
  23. #endif
  24. #ifndef CONFIG_PHYLIB_10G
  25. #error The Cortina PHY needs 10G support
  26. #endif
  27. struct cortina_reg_config cortina_reg_cfg[] = {
  28. /* CS4315_enable_sr_mode */
  29. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  30. {VILLA_MSEQ_OPTIONS, 0xf},
  31. {VILLA_MSEQ_PC, 0x0},
  32. {VILLA_MSEQ_BANKSELECT, 0x4},
  33. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
  34. {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
  35. {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
  36. {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
  37. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
  38. {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
  39. {VILLA_MSEQ_ENABLE_MSB, 0x0000},
  40. {VILLA_MSEQ_SPARE21_LSB, 0x6},
  41. {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
  42. {VILLA_MSEQ_SPARE12_MSB, 0x0000},
  43. /*
  44. * to invert the receiver path, uncomment the next line
  45. * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
  46. *
  47. * SPARE2_LSB is used to configure the device while in sr mode to
  48. * enable power savings and to use the optical module LOS signal.
  49. * in power savings mode, the internal prbs checker can not be used.
  50. * if the optical module LOS signal is used as an input to the micro
  51. * code, then the micro code will wait until the optical module
  52. * LOS = 0 before turning on the adaptive equalizer.
  53. * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
  54. * while setting bit 0 to 0 disables power savings mode.
  55. * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
  56. * optical module LOS signal while setting bit 2 to 1 configures the
  57. * device so that it will ignore the optical module LOS SPARE2_LSB = 0
  58. */
  59. /* enable power savings, ignore optical module LOS */
  60. {VILLA_MSEQ_SPARE2_LSB, 0x5},
  61. {VILLA_MSEQ_SPARE7_LSB, 0x1e},
  62. {VILLA_MSEQ_BANKSELECT, 0x4},
  63. {VILLA_MSEQ_SPARE9_LSB, 0x2},
  64. {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
  65. {VILLA_MSEQ_SPARE3_MSB, 0x2006},
  66. {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
  67. {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
  68. {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
  69. {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
  70. {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
  71. {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
  72. {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
  73. {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
  74. {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
  75. {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
  76. {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
  77. {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
  78. {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
  79. {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
  80. {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
  81. {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
  82. {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
  83. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  84. {VILLA_MSEQ_OPTIONS, 0x7},
  85. /* set up min value for ffe1 */
  86. {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
  87. {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
  88. /* CS4315_sr_rx_pre_eq_set_4in */
  89. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  90. {VILLA_MSEQ_OPTIONS, 0xf},
  91. {VILLA_MSEQ_BANKSELECT, 0x4},
  92. {VILLA_MSEQ_PC, 0x0},
  93. /* for lengths from 3.5 to 4.5inches */
  94. {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
  95. {VILLA_MSEQ_SPARE25_LSB, 0x0306},
  96. {VILLA_MSEQ_SPARE21_LSB, 0x2},
  97. {VILLA_MSEQ_SPARE23_LSB, 0x2},
  98. {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
  99. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  100. {VILLA_MSEQ_OPTIONS, 0x7},
  101. /* CS4315_rx_drive_4inch */
  102. /* for length 4inches */
  103. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  104. {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  105. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  106. /* CS4315_tx_drive_4inch */
  107. /* for length 4inches */
  108. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  109. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  110. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  111. };
  112. void cs4340_upload_firmware(struct phy_device *phydev)
  113. {
  114. char line_temp[0x50] = {0};
  115. char reg_addr[0x50] = {0};
  116. char reg_data[0x50] = {0};
  117. int i, line_cnt = 0, column_cnt = 0;
  118. struct cortina_reg_config fw_temp;
  119. char *addr = NULL;
  120. #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
  121. defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
  122. addr = (char *)CONFIG_CORTINA_FW_ADDR;
  123. #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
  124. int ret;
  125. size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
  126. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  127. ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
  128. &fw_length, (u_char *)addr);
  129. if (ret == -EUCLEAN) {
  130. printf("NAND read of Cortina firmware at 0x%x failed %d\n",
  131. CONFIG_CORTINA_FW_ADDR, ret);
  132. }
  133. #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
  134. int ret;
  135. struct spi_flash *ucode_flash;
  136. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  137. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  138. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  139. if (!ucode_flash) {
  140. puts("SF: probe for Cortina ucode failed\n");
  141. } else {
  142. ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
  143. CONFIG_CORTINA_FW_LENGTH, addr);
  144. if (ret)
  145. puts("SF: read for Cortina ucode failed\n");
  146. spi_flash_free(ucode_flash);
  147. }
  148. #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
  149. int dev = CONFIG_SYS_MMC_ENV_DEV;
  150. u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
  151. u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
  152. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  153. if (!mmc) {
  154. puts("Failed to find MMC device for Cortina ucode\n");
  155. } else {
  156. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  157. printf("MMC read: dev # %u, block # %u, count %u ...\n",
  158. dev, blk, cnt);
  159. mmc_init(mmc);
  160. (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
  161. addr);
  162. /* flush cache after read */
  163. flush_cache((ulong)addr, cnt * 512);
  164. }
  165. #endif
  166. while (*addr != 'Q') {
  167. i = 0;
  168. while (*addr != 0x0a) {
  169. line_temp[i++] = *addr++;
  170. if (0x50 < i) {
  171. printf("Not found Cortina PHY ucode at 0x%p\n",
  172. (char *)CONFIG_CORTINA_FW_ADDR);
  173. return;
  174. }
  175. }
  176. addr++; /* skip '\n' */
  177. line_cnt++;
  178. column_cnt = i;
  179. line_temp[column_cnt] = '\0';
  180. if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
  181. return;
  182. for (i = 0; i < column_cnt; i++) {
  183. if (isspace(line_temp[i++]))
  184. break;
  185. }
  186. memcpy(reg_addr, line_temp, i);
  187. memcpy(reg_data, &line_temp[i], column_cnt - i);
  188. strim(reg_addr);
  189. strim(reg_data);
  190. fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
  191. fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
  192. 0xffff;
  193. phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
  194. }
  195. }
  196. int cs4340_phy_init(struct phy_device *phydev)
  197. {
  198. int timeout = 100; /* 100ms */
  199. int reg_value;
  200. /* step1: BIST test */
  201. phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
  202. phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
  203. phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
  204. while (--timeout) {
  205. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
  206. if (reg_value & mseq_edc_bist_done) {
  207. if (0 == (reg_value & mseq_edc_bist_fail))
  208. break;
  209. }
  210. udelay(1000);
  211. }
  212. if (!timeout) {
  213. printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
  214. return -1;
  215. }
  216. /* setp2: upload ucode */
  217. cs4340_upload_firmware(phydev);
  218. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
  219. if (reg_value) {
  220. debug("%s checksum status failed.\n", __func__);
  221. return -1;
  222. }
  223. return 0;
  224. }
  225. int cs4340_config(struct phy_device *phydev)
  226. {
  227. cs4340_phy_init(phydev);
  228. return 0;
  229. }
  230. int cs4340_startup(struct phy_device *phydev)
  231. {
  232. phydev->link = 1;
  233. /* For now just lie and say it's 10G all the time */
  234. phydev->speed = SPEED_10000;
  235. phydev->duplex = DUPLEX_FULL;
  236. return 0;
  237. }
  238. struct phy_driver cs4340_driver = {
  239. .name = "Cortina CS4315/CS4340",
  240. .uid = PHY_UID_CS4340,
  241. .mask = 0xfffffff0,
  242. .features = PHY_10G_FEATURES,
  243. .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
  244. MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
  245. MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
  246. .config = &cs4340_config,
  247. .startup = &cs4340_startup,
  248. .shutdown = &gen10g_shutdown,
  249. };
  250. int phy_cortina_init(void)
  251. {
  252. phy_register(&cs4340_driver);
  253. return 0;
  254. }
  255. int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
  256. {
  257. int phy_reg;
  258. bool is_cortina_phy = false;
  259. switch (addr) {
  260. #ifdef CORTINA_PHY_ADDR1
  261. case CORTINA_PHY_ADDR1:
  262. #endif
  263. #ifdef CORTINA_PHY_ADDR2
  264. case CORTINA_PHY_ADDR2:
  265. #endif
  266. #ifdef CORTINA_PHY_ADDR3
  267. case CORTINA_PHY_ADDR3:
  268. #endif
  269. #ifdef CORTINA_PHY_ADDR4
  270. case CORTINA_PHY_ADDR4:
  271. #endif
  272. is_cortina_phy = true;
  273. break;
  274. default:
  275. break;
  276. }
  277. /* Cortina PHY has non-standard offset of PHY ID registers */
  278. if (is_cortina_phy)
  279. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
  280. else
  281. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  282. if (phy_reg < 0)
  283. return -EIO;
  284. *phy_id = (phy_reg & 0xffff) << 16;
  285. if (is_cortina_phy)
  286. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
  287. else
  288. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  289. if (phy_reg < 0)
  290. return -EIO;
  291. *phy_id |= (phy_reg & 0xffff);
  292. return 0;
  293. }