fm.c 12 KB

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  1. /*
  2. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  3. * Dave Liu <daveliu@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <malloc.h>
  9. #include <asm/io.h>
  10. #include <asm/errno.h>
  11. #include "fm.h"
  12. #include "../../qe/qe.h" /* For struct qe_firmware */
  13. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  14. #include <nand.h>
  15. #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
  16. #include <spi_flash.h>
  17. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
  18. #include <mmc.h>
  19. #endif
  20. struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
  21. void *fm_muram_base(int fm_idx)
  22. {
  23. return muram[fm_idx].base;
  24. }
  25. void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
  26. {
  27. void *ret;
  28. ulong align_mask;
  29. size_t off;
  30. void *save;
  31. align_mask = align - 1;
  32. save = muram[fm_idx].alloc;
  33. off = (ulong)save & align_mask;
  34. if (off != 0)
  35. muram[fm_idx].alloc += (align - off);
  36. off = size & align_mask;
  37. if (off != 0)
  38. size += (align - off);
  39. if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
  40. muram[fm_idx].alloc = save;
  41. printf("%s: run out of ram.\n", __func__);
  42. return NULL;
  43. }
  44. ret = muram[fm_idx].alloc;
  45. muram[fm_idx].alloc += size;
  46. memset((void *)ret, 0, size);
  47. return ret;
  48. }
  49. static void fm_init_muram(int fm_idx, void *reg)
  50. {
  51. void *base = reg;
  52. muram[fm_idx].base = base;
  53. muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
  54. muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
  55. muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
  56. }
  57. /*
  58. * fm_upload_ucode - Fman microcode upload worker function
  59. *
  60. * This function does the actual uploading of an Fman microcode
  61. * to an Fman.
  62. */
  63. static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
  64. u32 *ucode, unsigned int size)
  65. {
  66. unsigned int i;
  67. unsigned int timeout = 1000000;
  68. /* enable address auto increase */
  69. out_be32(&imem->iadd, IRAM_IADD_AIE);
  70. /* write microcode to IRAM */
  71. for (i = 0; i < size / 4; i++)
  72. out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
  73. /* verify if the writing is over */
  74. out_be32(&imem->iadd, 0);
  75. while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
  76. ;
  77. if (!timeout)
  78. printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
  79. /* enable microcode from IRAM */
  80. out_be32(&imem->iready, IRAM_READY);
  81. }
  82. /*
  83. * Upload an Fman firmware
  84. *
  85. * This function is similar to qe_upload_firmware(), exception that it uploads
  86. * a microcode to the Fman instead of the QE.
  87. *
  88. * Because the process for uploading a microcode to the Fman is similar for
  89. * that of the QE, the QE firmware binary format is used for Fman microcode.
  90. * It should be possible to unify these two functions, but for now we keep them
  91. * separate.
  92. */
  93. static int fman_upload_firmware(int fm_idx,
  94. struct fm_imem *fm_imem,
  95. const struct qe_firmware *firmware)
  96. {
  97. unsigned int i;
  98. u32 crc;
  99. size_t calc_size = sizeof(struct qe_firmware);
  100. size_t length;
  101. const struct qe_header *hdr;
  102. if (!firmware) {
  103. printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
  104. return -EINVAL;
  105. }
  106. hdr = &firmware->header;
  107. length = be32_to_cpu(hdr->length);
  108. /* Check the magic */
  109. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  110. (hdr->magic[2] != 'F')) {
  111. printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
  112. firmware);
  113. return -EPERM;
  114. }
  115. /* Check the version */
  116. if (hdr->version != 1) {
  117. printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
  118. hdr->version);
  119. return -EPERM;
  120. }
  121. /* Validate some of the fields */
  122. if ((firmware->count != 1)) {
  123. printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
  124. return -EINVAL;
  125. }
  126. /* Validate the length and check if there's a CRC */
  127. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  128. for (i = 0; i < firmware->count; i++)
  129. /*
  130. * For situations where the second RISC uses the same microcode
  131. * as the first, the 'code_offset' and 'count' fields will be
  132. * zero, so it's okay to add those.
  133. */
  134. calc_size += sizeof(u32) *
  135. be32_to_cpu(firmware->microcode[i].count);
  136. /* Validate the length */
  137. if (length != calc_size + sizeof(u32)) {
  138. printf("Fman%u: Invalid length in firmware header\n",
  139. fm_idx + 1);
  140. return -EPERM;
  141. }
  142. /*
  143. * Validate the CRC. We would normally call crc32_no_comp(), but that
  144. * function isn't available unless you turn on JFFS support.
  145. */
  146. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  147. if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
  148. printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
  149. return -EIO;
  150. }
  151. /* Loop through each microcode. */
  152. for (i = 0; i < firmware->count; i++) {
  153. const struct qe_microcode *ucode = &firmware->microcode[i];
  154. /* Upload a microcode if it's present */
  155. if (be32_to_cpu(ucode->code_offset)) {
  156. u32 ucode_size;
  157. u32 *code;
  158. printf("Fman%u: Uploading microcode version %u.%u.%u\n",
  159. fm_idx + 1, ucode->major, ucode->minor,
  160. ucode->revision);
  161. code = (void *)firmware +
  162. be32_to_cpu(ucode->code_offset);
  163. ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
  164. fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
  165. }
  166. }
  167. return 0;
  168. }
  169. static u32 fm_assign_risc(int port_id)
  170. {
  171. u32 risc_sel, val;
  172. risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
  173. val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
  174. val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
  175. return val;
  176. }
  177. static void fm_init_fpm(struct fm_fpm *fpm)
  178. {
  179. int i, port_id;
  180. u32 val;
  181. setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
  182. FMFPEE_CER | FMFPEE_DER);
  183. /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
  184. /* offline/parser port */
  185. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  186. port_id = OH_PORT_ID_BASE + i;
  187. val = fm_assign_risc(port_id);
  188. out_be32(&fpm->fpmprc, val);
  189. }
  190. /* Rx 1G port */
  191. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  192. port_id = RX_PORT_1G_BASE + i;
  193. val = fm_assign_risc(port_id);
  194. out_be32(&fpm->fpmprc, val);
  195. }
  196. /* Tx 1G port */
  197. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  198. port_id = TX_PORT_1G_BASE + i;
  199. val = fm_assign_risc(port_id);
  200. out_be32(&fpm->fpmprc, val);
  201. }
  202. /* Rx 10G port */
  203. port_id = RX_PORT_10G_BASE;
  204. val = fm_assign_risc(port_id);
  205. out_be32(&fpm->fpmprc, val);
  206. /* Tx 10G port */
  207. port_id = TX_PORT_10G_BASE;
  208. val = fm_assign_risc(port_id);
  209. out_be32(&fpm->fpmprc, val);
  210. /* disable the dispatch limit in IM case */
  211. out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
  212. /* clear events */
  213. out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
  214. /* clear risc events */
  215. for (i = 0; i < 4; i++)
  216. out_be32(&fpm->fpmcev[i], 0xffffffff);
  217. /* clear error */
  218. out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
  219. }
  220. static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
  221. {
  222. int blk, i, port_id;
  223. u32 val;
  224. size_t offset;
  225. void *base;
  226. /* alloc free buffer pool in MURAM */
  227. base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
  228. if (!base) {
  229. printf("%s: no muram for free buffer pool\n", __func__);
  230. return -ENOMEM;
  231. }
  232. offset = base - fm_muram_base(fm_idx);
  233. /* Need 128KB total free buffer pool size */
  234. val = offset / 256;
  235. blk = FM_FREE_POOL_SIZE / 256;
  236. /* in IM, we must not begin from offset 0 in MURAM */
  237. val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
  238. out_be32(&bmi->fmbm_cfg1, val);
  239. /* disable all BMI interrupt */
  240. out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
  241. /* clear all events */
  242. out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
  243. /*
  244. * set port parameters - FMBM_PP_x
  245. * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
  246. * max dma 10G Rx/Tx=3, others is 1
  247. * set port FIFO size - FMBM_PFS_x
  248. * 4KB for all Rx and Tx ports
  249. */
  250. /* offline/parser port */
  251. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  252. port_id = OH_PORT_ID_BASE + i - 1;
  253. /* max tasks=1, max dma=1, no extra */
  254. out_be32(&bmi->fmbm_pp[port_id], 0);
  255. /* port FIFO size - 256 bytes, no extra */
  256. out_be32(&bmi->fmbm_pfs[port_id], 0);
  257. }
  258. /* Rx 1G port */
  259. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  260. port_id = RX_PORT_1G_BASE + i - 1;
  261. /* max tasks=4, max dma=1, no extra */
  262. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  263. /* FIFO size - 4KB, no extra */
  264. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  265. }
  266. /* Tx 1G port FIFO size - 4KB, no extra */
  267. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  268. port_id = TX_PORT_1G_BASE + i - 1;
  269. /* max tasks=4, max dma=1, no extra */
  270. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  271. /* FIFO size - 4KB, no extra */
  272. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  273. }
  274. /* Rx 10G port */
  275. port_id = RX_PORT_10G_BASE - 1;
  276. /* max tasks=12, max dma=3, no extra */
  277. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  278. /* FIFO size - 4KB, no extra */
  279. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  280. /* Tx 10G port */
  281. port_id = TX_PORT_10G_BASE - 1;
  282. /* max tasks=12, max dma=3, no extra */
  283. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  284. /* FIFO size - 4KB, no extra */
  285. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  286. /* initialize internal buffers data base (linked list) */
  287. out_be32(&bmi->fmbm_init, FMBM_INIT_START);
  288. return 0;
  289. }
  290. static void fm_init_qmi(struct fm_qmi_common *qmi)
  291. {
  292. /* disable enqueue and dequeue of QMI */
  293. clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN);
  294. /* disable all error interrupts */
  295. out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
  296. /* clear all error events */
  297. out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
  298. /* disable all interrupts */
  299. out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
  300. /* clear all interrupts */
  301. out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
  302. }
  303. /* Init common part of FM, index is fm num# like fm as above */
  304. int fm_init_common(int index, struct ccsr_fman *reg)
  305. {
  306. int rc;
  307. #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
  308. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  309. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
  310. size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
  311. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  312. rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  313. &fw_length, (u_char *)addr);
  314. if (rc == -EUCLEAN) {
  315. printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
  316. CONFIG_SYS_FMAN_FW_ADDR, rc);
  317. }
  318. #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
  319. struct spi_flash *ucode_flash;
  320. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  321. int ret = 0;
  322. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  323. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  324. if (!ucode_flash)
  325. printf("SF: probe for ucode failed\n");
  326. else {
  327. ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
  328. CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
  329. if (ret)
  330. printf("SF: read for ucode failed\n");
  331. spi_flash_free(ucode_flash);
  332. }
  333. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
  334. int dev = CONFIG_SYS_MMC_ENV_DEV;
  335. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  336. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  337. u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
  338. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  339. if (!mmc)
  340. printf("\nMMC cannot find device for ucode\n");
  341. else {
  342. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  343. dev, blk, cnt);
  344. mmc_init(mmc);
  345. (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
  346. addr);
  347. /* flush cache after read */
  348. flush_cache((ulong)addr, cnt * 512);
  349. }
  350. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
  351. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  352. #else
  353. void *addr = NULL;
  354. #endif
  355. /* Upload the Fman microcode if it's present */
  356. rc = fman_upload_firmware(index, &reg->fm_imem, addr);
  357. if (rc)
  358. return rc;
  359. setenv_addr("fman_ucode", addr);
  360. fm_init_muram(index, &reg->muram);
  361. fm_init_qmi(&reg->fm_qmi_common);
  362. fm_init_fpm(&reg->fm_fpm);
  363. /* clear DMA status */
  364. setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
  365. /* set DMA mode */
  366. setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
  367. return fm_init_bmi(index, &reg->fm_bmi_common);
  368. }