systemace.c 6.1 KB

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  1. /*
  2. * Copyright (c) 2004 Picture Elements, Inc.
  3. * Stephen Williams (XXXXXXXXXXXXXXXX)
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * The Xilinx SystemACE chip support is activated by defining
  9. * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
  10. * to set the base address of the device. This code currently
  11. * assumes that the chip is connected via a byte-wide bus.
  12. *
  13. * The CONFIG_SYSTEMACE also adds to fat support the device class
  14. * "ace" that allows the user to execute "fatls ace 0" and the
  15. * like. This works by making the systemace_get_dev function
  16. * available to cmd_fat.c:get_dev and filling in a block device
  17. * description that has all the bits needed for FAT support to
  18. * read sectors.
  19. *
  20. * According to Xilinx technical support, before accessing the
  21. * SystemACE CF you need to set the following control bits:
  22. * FORCECFGMODE : 1
  23. * CFGMODE : 0
  24. * CFGSTART : 0
  25. */
  26. #include <common.h>
  27. #include <command.h>
  28. #include <systemace.h>
  29. #include <part.h>
  30. #include <asm/io.h>
  31. /*
  32. * The ace_readw and writew functions read/write 16bit words, but the
  33. * offset value is the BYTE offset as most used in the Xilinx
  34. * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
  35. * to be the base address for the chip, usually in the local
  36. * peripheral bus.
  37. */
  38. static u32 base = CONFIG_SYS_SYSTEMACE_BASE;
  39. static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH;
  40. static void ace_writew(u16 val, unsigned off)
  41. {
  42. if (width == 8) {
  43. #if !defined(__BIG_ENDIAN)
  44. writeb(val >> 8, base + off);
  45. writeb(val, base + off + 1);
  46. #else
  47. writeb(val, base + off);
  48. writeb(val >> 8, base + off + 1);
  49. #endif
  50. } else
  51. out16(base + off, val);
  52. }
  53. static u16 ace_readw(unsigned off)
  54. {
  55. if (width == 8) {
  56. #if !defined(__BIG_ENDIAN)
  57. return (readb(base + off) << 8) | readb(base + off + 1);
  58. #else
  59. return readb(base + off) | (readb(base + off + 1) << 8);
  60. #endif
  61. }
  62. return in16(base + off);
  63. }
  64. static unsigned long systemace_read(block_dev_desc_t *block_dev,
  65. unsigned long start, lbaint_t blkcnt,
  66. void *buffer);
  67. static block_dev_desc_t systemace_dev = { 0 };
  68. static int get_cf_lock(void)
  69. {
  70. int retry = 10;
  71. /* CONTROLREG = LOCKREG */
  72. unsigned val = ace_readw(0x18);
  73. val |= 0x0002;
  74. ace_writew((val & 0xffff), 0x18);
  75. /* Wait for MPULOCK in STATUSREG[15:0] */
  76. while (!(ace_readw(0x04) & 0x0002)) {
  77. if (retry < 0)
  78. return -1;
  79. udelay(100000);
  80. retry -= 1;
  81. }
  82. return 0;
  83. }
  84. static void release_cf_lock(void)
  85. {
  86. unsigned val = ace_readw(0x18);
  87. val &= ~(0x0002);
  88. ace_writew((val & 0xffff), 0x18);
  89. }
  90. #ifdef CONFIG_PARTITIONS
  91. block_dev_desc_t *systemace_get_dev(int dev)
  92. {
  93. /* The first time through this, the systemace_dev object is
  94. not yet initialized. In that case, fill it in. */
  95. if (systemace_dev.blksz == 0) {
  96. systemace_dev.if_type = IF_TYPE_UNKNOWN;
  97. systemace_dev.dev = 0;
  98. systemace_dev.part_type = PART_TYPE_UNKNOWN;
  99. systemace_dev.type = DEV_TYPE_HARDDISK;
  100. systemace_dev.blksz = 512;
  101. systemace_dev.log2blksz = LOG2(systemace_dev.blksz);
  102. systemace_dev.removable = 1;
  103. systemace_dev.block_read = systemace_read;
  104. /*
  105. * Ensure the correct bus mode (8/16 bits) gets enabled
  106. */
  107. ace_writew(width == 8 ? 0 : 0x0001, 0);
  108. init_part(&systemace_dev);
  109. }
  110. return &systemace_dev;
  111. }
  112. #endif
  113. /*
  114. * This function is called (by dereferencing the block_read pointer in
  115. * the dev_desc) to read blocks of data. The return value is the
  116. * number of blocks read. A zero return indicates an error.
  117. */
  118. static unsigned long systemace_read(block_dev_desc_t *block_dev,
  119. unsigned long start, lbaint_t blkcnt,
  120. void *buffer)
  121. {
  122. int retry;
  123. unsigned blk_countdown;
  124. unsigned char *dp = buffer;
  125. unsigned val;
  126. if (get_cf_lock() < 0) {
  127. unsigned status = ace_readw(0x04);
  128. /* If CFDETECT is false, card is missing. */
  129. if (!(status & 0x0010)) {
  130. printf("** CompactFlash card not present. **\n");
  131. return 0;
  132. }
  133. printf("**** ACE locked away from me (STATUSREG=%04x)\n",
  134. status);
  135. return 0;
  136. }
  137. #ifdef DEBUG_SYSTEMACE
  138. printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
  139. #endif
  140. retry = 2000;
  141. for (;;) {
  142. val = ace_readw(0x04);
  143. /* If CFDETECT is false, card is missing. */
  144. if (!(val & 0x0010)) {
  145. printf("**** ACE CompactFlash not found.\n");
  146. release_cf_lock();
  147. return 0;
  148. }
  149. /* If RDYFORCMD, then we are ready to go. */
  150. if (val & 0x0100)
  151. break;
  152. if (retry < 0) {
  153. printf("**** SystemACE not ready.\n");
  154. release_cf_lock();
  155. return 0;
  156. }
  157. udelay(1000);
  158. retry -= 1;
  159. }
  160. /* The SystemACE can only transfer 256 sectors at a time, so
  161. limit the current chunk of sectors. The blk_countdown
  162. variable is the number of sectors left to transfer. */
  163. blk_countdown = blkcnt;
  164. while (blk_countdown > 0) {
  165. unsigned trans = blk_countdown;
  166. if (trans > 256)
  167. trans = 256;
  168. #ifdef DEBUG_SYSTEMACE
  169. printf("... transfer %lu sector in a chunk\n", trans);
  170. #endif
  171. /* Write LBA block address */
  172. ace_writew((start >> 0) & 0xffff, 0x10);
  173. ace_writew((start >> 16) & 0x0fff, 0x12);
  174. /* NOTE: in the Write Sector count below, a count of 0
  175. causes a transfer of 256, so &0xff gives the right
  176. value for whatever transfer count we want. */
  177. /* Write sector count | ReadMemCardData. */
  178. ace_writew((trans & 0xff) | 0x0300, 0x14);
  179. /*
  180. * For FPGA configuration via SystemACE is reset unacceptable
  181. * CFGDONE bit in STATUSREG is not set to 1.
  182. */
  183. #ifndef SYSTEMACE_CONFIG_FPGA
  184. /* Reset the configruation controller */
  185. val = ace_readw(0x18);
  186. val |= 0x0080;
  187. ace_writew(val, 0x18);
  188. #endif
  189. retry = trans * 16;
  190. while (retry > 0) {
  191. int idx;
  192. /* Wait for buffer to become ready. */
  193. while (!(ace_readw(0x04) & 0x0020)) {
  194. udelay(100);
  195. }
  196. /* Read 16 words of 2bytes from the sector buffer. */
  197. for (idx = 0; idx < 16; idx += 1) {
  198. unsigned short val = ace_readw(0x40);
  199. *dp++ = val & 0xff;
  200. *dp++ = (val >> 8) & 0xff;
  201. }
  202. retry -= 1;
  203. }
  204. /* Clear the configruation controller reset */
  205. val = ace_readw(0x18);
  206. val &= ~0x0080;
  207. ace_writew(val, 0x18);
  208. /* Count the blocks we transfer this time. */
  209. start += trans;
  210. blk_countdown -= trans;
  211. }
  212. release_cf_lock();
  213. return blkcnt;
  214. }