km-mpc8360.h 2.0 KB

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  1. /* KMBEC FPGA (PRIO) */
  2. #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
  3. #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
  4. /*
  5. * High Level Configuration Options
  6. */
  7. /*
  8. * System IO Setup
  9. */
  10. #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
  11. /**
  12. * DDR RAM settings
  13. */
  14. #define CONFIG_SYS_DDR_SDRAM_CFG (\
  15. SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  16. SDRAM_CFG_SREN | \
  17. SDRAM_CFG_HSE)
  18. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  19. #define CONFIG_SYS_DDR_CLK_CNTL (\
  20. DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  21. #define CONFIG_SYS_DDR_INTERVAL (\
  22. (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  23. (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
  24. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
  25. #define CONFIG_SYS_DDRCDR (\
  26. DDRCDR_EN | \
  27. DDRCDR_Q_DRN)
  28. #define CONFIG_SYS_DDR_MODE 0x47860452
  29. #define CONFIG_SYS_DDR_MODE2 0x8080c000
  30. #define CONFIG_SYS_DDR_TIMING_0 (\
  31. (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  32. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  33. (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  34. (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  35. (0 << TIMING_CFG0_WWT_SHIFT) | \
  36. (0 << TIMING_CFG0_RRT_SHIFT) | \
  37. (0 << TIMING_CFG0_WRT_SHIFT) | \
  38. (0 << TIMING_CFG0_RWT_SHIFT))
  39. #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
  40. (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  41. (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  42. (3 << TIMING_CFG1_WRREC_SHIFT) | \
  43. (7 << TIMING_CFG1_REFREC_SHIFT) | \
  44. (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  45. (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  46. (3 << TIMING_CFG1_PRETOACT_SHIFT))
  47. #define CONFIG_SYS_DDR_TIMING_2 (\
  48. (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  49. (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  50. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  51. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  52. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  53. (5 << TIMING_CFG2_CPO_SHIFT) | \
  54. (0 << TIMING_CFG2_ADD_LAT_SHIFT))
  55. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  56. /* EEprom support */
  57. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  58. /*
  59. * PAXE on the local bus CS3
  60. */
  61. #define CONFIG_SYS_PAXE_BASE 0xA0000000
  62. #define CONFIG_SYS_PAXE_SIZE 256