km-mpc832x.h 2.2 KB

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  1. /*
  2. * High Level Configuration Options
  3. */
  4. #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
  5. /*
  6. * System Clock Setup
  7. */
  8. #define CONFIG_83XX_CLKIN 66000000
  9. #define CONFIG_SYS_CLK_FREQ 66000000
  10. #define CONFIG_83XX_PCICLK 66000000
  11. /*
  12. * System IO Config
  13. */
  14. #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
  15. #define CONFIG_SYS_DDRCDR (\
  16. DDRCDR_EN | \
  17. DDRCDR_PZ_MAXZ | \
  18. DDRCDR_NZ_MAXZ | \
  19. DDRCDR_M_ODR)
  20. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
  21. #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  22. SDRAM_CFG_32_BE | \
  23. SDRAM_CFG_SREN | \
  24. SDRAM_CFG_HSE)
  25. #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
  26. #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  27. #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  28. (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  29. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
  30. CSCONFIG_ODT_WR_CFG | \
  31. CSCONFIG_ROW_BIT_13 | \
  32. CSCONFIG_COL_BIT_10)
  33. #define CONFIG_SYS_DDR_MODE 0x47860242
  34. #define CONFIG_SYS_DDR_MODE2 0x8080c000
  35. #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  36. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  37. (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  38. (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  39. (0 << TIMING_CFG0_WWT_SHIFT) | \
  40. (0 << TIMING_CFG0_RRT_SHIFT) | \
  41. (0 << TIMING_CFG0_WRT_SHIFT) | \
  42. (0 << TIMING_CFG0_RWT_SHIFT))
  43. #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
  44. (2 << TIMING_CFG1_WRTORD_SHIFT) | \
  45. (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  46. (3 << TIMING_CFG1_WRREC_SHIFT) | \
  47. (7 << TIMING_CFG1_REFREC_SHIFT) | \
  48. (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
  49. (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  50. (3 << TIMING_CFG1_PRETOACT_SHIFT))
  51. #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
  52. (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  53. (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  54. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  55. (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  56. (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
  57. (5 << TIMING_CFG2_CPO_SHIFT))
  58. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  59. #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
  60. #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
  61. /* EEprom support */
  62. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1