km83xx.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * Copyright (C) 2007 Logic Product Development, Inc.
  7. * Peter Barada <peterb@logicpd.com>
  8. *
  9. * Copyright (C) 2007 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * (C) Copyright 2008 - 2010
  13. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14. */
  15. #include <common.h>
  16. #include <env.h>
  17. #include <fdt_support.h>
  18. #include <init.h>
  19. #include <ioports.h>
  20. #include <log.h>
  21. #include <mpc83xx.h>
  22. #include <i2c.h>
  23. #include <miiphy.h>
  24. #include <asm/io.h>
  25. #include <asm/mmu.h>
  26. #include <asm/processor.h>
  27. #include <pci.h>
  28. #include <linux/delay.h>
  29. #include <linux/libfdt.h>
  30. #include <post.h>
  31. #include "../common/common.h"
  32. DECLARE_GLOBAL_DATA_PTR;
  33. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  34. static int piggy_present(void)
  35. {
  36. struct km_bec_fpga __iomem *base =
  37. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  38. return in_8(&base->bprth) & PIGGY_PRESENT;
  39. }
  40. int ethernet_present(void)
  41. {
  42. return piggy_present();
  43. }
  44. int board_early_init_r(void)
  45. {
  46. struct km_bec_fpga *base =
  47. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  48. #if defined(CONFIG_ARCH_MPC8360)
  49. unsigned short svid;
  50. /*
  51. * Because of errata in the UCCs, we have to write to the reserved
  52. * registers to slow the clocks down.
  53. */
  54. svid = SVR_REV(mfspr(SVR));
  55. switch (svid) {
  56. case 0x0020:
  57. /*
  58. * MPC8360ECE.pdf QE_ENET10 table 4:
  59. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  60. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  61. */
  62. setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
  63. break;
  64. case 0x0021:
  65. /*
  66. * MPC8360ECE.pdf QE_ENET10 table 4:
  67. * IMMR + 0x14AC[24:27] = 1010
  68. */
  69. clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
  70. 0x00000050, 0x000000a0);
  71. break;
  72. }
  73. #endif
  74. /* enable the PHY on the PIGGY */
  75. setbits_8(&base->pgy_eth, 0x01);
  76. /* enable the Unit LED (green) */
  77. setbits_8(&base->oprth, WRL_BOOT);
  78. /* enable Application Buffer */
  79. setbits_8(&base->oprtl, OPRTL_XBUFENA);
  80. return 0;
  81. }
  82. int misc_init_r(void)
  83. {
  84. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  85. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  86. return 0;
  87. }
  88. int last_stage_init(void)
  89. {
  90. #if defined(CONFIG_TARGET_KMCOGE5NE)
  91. struct bfticu_iomap *base =
  92. (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
  93. u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
  94. if (dip_switch != 0) {
  95. /* start bootloader */
  96. puts("DIP: Enabled\n");
  97. env_set("actual_bank", "0");
  98. }
  99. #endif
  100. set_km_env();
  101. return 0;
  102. }
  103. static int fixed_sdram(void)
  104. {
  105. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  106. u32 msize = 0;
  107. u32 ddr_size;
  108. u32 ddr_size_log2;
  109. out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
  110. out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
  111. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  112. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  113. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  114. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  115. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  116. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  117. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  118. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  119. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  120. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  121. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  122. udelay(200);
  123. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  124. msize = CONFIG_SYS_DDR_SIZE << 20;
  125. disable_addr_trans();
  126. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  127. enable_addr_trans();
  128. msize /= (1024 * 1024);
  129. if (CONFIG_SYS_DDR_SIZE != msize) {
  130. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  131. (ddr_size > 1);
  132. ddr_size = ddr_size >> 1, ddr_size_log2++)
  133. if (ddr_size & 1)
  134. return -1;
  135. out_be32(&im->sysconf.ddrlaw[0].ar,
  136. (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
  137. out_be32(&im->ddr.csbnds[0].csbnds,
  138. (((msize / 16) - 1) & 0xff));
  139. }
  140. return msize;
  141. }
  142. int dram_init(void)
  143. {
  144. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  145. u32 msize = 0;
  146. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  147. return -ENXIO;
  148. out_be32(&im->sysconf.ddrlaw[0].bar,
  149. CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
  150. msize = fixed_sdram();
  151. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  152. /*
  153. * Initialize DDR ECC byte
  154. */
  155. ddr_enable_ecc(msize * 1024 * 1024);
  156. #endif
  157. /* return total bus SDRAM size(bytes) -- DDR */
  158. gd->ram_size = msize * 1024 * 1024;
  159. return 0;
  160. }
  161. int checkboard(void)
  162. {
  163. puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
  164. if (piggy_present())
  165. puts(" with PIGGY.");
  166. puts("\n");
  167. return 0;
  168. }
  169. int ft_board_setup(void *blob, struct bd_info *bd)
  170. {
  171. ft_cpu_setup(blob, bd);
  172. return 0;
  173. }
  174. #if defined(CONFIG_HUSH_INIT_VAR)
  175. int hush_init_var(void)
  176. {
  177. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  178. return 0;
  179. }
  180. #endif
  181. #if defined(CONFIG_POST)
  182. int post_hotkeys_pressed(void)
  183. {
  184. int testpin = 0;
  185. struct km_bec_fpga *base =
  186. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  187. int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
  188. testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
  189. debug("post_hotkeys_pressed: %d\n", !testpin);
  190. return testpin;
  191. }
  192. ulong post_word_load(void)
  193. {
  194. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  195. debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
  196. return in_le32(addr);
  197. }
  198. void post_word_store(ulong value)
  199. {
  200. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  201. debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
  202. out_le32(addr, value);
  203. }
  204. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  205. {
  206. /*
  207. * These match CONFIG_SYS_MEMTEST_START and
  208. * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
  209. */
  210. *vstart = 0x00100000;
  211. *size = 0xe00000;
  212. debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
  213. return 0;
  214. }
  215. #endif