init.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/io.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/mach-imx/boot_mode.h>
  10. #include <asm/arch/crm_regs.h>
  11. void init_aips(void)
  12. {
  13. struct aipstz_regs *aips1, *aips2, *aips3;
  14. aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  15. aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  16. aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
  17. /*
  18. * Set all MPROTx to be non-bufferable, trusted for R/W,
  19. * not forced to user-mode.
  20. */
  21. writel(0x77777777, &aips1->mprot0);
  22. writel(0x77777777, &aips1->mprot1);
  23. writel(0x77777777, &aips2->mprot0);
  24. writel(0x77777777, &aips2->mprot1);
  25. /*
  26. * Set all OPACRx to be non-bufferable, not require
  27. * supervisor privilege level for access,allow for
  28. * write access and untrusted master access.
  29. */
  30. writel(0x00000000, &aips1->opacr0);
  31. writel(0x00000000, &aips1->opacr1);
  32. writel(0x00000000, &aips1->opacr2);
  33. writel(0x00000000, &aips1->opacr3);
  34. writel(0x00000000, &aips1->opacr4);
  35. writel(0x00000000, &aips2->opacr0);
  36. writel(0x00000000, &aips2->opacr1);
  37. writel(0x00000000, &aips2->opacr2);
  38. writel(0x00000000, &aips2->opacr3);
  39. writel(0x00000000, &aips2->opacr4);
  40. if (is_mx6ull() || is_mx6sx() || is_mx7()) {
  41. /*
  42. * Set all MPROTx to be non-bufferable, trusted for R/W,
  43. * not forced to user-mode.
  44. */
  45. writel(0x77777777, &aips3->mprot0);
  46. writel(0x77777777, &aips3->mprot1);
  47. /*
  48. * Set all OPACRx to be non-bufferable, not require
  49. * supervisor privilege level for access,allow for
  50. * write access and untrusted master access.
  51. */
  52. writel(0x00000000, &aips3->opacr0);
  53. writel(0x00000000, &aips3->opacr1);
  54. writel(0x00000000, &aips3->opacr2);
  55. writel(0x00000000, &aips3->opacr3);
  56. writel(0x00000000, &aips3->opacr4);
  57. }
  58. }
  59. void imx_wdog_disable_powerdown(void)
  60. {
  61. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  62. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  63. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  64. #ifdef CONFIG_MX7D
  65. struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
  66. #endif
  67. /* Write to the PDE (Power Down Enable) bit */
  68. writew(0, &wdog1->wmcr);
  69. writew(0, &wdog2->wmcr);
  70. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
  71. writew(0, &wdog3->wmcr);
  72. #ifdef CONFIG_MX7D
  73. writew(0, &wdog4->wmcr);
  74. #endif
  75. }
  76. #define SRC_SCR_WARM_RESET_ENABLE 0
  77. void init_src(void)
  78. {
  79. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  80. u32 val;
  81. /*
  82. * force warm reset sources to generate cold reset
  83. * for a more reliable restart
  84. */
  85. val = readl(&src_regs->scr);
  86. val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
  87. writel(val, &src_regs->scr);
  88. }
  89. #ifdef CONFIG_CMD_BMODE
  90. void boot_mode_apply(unsigned cfg_val)
  91. {
  92. #ifdef CONFIG_MX6
  93. const u32 persist_sec = IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT;
  94. const u32 bmode = IMX6_SRC_GPR10_BMODE;
  95. #elif CONFIG_MX7
  96. const u32 persist_sec = IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT;
  97. const u32 bmode = IMX7_SRC_GPR10_BMODE;
  98. #endif
  99. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  100. unsigned reg;
  101. if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
  102. clrbits_le32(&psrc->gpr10, persist_sec);
  103. else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
  104. setbits_le32(&psrc->gpr10, persist_sec);
  105. else {
  106. writel(cfg_val, &psrc->gpr9);
  107. reg = readl(&psrc->gpr10);
  108. if (cfg_val)
  109. reg |= bmode;
  110. else
  111. reg &= ~bmode;
  112. writel(reg, &psrc->gpr10);
  113. }
  114. }
  115. #endif
  116. #if defined(CONFIG_MX6)
  117. u32 imx6_src_get_boot_mode(void)
  118. {
  119. if (readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE)
  120. return readl(&src_base->gpr9);
  121. else
  122. return readl(&src_base->sbmr1);
  123. }
  124. #endif