dw_mmc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. * Rajeshawari Shinde <rajeshwari.s@samsung.com>
  6. */
  7. #include <bouncebuf.h>
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <mmc.h>
  13. #include <dwmmc.h>
  14. #include <wait_bit.h>
  15. #define PAGE_SIZE 4096
  16. static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  17. {
  18. unsigned long timeout = 1000;
  19. u32 ctrl;
  20. dwmci_writel(host, DWMCI_CTRL, value);
  21. while (timeout--) {
  22. ctrl = dwmci_readl(host, DWMCI_CTRL);
  23. if (!(ctrl & DWMCI_RESET_ALL))
  24. return 1;
  25. }
  26. return 0;
  27. }
  28. static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  29. u32 desc0, u32 desc1, u32 desc2)
  30. {
  31. struct dwmci_idmac *desc = idmac;
  32. desc->flags = desc0;
  33. desc->cnt = desc1;
  34. desc->addr = desc2;
  35. desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  36. }
  37. static void dwmci_prepare_data(struct dwmci_host *host,
  38. struct mmc_data *data,
  39. struct dwmci_idmac *cur_idmac,
  40. void *bounce_buffer)
  41. {
  42. unsigned long ctrl;
  43. unsigned int i = 0, flags, cnt, blk_cnt;
  44. ulong data_start, data_end;
  45. blk_cnt = data->blocks;
  46. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  47. /* Clear IDMAC interrupt */
  48. dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
  49. data_start = (ulong)cur_idmac;
  50. dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  51. do {
  52. flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  53. flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  54. if (blk_cnt <= 8) {
  55. flags |= DWMCI_IDMAC_LD;
  56. cnt = data->blocksize * blk_cnt;
  57. } else
  58. cnt = data->blocksize * 8;
  59. dwmci_set_idma_desc(cur_idmac, flags, cnt,
  60. (ulong)bounce_buffer + (i * PAGE_SIZE));
  61. if (blk_cnt <= 8)
  62. break;
  63. blk_cnt -= 8;
  64. cur_idmac++;
  65. i++;
  66. } while(1);
  67. data_end = (ulong)cur_idmac;
  68. flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
  69. ctrl = dwmci_readl(host, DWMCI_CTRL);
  70. ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  71. dwmci_writel(host, DWMCI_CTRL, ctrl);
  72. ctrl = dwmci_readl(host, DWMCI_BMOD);
  73. ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  74. dwmci_writel(host, DWMCI_BMOD, ctrl);
  75. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  76. dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  77. }
  78. static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
  79. {
  80. u32 timeout = 20000;
  81. *len = dwmci_readl(host, DWMCI_STATUS);
  82. while (--timeout && (*len & bit)) {
  83. udelay(200);
  84. *len = dwmci_readl(host, DWMCI_STATUS);
  85. }
  86. if (!timeout) {
  87. debug("%s: FIFO underflow timeout\n", __func__);
  88. return -ETIMEDOUT;
  89. }
  90. return 0;
  91. }
  92. static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
  93. {
  94. int ret = 0;
  95. u32 timeout = 240000;
  96. u32 mask, size, i, len = 0;
  97. u32 *buf = NULL;
  98. ulong start = get_timer(0);
  99. u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
  100. RX_WMARK_SHIFT) + 1) * 2;
  101. size = data->blocksize * data->blocks / 4;
  102. if (data->flags == MMC_DATA_READ)
  103. buf = (unsigned int *)data->dest;
  104. else
  105. buf = (unsigned int *)data->src;
  106. for (;;) {
  107. mask = dwmci_readl(host, DWMCI_RINTSTS);
  108. /* Error during data transfer. */
  109. if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
  110. debug("%s: DATA ERROR!\n", __func__);
  111. ret = -EINVAL;
  112. break;
  113. }
  114. if (host->fifo_mode && size) {
  115. len = 0;
  116. if (data->flags == MMC_DATA_READ &&
  117. (mask & DWMCI_INTMSK_RXDR)) {
  118. while (size) {
  119. ret = dwmci_fifo_ready(host,
  120. DWMCI_FIFO_EMPTY,
  121. &len);
  122. if (ret < 0)
  123. break;
  124. len = (len >> DWMCI_FIFO_SHIFT) &
  125. DWMCI_FIFO_MASK;
  126. len = min(size, len);
  127. for (i = 0; i < len; i++)
  128. *buf++ =
  129. dwmci_readl(host, DWMCI_DATA);
  130. size = size > len ? (size - len) : 0;
  131. }
  132. dwmci_writel(host, DWMCI_RINTSTS,
  133. DWMCI_INTMSK_RXDR);
  134. } else if (data->flags == MMC_DATA_WRITE &&
  135. (mask & DWMCI_INTMSK_TXDR)) {
  136. while (size) {
  137. ret = dwmci_fifo_ready(host,
  138. DWMCI_FIFO_FULL,
  139. &len);
  140. if (ret < 0)
  141. break;
  142. len = fifo_depth - ((len >>
  143. DWMCI_FIFO_SHIFT) &
  144. DWMCI_FIFO_MASK);
  145. len = min(size, len);
  146. for (i = 0; i < len; i++)
  147. dwmci_writel(host, DWMCI_DATA,
  148. *buf++);
  149. size = size > len ? (size - len) : 0;
  150. }
  151. dwmci_writel(host, DWMCI_RINTSTS,
  152. DWMCI_INTMSK_TXDR);
  153. }
  154. }
  155. /* Data arrived correctly. */
  156. if (mask & DWMCI_INTMSK_DTO) {
  157. ret = 0;
  158. break;
  159. }
  160. /* Check for timeout. */
  161. if (get_timer(start) > timeout) {
  162. debug("%s: Timeout waiting for data!\n",
  163. __func__);
  164. ret = -ETIMEDOUT;
  165. break;
  166. }
  167. }
  168. dwmci_writel(host, DWMCI_RINTSTS, mask);
  169. return ret;
  170. }
  171. static int dwmci_set_transfer_mode(struct dwmci_host *host,
  172. struct mmc_data *data)
  173. {
  174. unsigned long mode;
  175. mode = DWMCI_CMD_DATA_EXP;
  176. if (data->flags & MMC_DATA_WRITE)
  177. mode |= DWMCI_CMD_RW;
  178. return mode;
  179. }
  180. #ifdef CONFIG_DM_MMC
  181. static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  182. struct mmc_data *data)
  183. {
  184. struct mmc *mmc = mmc_get_mmc_dev(dev);
  185. #else
  186. static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  187. struct mmc_data *data)
  188. {
  189. #endif
  190. struct dwmci_host *host = mmc->priv;
  191. ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
  192. data ? DIV_ROUND_UP(data->blocks, 8) : 0);
  193. int ret = 0, flags = 0, i;
  194. unsigned int timeout = 500;
  195. u32 retry = 100000;
  196. u32 mask, ctrl;
  197. ulong start = get_timer(0);
  198. struct bounce_buffer bbstate;
  199. while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
  200. if (get_timer(start) > timeout) {
  201. debug("%s: Timeout on data busy\n", __func__);
  202. return -ETIMEDOUT;
  203. }
  204. }
  205. dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
  206. if (data) {
  207. if (host->fifo_mode) {
  208. dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  209. dwmci_writel(host, DWMCI_BYTCNT,
  210. data->blocksize * data->blocks);
  211. dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  212. } else {
  213. if (data->flags == MMC_DATA_READ) {
  214. bounce_buffer_start(&bbstate, (void*)data->dest,
  215. data->blocksize *
  216. data->blocks, GEN_BB_WRITE);
  217. } else {
  218. bounce_buffer_start(&bbstate, (void*)data->src,
  219. data->blocksize *
  220. data->blocks, GEN_BB_READ);
  221. }
  222. dwmci_prepare_data(host, data, cur_idmac,
  223. bbstate.bounce_buffer);
  224. }
  225. }
  226. dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
  227. if (data)
  228. flags = dwmci_set_transfer_mode(host, data);
  229. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
  230. return -1;
  231. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  232. flags |= DWMCI_CMD_ABORT_STOP;
  233. else
  234. flags |= DWMCI_CMD_PRV_DAT_WAIT;
  235. if (cmd->resp_type & MMC_RSP_PRESENT) {
  236. flags |= DWMCI_CMD_RESP_EXP;
  237. if (cmd->resp_type & MMC_RSP_136)
  238. flags |= DWMCI_CMD_RESP_LENGTH;
  239. }
  240. if (cmd->resp_type & MMC_RSP_CRC)
  241. flags |= DWMCI_CMD_CHECK_CRC;
  242. flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
  243. debug("Sending CMD%d\n",cmd->cmdidx);
  244. dwmci_writel(host, DWMCI_CMD, flags);
  245. for (i = 0; i < retry; i++) {
  246. mask = dwmci_readl(host, DWMCI_RINTSTS);
  247. if (mask & DWMCI_INTMSK_CDONE) {
  248. if (!data)
  249. dwmci_writel(host, DWMCI_RINTSTS, mask);
  250. break;
  251. }
  252. }
  253. if (i == retry) {
  254. debug("%s: Timeout.\n", __func__);
  255. return -ETIMEDOUT;
  256. }
  257. if (mask & DWMCI_INTMSK_RTO) {
  258. /*
  259. * Timeout here is not necessarily fatal. (e)MMC cards
  260. * will splat here when they receive CMD55 as they do
  261. * not support this command and that is exactly the way
  262. * to tell them apart from SD cards. Thus, this output
  263. * below shall be debug(). eMMC cards also do not favor
  264. * CMD8, please keep that in mind.
  265. */
  266. debug("%s: Response Timeout.\n", __func__);
  267. return -ETIMEDOUT;
  268. } else if (mask & DWMCI_INTMSK_RE) {
  269. debug("%s: Response Error.\n", __func__);
  270. return -EIO;
  271. } else if ((cmd->resp_type & MMC_RSP_CRC) &&
  272. (mask & DWMCI_INTMSK_RCRC)) {
  273. debug("%s: Response CRC Error.\n", __func__);
  274. return -EIO;
  275. }
  276. if (cmd->resp_type & MMC_RSP_PRESENT) {
  277. if (cmd->resp_type & MMC_RSP_136) {
  278. cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
  279. cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
  280. cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
  281. cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
  282. } else {
  283. cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
  284. }
  285. }
  286. if (data) {
  287. ret = dwmci_data_transfer(host, data);
  288. /* only dma mode need it */
  289. if (!host->fifo_mode) {
  290. if (data->flags == MMC_DATA_READ)
  291. mask = DWMCI_IDINTEN_RI;
  292. else
  293. mask = DWMCI_IDINTEN_TI;
  294. ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
  295. mask, true, 1000, false);
  296. if (ret)
  297. debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
  298. __func__, mask);
  299. /* clear interrupts */
  300. dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
  301. ctrl = dwmci_readl(host, DWMCI_CTRL);
  302. ctrl &= ~(DWMCI_DMA_EN);
  303. dwmci_writel(host, DWMCI_CTRL, ctrl);
  304. bounce_buffer_stop(&bbstate);
  305. }
  306. }
  307. udelay(100);
  308. return ret;
  309. }
  310. static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
  311. {
  312. u32 div, status;
  313. int timeout = 10000;
  314. unsigned long sclk;
  315. if ((freq == host->clock) || (freq == 0))
  316. return 0;
  317. /*
  318. * If host->get_mmc_clk isn't defined,
  319. * then assume that host->bus_hz is source clock value.
  320. * host->bus_hz should be set by user.
  321. */
  322. if (host->get_mmc_clk)
  323. sclk = host->get_mmc_clk(host, freq);
  324. else if (host->bus_hz)
  325. sclk = host->bus_hz;
  326. else {
  327. debug("%s: Didn't get source clock value.\n", __func__);
  328. return -EINVAL;
  329. }
  330. if (sclk == freq)
  331. div = 0; /* bypass mode */
  332. else
  333. div = DIV_ROUND_UP(sclk, 2 * freq);
  334. dwmci_writel(host, DWMCI_CLKENA, 0);
  335. dwmci_writel(host, DWMCI_CLKSRC, 0);
  336. dwmci_writel(host, DWMCI_CLKDIV, div);
  337. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  338. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  339. do {
  340. status = dwmci_readl(host, DWMCI_CMD);
  341. if (timeout-- < 0) {
  342. debug("%s: Timeout!\n", __func__);
  343. return -ETIMEDOUT;
  344. }
  345. } while (status & DWMCI_CMD_START);
  346. dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
  347. DWMCI_CLKEN_LOW_PWR);
  348. dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
  349. DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
  350. timeout = 10000;
  351. do {
  352. status = dwmci_readl(host, DWMCI_CMD);
  353. if (timeout-- < 0) {
  354. debug("%s: Timeout!\n", __func__);
  355. return -ETIMEDOUT;
  356. }
  357. } while (status & DWMCI_CMD_START);
  358. host->clock = freq;
  359. return 0;
  360. }
  361. #ifdef CONFIG_DM_MMC
  362. static int dwmci_set_ios(struct udevice *dev)
  363. {
  364. struct mmc *mmc = mmc_get_mmc_dev(dev);
  365. #else
  366. static int dwmci_set_ios(struct mmc *mmc)
  367. {
  368. #endif
  369. struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
  370. u32 ctype, regs;
  371. debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
  372. dwmci_setup_bus(host, mmc->clock);
  373. switch (mmc->bus_width) {
  374. case 8:
  375. ctype = DWMCI_CTYPE_8BIT;
  376. break;
  377. case 4:
  378. ctype = DWMCI_CTYPE_4BIT;
  379. break;
  380. default:
  381. ctype = DWMCI_CTYPE_1BIT;
  382. break;
  383. }
  384. dwmci_writel(host, DWMCI_CTYPE, ctype);
  385. regs = dwmci_readl(host, DWMCI_UHS_REG);
  386. if (mmc->ddr_mode)
  387. regs |= DWMCI_DDR_MODE;
  388. else
  389. regs &= ~DWMCI_DDR_MODE;
  390. dwmci_writel(host, DWMCI_UHS_REG, regs);
  391. if (host->clksel)
  392. host->clksel(host);
  393. return 0;
  394. }
  395. static int dwmci_init(struct mmc *mmc)
  396. {
  397. struct dwmci_host *host = mmc->priv;
  398. if (host->board_init)
  399. host->board_init(host);
  400. dwmci_writel(host, DWMCI_PWREN, 1);
  401. if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
  402. debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
  403. return -EIO;
  404. }
  405. /* Enumerate at 400KHz */
  406. dwmci_setup_bus(host, mmc->cfg->f_min);
  407. dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
  408. dwmci_writel(host, DWMCI_INTMASK, 0);
  409. dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
  410. dwmci_writel(host, DWMCI_IDINTEN, 0);
  411. dwmci_writel(host, DWMCI_BMOD, 1);
  412. if (!host->fifoth_val) {
  413. uint32_t fifo_size;
  414. fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
  415. fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
  416. host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
  417. TX_WMARK(fifo_size / 2);
  418. }
  419. dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
  420. dwmci_writel(host, DWMCI_CLKENA, 0);
  421. dwmci_writel(host, DWMCI_CLKSRC, 0);
  422. if (!host->fifo_mode)
  423. dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
  424. return 0;
  425. }
  426. #ifdef CONFIG_DM_MMC
  427. int dwmci_probe(struct udevice *dev)
  428. {
  429. struct mmc *mmc = mmc_get_mmc_dev(dev);
  430. return dwmci_init(mmc);
  431. }
  432. const struct dm_mmc_ops dm_dwmci_ops = {
  433. .send_cmd = dwmci_send_cmd,
  434. .set_ios = dwmci_set_ios,
  435. };
  436. #else
  437. static const struct mmc_ops dwmci_ops = {
  438. .send_cmd = dwmci_send_cmd,
  439. .set_ios = dwmci_set_ios,
  440. .init = dwmci_init,
  441. };
  442. #endif
  443. void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
  444. u32 max_clk, u32 min_clk)
  445. {
  446. cfg->name = host->name;
  447. #ifndef CONFIG_DM_MMC
  448. cfg->ops = &dwmci_ops;
  449. #endif
  450. cfg->f_min = min_clk;
  451. cfg->f_max = max_clk;
  452. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  453. cfg->host_caps = host->caps;
  454. if (host->buswidth == 8) {
  455. cfg->host_caps |= MMC_MODE_8BIT;
  456. cfg->host_caps &= ~MMC_MODE_4BIT;
  457. } else {
  458. cfg->host_caps |= MMC_MODE_4BIT;
  459. cfg->host_caps &= ~MMC_MODE_8BIT;
  460. }
  461. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  462. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  463. }
  464. #ifdef CONFIG_BLK
  465. int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  466. {
  467. return mmc_bind(dev, mmc, cfg);
  468. }
  469. #else
  470. int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
  471. {
  472. dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
  473. host->mmc = mmc_create(&host->cfg, host);
  474. if (host->mmc == NULL)
  475. return -1;
  476. return 0;
  477. }
  478. #endif