clk-gate2.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
  7. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * Gated clock implementation
  14. *
  15. */
  16. #include <common.h>
  17. #include <asm/io.h>
  18. #include <malloc.h>
  19. #include <clk-uclass.h>
  20. #include <dm/device.h>
  21. #include <dm/devres.h>
  22. #include <linux/clk-provider.h>
  23. #include <clk.h>
  24. #include "clk.h"
  25. #include <linux/err.h>
  26. #define UBOOT_DM_CLK_IMX_GATE2 "imx_clk_gate2"
  27. struct clk_gate2 {
  28. struct clk clk;
  29. void __iomem *reg;
  30. u8 bit_idx;
  31. u8 cgr_val;
  32. u8 flags;
  33. };
  34. #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  35. static int clk_gate2_enable(struct clk *clk)
  36. {
  37. struct clk_gate2 *gate = to_clk_gate2(clk);
  38. u32 reg;
  39. reg = readl(gate->reg);
  40. reg &= ~(3 << gate->bit_idx);
  41. reg |= gate->cgr_val << gate->bit_idx;
  42. writel(reg, gate->reg);
  43. return 0;
  44. }
  45. static int clk_gate2_disable(struct clk *clk)
  46. {
  47. struct clk_gate2 *gate = to_clk_gate2(clk);
  48. u32 reg;
  49. reg = readl(gate->reg);
  50. reg &= ~(3 << gate->bit_idx);
  51. writel(reg, gate->reg);
  52. return 0;
  53. }
  54. static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
  55. {
  56. struct clk *parent = clk_get_parent(clk);
  57. if (parent)
  58. return clk_set_rate(parent, rate);
  59. return -ENODEV;
  60. }
  61. static const struct clk_ops clk_gate2_ops = {
  62. .set_rate = clk_gate2_set_rate,
  63. .enable = clk_gate2_enable,
  64. .disable = clk_gate2_disable,
  65. .get_rate = clk_generic_get_rate,
  66. };
  67. struct clk *clk_register_gate2(struct device *dev, const char *name,
  68. const char *parent_name, unsigned long flags,
  69. void __iomem *reg, u8 bit_idx, u8 cgr_val,
  70. u8 clk_gate2_flags)
  71. {
  72. struct clk_gate2 *gate;
  73. struct clk *clk;
  74. int ret;
  75. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  76. if (!gate)
  77. return ERR_PTR(-ENOMEM);
  78. gate->reg = reg;
  79. gate->bit_idx = bit_idx;
  80. gate->cgr_val = cgr_val;
  81. gate->flags = clk_gate2_flags;
  82. clk = &gate->clk;
  83. ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
  84. if (ret) {
  85. kfree(gate);
  86. return ERR_PTR(ret);
  87. }
  88. return clk;
  89. }
  90. U_BOOT_DRIVER(clk_gate2) = {
  91. .name = UBOOT_DM_CLK_IMX_GATE2,
  92. .id = UCLASS_CLK,
  93. .ops = &clk_gate2_ops,
  94. .flags = DM_FLAG_PRE_RELOC,
  95. };