clk-composite.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <malloc.h>
  9. #include <clk-uclass.h>
  10. #include <dm/device.h>
  11. #include <dm/devres.h>
  12. #include <linux/clk-provider.h>
  13. #include <clk.h>
  14. #include <linux/err.h>
  15. #include "clk.h"
  16. #define UBOOT_DM_CLK_COMPOSITE "clk_composite"
  17. static u8 clk_composite_get_parent(struct clk *clk)
  18. {
  19. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  20. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  21. struct clk *mux = composite->mux;
  22. return clk_mux_get_parent(mux);
  23. }
  24. static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
  25. {
  26. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  27. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  28. const struct clk_ops *mux_ops = composite->mux_ops;
  29. struct clk *mux = composite->mux;
  30. return mux_ops->set_parent(mux, parent);
  31. }
  32. static unsigned long clk_composite_recalc_rate(struct clk *clk)
  33. {
  34. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  35. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  36. const struct clk_ops *rate_ops = composite->rate_ops;
  37. struct clk *rate = composite->rate;
  38. return rate_ops->get_rate(rate);
  39. }
  40. static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
  41. {
  42. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  43. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  44. const struct clk_ops *rate_ops = composite->rate_ops;
  45. struct clk *clk_rate = composite->rate;
  46. return rate_ops->set_rate(clk_rate, rate);
  47. }
  48. static int clk_composite_enable(struct clk *clk)
  49. {
  50. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  51. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  52. const struct clk_ops *gate_ops = composite->gate_ops;
  53. struct clk *gate = composite->gate;
  54. return gate_ops->enable(gate);
  55. }
  56. static int clk_composite_disable(struct clk *clk)
  57. {
  58. struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
  59. (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
  60. const struct clk_ops *gate_ops = composite->gate_ops;
  61. struct clk *gate = composite->gate;
  62. gate_ops->disable(gate);
  63. return 0;
  64. }
  65. struct clk_ops clk_composite_ops = {
  66. /* This will be set according to clk_register_composite */
  67. };
  68. struct clk *clk_register_composite(struct device *dev, const char *name,
  69. const char * const *parent_names,
  70. int num_parents, struct clk *mux,
  71. const struct clk_ops *mux_ops,
  72. struct clk *rate,
  73. const struct clk_ops *rate_ops,
  74. struct clk *gate,
  75. const struct clk_ops *gate_ops,
  76. unsigned long flags)
  77. {
  78. struct clk *clk;
  79. struct clk_composite *composite;
  80. int ret;
  81. struct clk_ops *composite_ops = &clk_composite_ops;
  82. composite = kzalloc(sizeof(*composite), GFP_KERNEL);
  83. if (!composite)
  84. return ERR_PTR(-ENOMEM);
  85. if (mux && mux_ops) {
  86. composite->mux = mux;
  87. composite->mux_ops = mux_ops;
  88. if (mux_ops->set_parent)
  89. composite_ops->set_parent = clk_composite_set_parent;
  90. mux->data = (ulong)composite;
  91. }
  92. if (rate && rate_ops) {
  93. if (!rate_ops->get_rate) {
  94. clk = ERR_PTR(-EINVAL);
  95. goto err;
  96. }
  97. composite_ops->get_rate = clk_composite_recalc_rate;
  98. /* .set_rate requires either .round_rate or .determine_rate */
  99. if (rate_ops->set_rate)
  100. composite_ops->set_rate = clk_composite_set_rate;
  101. composite->rate = rate;
  102. composite->rate_ops = rate_ops;
  103. rate->data = (ulong)composite;
  104. }
  105. if (gate && gate_ops) {
  106. if (!gate_ops->enable || !gate_ops->disable) {
  107. clk = ERR_PTR(-EINVAL);
  108. goto err;
  109. }
  110. composite->gate = gate;
  111. composite->gate_ops = gate_ops;
  112. composite_ops->enable = clk_composite_enable;
  113. composite_ops->disable = clk_composite_disable;
  114. gate->data = (ulong)composite;
  115. }
  116. clk = &composite->clk;
  117. ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
  118. parent_names[clk_composite_get_parent(clk)]);
  119. if (ret) {
  120. clk = ERR_PTR(ret);
  121. goto err;
  122. }
  123. if (composite->mux)
  124. composite->mux->dev = clk->dev;
  125. if (composite->rate)
  126. composite->rate->dev = clk->dev;
  127. if (composite->gate)
  128. composite->gate->dev = clk->dev;
  129. return clk;
  130. err:
  131. kfree(composite);
  132. return clk;
  133. }
  134. U_BOOT_DRIVER(clk_composite) = {
  135. .name = UBOOT_DM_CLK_COMPOSITE,
  136. .id = UCLASS_CLK,
  137. .ops = &clk_composite_ops,
  138. .flags = DM_FLAG_PRE_RELOC,
  139. };