config_mpc85xx.h 31 KB

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  1. /*
  2. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _ASM_MPC85xx_CONFIG_H_
  7. #define _ASM_MPC85xx_CONFIG_H_
  8. /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
  9. #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
  10. #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
  11. #endif
  12. /*
  13. * This macro should be removed when we no longer care about backwards
  14. * compatibility with older operating systems.
  15. */
  16. #define CONFIG_PPC_SPINTABLE_COMPATIBLE
  17. #include <fsl_ddrc_version.h>
  18. #define CONFIG_SYS_FSL_DDR_BE
  19. /* IP endianness */
  20. #define CONFIG_SYS_FSL_IFC_BE
  21. #define CONFIG_SYS_FSL_SEC_BE
  22. #define CONFIG_SYS_FSL_SFP_BE
  23. #define CONFIG_SYS_FSL_SEC_MON_BE
  24. /* Number of TLB CAM entries we have on FSL Book-E chips */
  25. #if defined(CONFIG_E500MC)
  26. #define CONFIG_SYS_NUM_TLBCAMS 64
  27. #elif defined(CONFIG_E500)
  28. #define CONFIG_SYS_NUM_TLBCAMS 16
  29. #endif
  30. #if defined(CONFIG_ARCH_MPC8536)
  31. #define CONFIG_MAX_CPUS 1
  32. #define CONFIG_SYS_FSL_NUM_LAWS 12
  33. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
  34. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  35. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  36. #define CONFIG_SYS_FSL_ERRATUM_A004508
  37. #define CONFIG_SYS_FSL_ERRATUM_A005125
  38. #elif defined(CONFIG_ARCH_MPC8540)
  39. #define CONFIG_MAX_CPUS 1
  40. #define CONFIG_SYS_FSL_NUM_LAWS 8
  41. #define CONFIG_SYS_FSL_DDRC_GEN1
  42. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  43. #elif defined(CONFIG_ARCH_MPC8541)
  44. #define CONFIG_MAX_CPUS 1
  45. #define CONFIG_SYS_FSL_NUM_LAWS 8
  46. #define CONFIG_SYS_FSL_DDRC_GEN1
  47. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  48. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  49. #elif defined(CONFIG_ARCH_MPC8544)
  50. #define CONFIG_MAX_CPUS 1
  51. #define CONFIG_SYS_FSL_NUM_LAWS 10
  52. #define CONFIG_SYS_FSL_DDRC_GEN2
  53. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  54. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  55. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  56. #define CONFIG_SYS_FSL_ERRATUM_A005125
  57. #elif defined(CONFIG_ARCH_MPC8548)
  58. #define CONFIG_MAX_CPUS 1
  59. #define CONFIG_SYS_FSL_NUM_LAWS 10
  60. #define CONFIG_SYS_FSL_DDRC_GEN2
  61. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  62. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  63. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  64. #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  65. #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  66. #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  67. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  68. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  69. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  70. #define CONFIG_SYS_FSL_RMU
  71. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  72. #define CONFIG_SYS_FSL_ERRATUM_A005125
  73. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  74. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
  75. #elif defined(CONFIG_ARCH_MPC8555)
  76. #define CONFIG_MAX_CPUS 1
  77. #define CONFIG_SYS_FSL_NUM_LAWS 8
  78. #define CONFIG_SYS_FSL_DDRC_GEN1
  79. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  80. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  81. #elif defined(CONFIG_ARCH_MPC8560)
  82. #define CONFIG_MAX_CPUS 1
  83. #define CONFIG_SYS_FSL_NUM_LAWS 8
  84. #define CONFIG_SYS_FSL_DDRC_GEN1
  85. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  86. #elif defined(CONFIG_ARCH_MPC8568)
  87. #define CONFIG_MAX_CPUS 1
  88. #define CONFIG_SYS_FSL_NUM_LAWS 10
  89. #define CONFIG_SYS_FSL_DDRC_GEN2
  90. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  91. #define QE_MURAM_SIZE 0x10000UL
  92. #define MAX_QE_RISC 2
  93. #define QE_NUM_OF_SNUM 28
  94. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  95. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  96. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  97. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  98. #define CONFIG_SYS_FSL_RMU
  99. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  100. #elif defined(CONFIG_ARCH_MPC8569)
  101. #define CONFIG_MAX_CPUS 1
  102. #define CONFIG_SYS_FSL_NUM_LAWS 10
  103. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  104. #define QE_MURAM_SIZE 0x20000UL
  105. #define MAX_QE_RISC 4
  106. #define QE_NUM_OF_SNUM 46
  107. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  108. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  109. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  110. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  111. #define CONFIG_SYS_FSL_RMU
  112. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  113. #define CONFIG_SYS_FSL_ERRATUM_A004508
  114. #define CONFIG_SYS_FSL_ERRATUM_A005125
  115. #elif defined(CONFIG_ARCH_MPC8572)
  116. #define CONFIG_MAX_CPUS 2
  117. #define CONFIG_SYS_FSL_NUM_LAWS 12
  118. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  119. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  120. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  121. #define CONFIG_SYS_FSL_ERRATUM_DDR_115
  122. #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  123. #define CONFIG_SYS_FSL_ERRATUM_A004508
  124. #define CONFIG_SYS_FSL_ERRATUM_A005125
  125. #elif defined(CONFIG_ARCH_P1010)
  126. #define CONFIG_MAX_CPUS 1
  127. #define CONFIG_FSL_SDHC_V2_3
  128. #define CONFIG_SYS_FSL_NUM_LAWS 12
  129. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  130. #define CONFIG_TSECV2
  131. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  132. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  133. #define CONFIG_NUM_DDR_CONTROLLERS 1
  134. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  135. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  136. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  137. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  138. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  139. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  140. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  141. #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  142. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  143. #define CONFIG_SYS_FSL_ERRATUM_A005125
  144. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  145. #define CONFIG_SYS_FSL_ERRATUM_A004508
  146. #define CONFIG_SYS_FSL_ERRATUM_A007075
  147. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  148. #define CONFIG_SYS_FSL_ERRATUM_A006261
  149. #define CONFIG_SYS_FSL_ERRATUM_A004477
  150. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
  151. #define CONFIG_ESDHC_HC_BLK_ADDR
  152. /* P1011 is single core version of P1020 */
  153. #elif defined(CONFIG_ARCH_P1011)
  154. #define CONFIG_MAX_CPUS 1
  155. #define CONFIG_SYS_FSL_NUM_LAWS 12
  156. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  157. #define CONFIG_TSECV2
  158. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  159. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  160. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  161. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  162. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  163. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  164. #define CONFIG_SYS_FSL_ERRATUM_A004508
  165. #define CONFIG_SYS_FSL_ERRATUM_A005125
  166. #elif defined(CONFIG_ARCH_P1020)
  167. #define CONFIG_MAX_CPUS 2
  168. #define CONFIG_SYS_FSL_NUM_LAWS 12
  169. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  170. #define CONFIG_TSECV2
  171. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  172. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  173. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  174. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  175. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  176. #define CONFIG_SYS_FSL_ERRATUM_A004508
  177. #define CONFIG_SYS_FSL_ERRATUM_A005125
  178. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  179. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  180. #endif
  181. #elif defined(CONFIG_ARCH_P1021)
  182. #define CONFIG_MAX_CPUS 2
  183. #define CONFIG_SYS_FSL_NUM_LAWS 12
  184. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  185. #define CONFIG_TSECV2
  186. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  187. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  188. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  189. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  190. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  191. #define QE_MURAM_SIZE 0x6000UL
  192. #define MAX_QE_RISC 1
  193. #define QE_NUM_OF_SNUM 28
  194. #define CONFIG_SYS_FSL_ERRATUM_A004508
  195. #define CONFIG_SYS_FSL_ERRATUM_A005125
  196. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  197. #elif defined(CONFIG_ARCH_P1022)
  198. #define CONFIG_MAX_CPUS 2
  199. #define CONFIG_SYS_FSL_NUM_LAWS 12
  200. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  201. #define CONFIG_TSECV2
  202. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  203. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  204. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  205. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  206. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  207. #define CONFIG_FSL_SATA_ERRATUM_A001
  208. #define CONFIG_SYS_FSL_ERRATUM_A004508
  209. #define CONFIG_SYS_FSL_ERRATUM_A005125
  210. #define CONFIG_SYS_FSL_ERRATUM_A004477
  211. #elif defined(CONFIG_ARCH_P1023)
  212. #define CONFIG_MAX_CPUS 2
  213. #define CONFIG_SYS_FSL_NUM_LAWS 12
  214. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  215. #define CONFIG_SYS_NUM_FMAN 1
  216. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  217. #define CONFIG_NUM_DDR_CONTROLLERS 1
  218. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  219. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  220. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  221. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  222. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  223. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
  224. #define CONFIG_SYS_FSL_ERRATUM_A004508
  225. #define CONFIG_SYS_FSL_ERRATUM_A005125
  226. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  227. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  228. /* P1024 is lower end variant of P1020 */
  229. #elif defined(CONFIG_ARCH_P1024)
  230. #define CONFIG_MAX_CPUS 2
  231. #define CONFIG_SYS_FSL_NUM_LAWS 12
  232. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  233. #define CONFIG_TSECV2
  234. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  235. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  236. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  237. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  238. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  239. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  240. #define CONFIG_SYS_FSL_ERRATUM_A004508
  241. #define CONFIG_SYS_FSL_ERRATUM_A005125
  242. /* P1025 is lower end variant of P1021 */
  243. #elif defined(CONFIG_ARCH_P1025)
  244. #define CONFIG_MAX_CPUS 2
  245. #define CONFIG_SYS_FSL_NUM_LAWS 12
  246. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  247. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  248. #define CONFIG_TSECV2
  249. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  250. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  251. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  252. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  253. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  254. #define QE_MURAM_SIZE 0x6000UL
  255. #define MAX_QE_RISC 1
  256. #define QE_NUM_OF_SNUM 28
  257. #define CONFIG_SYS_FSL_ERRATUM_A004508
  258. #define CONFIG_SYS_FSL_ERRATUM_A005125
  259. #elif defined(CONFIG_ARCH_P2020)
  260. #define CONFIG_MAX_CPUS 2
  261. #define CONFIG_SYS_FSL_NUM_LAWS 12
  262. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  263. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  264. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  265. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  266. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  267. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  268. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  269. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  270. #define CONFIG_SYS_FSL_RMU
  271. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  272. #define CONFIG_SYS_FSL_ERRATUM_A004508
  273. #define CONFIG_SYS_FSL_ERRATUM_A005125
  274. #define CONFIG_SYS_FSL_ERRATUM_A004477
  275. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  276. #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
  277. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  278. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  279. #define CONFIG_MAX_CPUS 4
  280. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  281. #define CONFIG_SYS_FSL_NUM_LAWS 32
  282. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  283. #define CONFIG_SYS_NUM_FMAN 1
  284. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  285. #define CONFIG_SYS_NUM_FM1_10GEC 1
  286. #define CONFIG_NUM_DDR_CONTROLLERS 1
  287. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  288. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  289. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  290. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  291. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  292. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  293. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  294. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  295. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  296. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  297. #define CONFIG_SYS_FSL_ERRATUM_USB14
  298. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  299. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  300. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  301. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  302. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  303. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  304. #define CONFIG_SYS_FSL_ERRATUM_A004510
  305. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  306. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  307. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  308. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  309. #define CONFIG_SYS_FSL_ERRATUM_A004849
  310. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  311. #define CONFIG_SYS_FSL_ERRATUM_A006261
  312. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  313. #elif defined(CONFIG_PPC_P3041)
  314. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  315. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  316. #define CONFIG_MAX_CPUS 4
  317. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  318. #define CONFIG_SYS_FSL_NUM_LAWS 32
  319. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  320. #define CONFIG_SYS_NUM_FMAN 1
  321. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  322. #define CONFIG_SYS_NUM_FM1_10GEC 1
  323. #define CONFIG_NUM_DDR_CONTROLLERS 1
  324. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
  325. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  326. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  327. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  328. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  329. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  330. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  331. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  332. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  333. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  334. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  335. #define CONFIG_SYS_FSL_ERRATUM_USB14
  336. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  337. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  338. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  339. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  340. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  341. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  342. #define CONFIG_SYS_FSL_ERRATUM_A004510
  343. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  344. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  345. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  346. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  347. #define CONFIG_SYS_FSL_ERRATUM_A004849
  348. #define CONFIG_SYS_FSL_ERRATUM_A005812
  349. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  350. #define CONFIG_SYS_FSL_ERRATUM_A006261
  351. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  352. #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
  353. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  354. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  355. #define CONFIG_MAX_CPUS 8
  356. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  357. #define CONFIG_SYS_FSL_NUM_LAWS 32
  358. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  359. #define CONFIG_SYS_NUM_FMAN 2
  360. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  361. #define CONFIG_SYS_NUM_FM2_DTSEC 4
  362. #define CONFIG_SYS_NUM_FM1_10GEC 1
  363. #define CONFIG_SYS_NUM_FM2_10GEC 1
  364. #define CONFIG_NUM_DDR_CONTROLLERS 2
  365. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  366. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  367. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  368. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  369. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  370. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  371. #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
  372. #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
  373. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  374. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  375. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  376. #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
  377. #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
  378. #define CONFIG_SYS_P4080_ERRATUM_CPU22
  379. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  380. #define CONFIG_SYS_P4080_ERRATUM_SERDES8
  381. #define CONFIG_SYS_P4080_ERRATUM_SERDES9
  382. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  383. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  384. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  385. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  386. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  387. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  388. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  389. #define CONFIG_SYS_FSL_RMU
  390. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  391. #define CONFIG_SYS_FSL_ERRATUM_A004510
  392. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
  393. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
  394. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  395. #define CONFIG_SYS_FSL_ERRATUM_A004849
  396. #define CONFIG_SYS_FSL_ERRATUM_A004580
  397. #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  398. #define CONFIG_SYS_FSL_ERRATUM_A005812
  399. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  400. #define CONFIG_SYS_FSL_ERRATUM_A007075
  401. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  402. #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
  403. #define CONFIG_SYS_PPC64 /* 64-bit core */
  404. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  405. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  406. #define CONFIG_MAX_CPUS 2
  407. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  408. #define CONFIG_SYS_FSL_NUM_LAWS 32
  409. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  410. #define CONFIG_SYS_NUM_FMAN 1
  411. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  412. #define CONFIG_SYS_NUM_FM1_10GEC 1
  413. #define CONFIG_NUM_DDR_CONTROLLERS 2
  414. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  415. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  416. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  417. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  418. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  419. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  420. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  421. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  422. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  423. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  424. #define CONFIG_SYS_FSL_ERRATUM_USB14
  425. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  426. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  427. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  428. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  429. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  430. #define CONFIG_SYS_FSL_ERRATUM_A004510
  431. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  432. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
  433. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  434. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  435. #define CONFIG_SYS_FSL_ERRATUM_A006261
  436. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  437. #elif defined(CONFIG_PPC_P5040)
  438. #define CONFIG_SYS_PPC64
  439. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  440. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  441. #define CONFIG_MAX_CPUS 4
  442. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  443. #define CONFIG_SYS_FSL_NUM_LAWS 32
  444. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  445. #define CONFIG_SYS_NUM_FMAN 2
  446. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  447. #define CONFIG_SYS_NUM_FM1_10GEC 1
  448. #define CONFIG_SYS_NUM_FM2_DTSEC 5
  449. #define CONFIG_SYS_NUM_FM2_10GEC 1
  450. #define CONFIG_NUM_DDR_CONTROLLERS 2
  451. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  452. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  453. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  454. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  455. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  456. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  457. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  458. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  459. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  460. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  461. #define CONFIG_SYS_FSL_ERRATUM_USB14
  462. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  463. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  464. #define CONFIG_SYS_FSL_ERRATUM_A004699
  465. #define CONFIG_SYS_FSL_ERRATUM_A004510
  466. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  467. #define CONFIG_SYS_FSL_ERRATUM_A006261
  468. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  469. #define CONFIG_SYS_FSL_ERRATUM_A005812
  470. #elif defined(CONFIG_ARCH_BSC9131)
  471. #define CONFIG_MAX_CPUS 1
  472. #define CONFIG_FSL_SDHC_V2_3
  473. #define CONFIG_SYS_FSL_NUM_LAWS 12
  474. #define CONFIG_TSECV2
  475. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  476. #define CONFIG_NUM_DDR_CONTROLLERS 1
  477. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  478. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  479. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  480. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  481. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  482. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  483. #define CONFIG_NAND_FSL_IFC
  484. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  485. #define CONFIG_SYS_FSL_ERRATUM_A005125
  486. #define CONFIG_SYS_FSL_ERRATUM_A004477
  487. #define CONFIG_ESDHC_HC_BLK_ADDR
  488. #elif defined(CONFIG_ARCH_BSC9132)
  489. #define CONFIG_MAX_CPUS 2
  490. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  491. #define CONFIG_FSL_SDHC_V2_3
  492. #define CONFIG_SYS_FSL_NUM_LAWS 12
  493. #define CONFIG_TSECV2
  494. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  495. #define CONFIG_NUM_DDR_CONTROLLERS 2
  496. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  497. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  498. #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
  499. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  500. #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
  501. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  502. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  503. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  504. #define CONFIG_NAND_FSL_IFC
  505. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  506. #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
  507. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  508. #define CONFIG_SYS_FSL_ERRATUM_A005125
  509. #define CONFIG_SYS_FSL_ERRATUM_A005434
  510. #define CONFIG_SYS_FSL_ERRATUM_A004477
  511. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  512. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  513. #define CONFIG_ESDHC_HC_BLK_ADDR
  514. #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
  515. defined(CONFIG_PPC_T4080)
  516. #define CONFIG_E6500
  517. #define CONFIG_SYS_PPC64 /* 64-bit core */
  518. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  519. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  520. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  521. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  522. #ifdef CONFIG_PPC_T4240
  523. #define CONFIG_MAX_CPUS 12
  524. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
  525. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  526. #define CONFIG_SYS_NUM_FM1_10GEC 2
  527. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  528. #define CONFIG_SYS_NUM_FM2_10GEC 2
  529. #define CONFIG_NUM_DDR_CONTROLLERS 3
  530. #define CONFIG_SYS_FSL_ERRATUM_A006261
  531. #else
  532. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  533. #define CONFIG_SYS_NUM_FM1_10GEC 1
  534. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  535. #define CONFIG_SYS_NUM_FM2_10GEC 1
  536. #define CONFIG_NUM_DDR_CONTROLLERS 2
  537. #if defined(CONFIG_PPC_T4160)
  538. #define CONFIG_MAX_CPUS 8
  539. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  540. #elif defined(CONFIG_PPC_T4080)
  541. #define CONFIG_MAX_CPUS 4
  542. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
  543. #endif
  544. #endif
  545. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  546. #define CONFIG_SYS_FSL_NUM_LAWS 32
  547. #define CONFIG_SYS_FSL_SRDS_1
  548. #define CONFIG_SYS_FSL_SRDS_2
  549. #define CONFIG_SYS_FSL_SRDS_3
  550. #define CONFIG_SYS_FSL_SRDS_4
  551. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  552. #define CONFIG_SYS_NUM_FMAN 2
  553. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  554. #define CONFIG_SYS_PME_CLK 0
  555. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  556. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  557. #define CONFIG_SYS_FMAN_V3
  558. #define CONFIG_SYS_FM1_CLK 3
  559. #define CONFIG_SYS_FM2_CLK 3
  560. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  561. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  562. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  563. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  564. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  565. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  566. #define CONFIG_SYS_FSL_SRIO_LIODN
  567. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  568. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  569. #define CONFIG_SYS_FSL_ERRATUM_A004468
  570. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  571. #define CONFIG_SYS_FSL_ERRATUM_A005871
  572. #define CONFIG_SYS_FSL_ERRATUM_A006379
  573. #define CONFIG_SYS_FSL_ERRATUM_A007186
  574. #define CONFIG_SYS_FSL_ERRATUM_A006593
  575. #define CONFIG_SYS_FSL_ERRATUM_A007798
  576. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  577. #define CONFIG_SYS_FSL_SFP_VER_3_0
  578. #define CONFIG_SYS_FSL_PCI_VER_3_X
  579. #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
  580. #define CONFIG_E6500
  581. #define CONFIG_SYS_PPC64 /* 64-bit core */
  582. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  583. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  584. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  585. #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
  586. #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
  587. #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
  588. #define CONFIG_SYS_FSL_NUM_LAWS 32
  589. #define CONFIG_SYS_FSL_SRDS_1
  590. #define CONFIG_SYS_FSL_SRDS_2
  591. #define CONFIG_SYS_MAPLE
  592. #define CONFIG_SYS_CPRI
  593. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  594. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  595. #define CONFIG_SYS_NUM_FMAN 1
  596. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  597. #define CONFIG_SYS_FM1_CLK 0
  598. #define CONFIG_SYS_CPRI_CLK 3
  599. #define CONFIG_SYS_ULB_CLK 4
  600. #define CONFIG_SYS_ETVPE_CLK 1
  601. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  602. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  603. #define CONFIG_SYS_FMAN_V3
  604. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  605. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  606. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  607. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  608. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  609. #define CONFIG_SYS_FSL_ERRATUM_A005871
  610. #define CONFIG_SYS_FSL_ERRATUM_A006379
  611. #define CONFIG_SYS_FSL_ERRATUM_A007186
  612. #define CONFIG_SYS_FSL_ERRATUM_A006593
  613. #define CONFIG_SYS_FSL_ERRATUM_A007075
  614. #define CONFIG_SYS_FSL_ERRATUM_A006475
  615. #define CONFIG_SYS_FSL_ERRATUM_A006384
  616. #define CONFIG_SYS_FSL_ERRATUM_A007212
  617. #define CONFIG_SYS_FSL_ERRATUM_A004477
  618. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  619. #define CONFIG_SYS_FSL_SFP_VER_3_0
  620. #ifdef CONFIG_PPC_B4860
  621. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  622. #define CONFIG_MAX_CPUS 4
  623. #define CONFIG_MAX_DSP_CPUS 12
  624. #define CONFIG_NUM_DSP_CPUS 6
  625. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
  626. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  627. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  628. #define CONFIG_SYS_NUM_FM1_10GEC 2
  629. #define CONFIG_NUM_DDR_CONTROLLERS 2
  630. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  631. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  632. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  633. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  634. #define CONFIG_SYS_FSL_SRIO_LIODN
  635. #else
  636. #define CONFIG_MAX_CPUS 2
  637. #define CONFIG_MAX_DSP_CPUS 2
  638. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
  639. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
  640. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
  641. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  642. #define CONFIG_SYS_NUM_FM1_10GEC 0
  643. #define CONFIG_NUM_DDR_CONTROLLERS 1
  644. #endif
  645. #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
  646. defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
  647. #define CONFIG_E5500
  648. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  649. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  650. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  651. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  652. #ifdef CONFIG_SYS_FSL_DDR4
  653. #define CONFIG_SYS_FSL_DDRC_GEN4
  654. #endif
  655. #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
  656. #define CONFIG_MAX_CPUS 4
  657. #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
  658. #define CONFIG_MAX_CPUS 2
  659. #endif
  660. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  661. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  662. #define CONFIG_SYS_FSL_NUM_LAWS 16
  663. #define CONFIG_SYS_FSL_SRDS_1
  664. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  665. #define CONFIG_SYS_NUM_FMAN 1
  666. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  667. #define CONFIG_NUM_DDR_CONTROLLERS 1
  668. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  669. #define CONFIG_PME_PLAT_CLK_DIV 2
  670. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  671. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  672. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  673. #define CONFIG_SYS_FSL_ERRATUM_A008044
  674. #define CONFIG_SYS_FMAN_V3
  675. #define CONFIG_FM_PLAT_CLK_DIV 1
  676. #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
  677. #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  678. per rcw field value */
  679. #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
  680. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  681. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  682. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  683. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  684. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  685. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  686. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  687. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  688. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  689. #define QE_MURAM_SIZE 0x6000UL
  690. #define MAX_QE_RISC 1
  691. #define QE_NUM_OF_SNUM 28
  692. #define CONFIG_SYS_FSL_SFP_VER_3_0
  693. #define CONFIG_SYS_FSL_ERRATUM_A008378
  694. #define CONFIG_SYS_FSL_ERRATUM_A009663
  695. #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
  696. defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
  697. #define CONFIG_E5500
  698. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  699. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  700. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  701. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  702. #define CONFIG_SYS_FMAN_V3
  703. #ifdef CONFIG_SYS_FSL_DDR4
  704. #define CONFIG_SYS_FSL_DDRC_GEN4
  705. #endif
  706. #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
  707. #define CONFIG_MAX_CPUS 2
  708. #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
  709. #define CONFIG_MAX_CPUS 1
  710. #endif
  711. #define CONFIG_SYS_FSL_NUM_CC_PLL 2
  712. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  713. #define CONFIG_SYS_FSL_NUM_LAWS 16
  714. #define CONFIG_SYS_FSL_SRDS_1
  715. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  716. #define CONFIG_SYS_NUM_FMAN 1
  717. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  718. #define CONFIG_SYS_NUM_FM1_10GEC 1
  719. #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  720. #define CONFIG_NUM_DDR_CONTROLLERS 1
  721. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  722. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  723. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  724. #define CONFIG_SYS_FM1_CLK 0
  725. #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  726. per rcw field value */
  727. #define CONFIG_QBMAN_CLK_DIV 1
  728. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  729. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  730. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  731. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  732. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  733. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  734. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  735. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  736. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  737. #define QE_MURAM_SIZE 0x6000UL
  738. #define MAX_QE_RISC 1
  739. #define QE_NUM_OF_SNUM 28
  740. #define CONFIG_SYS_FSL_SFP_VER_3_0
  741. #define CONFIG_SYS_FSL_ERRATUM_A008378
  742. #define CONFIG_SYS_FSL_ERRATUM_A009663
  743. #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
  744. #define CONFIG_E6500
  745. #define CONFIG_SYS_PPC64 /* 64-bit core */
  746. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  747. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  748. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  749. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  750. #define CONFIG_SYS_FSL_QMAN_V3
  751. #define CONFIG_MAX_CPUS 4
  752. #define CONFIG_SYS_FSL_NUM_LAWS 32
  753. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  754. #define CONFIG_SYS_NUM_FMAN 1
  755. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  756. #define CONFIG_SYS_FSL_SRDS_1
  757. #define CONFIG_SYS_FSL_PCI_VER_3_X
  758. #if defined(CONFIG_PPC_T2080)
  759. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  760. #define CONFIG_SYS_NUM_FM1_10GEC 4
  761. #define CONFIG_SYS_FSL_SRDS_2
  762. #define CONFIG_SYS_FSL_SRIO_LIODN
  763. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  764. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  765. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  766. #elif defined(CONFIG_PPC_T2081)
  767. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  768. #define CONFIG_SYS_NUM_FM1_10GEC 2
  769. #endif
  770. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  771. #define CONFIG_NUM_DDR_CONTROLLERS 1
  772. #define CONFIG_PME_PLAT_CLK_DIV 1
  773. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  774. #define CONFIG_SYS_FM1_CLK 0
  775. #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
  776. per rcw field value */
  777. #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
  778. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  779. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  780. #define CONFIG_SYS_FMAN_V3
  781. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  782. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  783. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  784. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  785. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  786. #define CONFIG_SYS_FSL_ERRATUM_A007212
  787. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  788. #define CONFIG_SYS_FSL_SFP_VER_3_0
  789. #define CONFIG_SYS_FSL_ISBC_VER 2
  790. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  791. #define CONFIG_SYS_FSL_ERRATUM_A006593
  792. #define CONFIG_SYS_FSL_ERRATUM_A007186
  793. #define CONFIG_SYS_FSL_ERRATUM_A006379
  794. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  795. #define CONFIG_SYS_FSL_SFP_VER_3_0
  796. #elif defined(CONFIG_ARCH_C29X)
  797. #define CONFIG_MAX_CPUS 1
  798. #define CONFIG_FSL_SDHC_V2_3
  799. #define CONFIG_SYS_FSL_NUM_LAWS 12
  800. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  801. #define CONFIG_TSECV2_1
  802. #define CONFIG_SYS_FSL_SEC_COMPAT 6
  803. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  804. #define CONFIG_NUM_DDR_CONTROLLERS 1
  805. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  806. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  807. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  808. #define CONFIG_SYS_FSL_ERRATUM_A005125
  809. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
  810. #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
  811. #elif defined(CONFIG_QEMU_E500)
  812. #define CONFIG_MAX_CPUS 1
  813. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
  814. #else
  815. #error Processor type not defined for this platform
  816. #endif
  817. #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
  818. #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
  819. #endif
  820. #ifdef CONFIG_E6500
  821. #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
  822. #else
  823. #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
  824. #endif
  825. #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
  826. !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
  827. !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
  828. !defined(CONFIG_SYS_FSL_DDRC_GEN4)
  829. #define CONFIG_SYS_FSL_DDRC_GEN3
  830. #endif
  831. #if !defined(CONFIG_ARCH_C29X)
  832. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  833. #endif
  834. #endif /* _ASM_MPC85xx_CONFIG_H_ */