duovero.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Gumstix Inc. <www.gumstix.com>
  5. * Maintainer: Ash Charles <ash@gumstix.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <net.h>
  10. #include <netdev.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/mmc_host_def.h>
  13. #include <twl6030.h>
  14. #include <asm/emif.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/gpio.h>
  18. #include <asm/mach-types.h>
  19. #include <linux/delay.h>
  20. #include "duovero_mux_data.h"
  21. #define WIFI_EN 43
  22. #if defined(CONFIG_CMD_NET)
  23. #define SMSC_NRESET 45
  24. static void setup_net_chip(void);
  25. #endif
  26. #ifdef CONFIG_USB_EHCI_HCD
  27. #include <usb.h>
  28. #include <asm/arch/ehci.h>
  29. #include <asm/ehci-omap.h>
  30. #endif
  31. DECLARE_GLOBAL_DATA_PTR;
  32. const struct omap_sysinfo sysinfo = {
  33. "Board: duovero\n"
  34. };
  35. struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
  36. /**
  37. * @brief board_init
  38. *
  39. * @return 0
  40. */
  41. int board_init(void)
  42. {
  43. gpmc_init();
  44. gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
  45. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  46. return 0;
  47. }
  48. /**
  49. * @brief misc_init_r - Configure board specific configurations
  50. * such as power configurations, ethernet initialization as phase2 of
  51. * boot sequence
  52. *
  53. * @return 0
  54. */
  55. int misc_init_r(void)
  56. {
  57. int ret = 0;
  58. u8 val;
  59. /* wifi setup: first enable 32Khz clock from 6030 pmic */
  60. val = 0xe1;
  61. ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
  62. if (ret)
  63. printf("Failed to enable 32Khz clock to wifi module\n");
  64. /* then setup WIFI_EN as an output pin and send reset pulse */
  65. if (!gpio_request(WIFI_EN, "")) {
  66. gpio_direction_output(WIFI_EN, 0);
  67. gpio_set_value(WIFI_EN, 1);
  68. udelay(1);
  69. gpio_set_value(WIFI_EN, 0);
  70. udelay(1);
  71. gpio_set_value(WIFI_EN, 1);
  72. }
  73. #if defined(CONFIG_CMD_NET)
  74. setup_net_chip();
  75. #endif
  76. return 0;
  77. }
  78. void set_muxconf_regs(void)
  79. {
  80. do_set_mux((*ctrl)->control_padconf_core_base,
  81. core_padconf_array_essential,
  82. sizeof(core_padconf_array_essential) /
  83. sizeof(struct pad_conf_entry));
  84. do_set_mux((*ctrl)->control_padconf_wkup_base,
  85. wkup_padconf_array_essential,
  86. sizeof(wkup_padconf_array_essential) /
  87. sizeof(struct pad_conf_entry));
  88. do_set_mux((*ctrl)->control_padconf_core_base,
  89. core_padconf_array_non_essential,
  90. sizeof(core_padconf_array_non_essential) /
  91. sizeof(struct pad_conf_entry));
  92. do_set_mux((*ctrl)->control_padconf_wkup_base,
  93. wkup_padconf_array_non_essential,
  94. sizeof(wkup_padconf_array_non_essential) /
  95. sizeof(struct pad_conf_entry));
  96. }
  97. #if defined(CONFIG_MMC)
  98. int board_mmc_init(bd_t *bis)
  99. {
  100. return omap_mmc_init(0, 0, 0, -1, -1);
  101. }
  102. #if !defined(CONFIG_SPL_BUILD)
  103. void board_mmc_power_init(void)
  104. {
  105. twl6030_power_mmc_init(0);
  106. }
  107. #endif
  108. #endif
  109. #if defined(CONFIG_CMD_NET)
  110. #define GPMC_SIZE_16M 0xF
  111. #define GPMC_BASEADDR_MASK 0x3F
  112. #define GPMC_CS_ENABLE 0x1
  113. static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  114. u32 base, u32 size)
  115. {
  116. writel(0, &cs->config7);
  117. sdelay(1000);
  118. /* Delay for settling */
  119. writel(gpmc_config[0], &cs->config1);
  120. writel(gpmc_config[1], &cs->config2);
  121. writel(gpmc_config[2], &cs->config3);
  122. writel(gpmc_config[3], &cs->config4);
  123. writel(gpmc_config[4], &cs->config5);
  124. writel(gpmc_config[5], &cs->config6);
  125. /*
  126. * Enable the config. size is the CS size and goes in
  127. * bits 11:8. We set bit 6 to enable this CS and the base
  128. * address goes into bits 5:0.
  129. */
  130. writel((size << 8) | (GPMC_CS_ENABLE << 6) |
  131. ((base >> 24) & GPMC_BASEADDR_MASK),
  132. &cs->config7);
  133. sdelay(2000);
  134. }
  135. /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
  136. #define NET_LAN9221_GPMC_CONFIG1 0x2a001203
  137. #define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
  138. #define NET_LAN9221_GPMC_CONFIG3 0x00020200
  139. #define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
  140. #define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
  141. #define NET_LAN9221_GPMC_CONFIG6 0x8a070707
  142. #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
  143. /* GPMC definitions for LAN9221 chips on expansion boards */
  144. static const u32 gpmc_lan_config[] = {
  145. NET_LAN9221_GPMC_CONFIG1,
  146. NET_LAN9221_GPMC_CONFIG2,
  147. NET_LAN9221_GPMC_CONFIG3,
  148. NET_LAN9221_GPMC_CONFIG4,
  149. NET_LAN9221_GPMC_CONFIG5,
  150. NET_LAN9221_GPMC_CONFIG6,
  151. /*CONFIG7- computed as params */
  152. };
  153. /*
  154. * Routine: setup_net_chip
  155. * Description: Setting up the configuration GPMC registers specific to the
  156. * Ethernet hardware.
  157. */
  158. static void setup_net_chip(void)
  159. {
  160. enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
  161. GPMC_SIZE_16M);
  162. /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
  163. if (!gpio_request(SMSC_NRESET, "")) {
  164. gpio_direction_output(SMSC_NRESET, 0);
  165. gpio_set_value(SMSC_NRESET, 1);
  166. udelay(1);
  167. gpio_set_value(SMSC_NRESET, 0);
  168. udelay(1);
  169. gpio_set_value(SMSC_NRESET, 1);
  170. }
  171. }
  172. #endif
  173. int board_eth_init(bd_t *bis)
  174. {
  175. int rc = 0;
  176. #ifdef CONFIG_SMC911X
  177. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  178. #endif
  179. return rc;
  180. }
  181. #ifdef CONFIG_USB_EHCI_HCD
  182. static struct omap_usbhs_board_data usbhs_bdata = {
  183. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  184. .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
  185. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  186. };
  187. int ehci_hcd_init(int index, enum usb_init_type init,
  188. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  189. {
  190. int ret;
  191. unsigned int utmi_clk;
  192. u32 auxclk, altclksrc;
  193. /* Now we can enable our port clocks */
  194. utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
  195. utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
  196. setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
  197. auxclk = readl(&scrm->auxclk3);
  198. /* Select sys_clk */
  199. auxclk &= ~AUXCLK_SRCSELECT_MASK;
  200. auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
  201. /* Set the divisor to 2 */
  202. auxclk &= ~AUXCLK_CLKDIV_MASK;
  203. auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
  204. /* Request auxilary clock #3 */
  205. auxclk |= AUXCLK_ENABLE_MASK;
  206. writel(auxclk, &scrm->auxclk3);
  207. altclksrc = readl(&scrm->altclksrc);
  208. /* Activate alternate system clock supplier */
  209. altclksrc &= ~ALTCLKSRC_MODE_MASK;
  210. altclksrc |= ALTCLKSRC_MODE_ACTIVE;
  211. /* enable clocks */
  212. altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
  213. writel(altclksrc, &scrm->altclksrc);
  214. ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
  215. if (ret < 0)
  216. return ret;
  217. return 0;
  218. }
  219. int ehci_hcd_stop(int index)
  220. {
  221. return omap_ehci_hcd_stop();
  222. }
  223. #endif
  224. /*
  225. * get_board_rev() - get board revision
  226. */
  227. u32 get_board_rev(void)
  228. {
  229. return 0x20;
  230. }