dwc_ahsata.c 23 KB

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  1. /*
  2. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  3. * Terry Lv <r65388@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <ahci.h>
  9. #include <fis.h>
  10. #include <libata.h>
  11. #include <malloc.h>
  12. #include <memalign.h>
  13. #include <sata.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <linux/bitops.h>
  18. #include <linux/ctype.h>
  19. #include <linux/errno.h>
  20. #include "dwc_ahsata_priv.h"
  21. struct sata_port_regs {
  22. u32 clb;
  23. u32 clbu;
  24. u32 fb;
  25. u32 fbu;
  26. u32 is;
  27. u32 ie;
  28. u32 cmd;
  29. u32 res1[1];
  30. u32 tfd;
  31. u32 sig;
  32. u32 ssts;
  33. u32 sctl;
  34. u32 serr;
  35. u32 sact;
  36. u32 ci;
  37. u32 sntf;
  38. u32 res2[1];
  39. u32 dmacr;
  40. u32 res3[1];
  41. u32 phycr;
  42. u32 physr;
  43. };
  44. struct sata_host_regs {
  45. u32 cap;
  46. u32 ghc;
  47. u32 is;
  48. u32 pi;
  49. u32 vs;
  50. u32 ccc_ctl;
  51. u32 ccc_ports;
  52. u32 res1[2];
  53. u32 cap2;
  54. u32 res2[30];
  55. u32 bistafr;
  56. u32 bistcr;
  57. u32 bistfctr;
  58. u32 bistsr;
  59. u32 bistdecr;
  60. u32 res3[2];
  61. u32 oobr;
  62. u32 res4[8];
  63. u32 timer1ms;
  64. u32 res5[1];
  65. u32 gparam1r;
  66. u32 gparam2r;
  67. u32 pparamr;
  68. u32 testr;
  69. u32 versionr;
  70. u32 idr;
  71. };
  72. #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
  73. #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  74. #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  75. static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  76. {
  77. return base + 0x100 + (port * 0x80);
  78. }
  79. static int waiting_for_cmd_completed(u8 *offset,
  80. int timeout_msec,
  81. u32 sign)
  82. {
  83. int i;
  84. u32 status;
  85. for (i = 0;
  86. ((status = readl(offset)) & sign) && i < timeout_msec;
  87. ++i)
  88. mdelay(1);
  89. return (i < timeout_msec) ? 0 : -1;
  90. }
  91. static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
  92. {
  93. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  94. writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
  95. writel(0x02060b14, &host_mmio->oobr);
  96. return 0;
  97. }
  98. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  99. {
  100. u32 tmp, cap_save, num_ports;
  101. int i, j, timeout = 1000;
  102. struct sata_port_regs *port_mmio = NULL;
  103. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  104. int clk = mxc_get_clock(MXC_SATA_CLK);
  105. cap_save = readl(&host_mmio->cap);
  106. cap_save |= SATA_HOST_CAP_SSS;
  107. /* global controller reset */
  108. tmp = readl(&host_mmio->ghc);
  109. if ((tmp & SATA_HOST_GHC_HR) == 0)
  110. writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
  111. while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
  112. ;
  113. if (timeout <= 0) {
  114. debug("controller reset failed (0x%x)\n", tmp);
  115. return -1;
  116. }
  117. /* Set timer 1ms */
  118. writel(clk / 1000, &host_mmio->timer1ms);
  119. ahci_setup_oobr(uc_priv, 0);
  120. writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
  121. writel(cap_save, &host_mmio->cap);
  122. num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
  123. writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
  124. /*
  125. * Determine which Ports are implemented by the DWC_ahsata,
  126. * by reading the PI register. This bit map value aids the
  127. * software to determine how many Ports are available and
  128. * which Port registers need to be initialized.
  129. */
  130. uc_priv->cap = readl(&host_mmio->cap);
  131. uc_priv->port_map = readl(&host_mmio->pi);
  132. /* Determine how many command slots the HBA supports */
  133. uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
  134. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  135. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  136. for (i = 0; i < uc_priv->n_ports; i++) {
  137. uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
  138. port_mmio = uc_priv->port[i].port_mmio;
  139. /* Ensure that the DWC_ahsata is in idle state */
  140. tmp = readl(&port_mmio->cmd);
  141. /*
  142. * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
  143. * are all cleared, the Port is in an idle state.
  144. */
  145. if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
  146. SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
  147. /*
  148. * System software places a Port into the idle state by
  149. * clearing P#CMD.ST and waiting for P#CMD.CR to return
  150. * 0 when read.
  151. */
  152. tmp &= ~SATA_PORT_CMD_ST;
  153. writel_with_flush(tmp, &port_mmio->cmd);
  154. /*
  155. * spec says 500 msecs for each bit, so
  156. * this is slightly incorrect.
  157. */
  158. mdelay(500);
  159. timeout = 1000;
  160. while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
  161. && --timeout)
  162. ;
  163. if (timeout <= 0) {
  164. debug("port reset failed (0x%x)\n", tmp);
  165. return -1;
  166. }
  167. }
  168. /* Spin-up device */
  169. tmp = readl(&port_mmio->cmd);
  170. writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
  171. /* Wait for spin-up to finish */
  172. timeout = 1000;
  173. while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
  174. && --timeout)
  175. ;
  176. if (timeout <= 0) {
  177. debug("Spin-Up can't finish!\n");
  178. return -1;
  179. }
  180. for (j = 0; j < 100; ++j) {
  181. mdelay(10);
  182. tmp = readl(&port_mmio->ssts);
  183. if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
  184. ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
  185. break;
  186. }
  187. /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
  188. timeout = 1000;
  189. while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
  190. && --timeout)
  191. ;
  192. if (timeout <= 0) {
  193. debug("Can't find DIAG_X set!\n");
  194. return -1;
  195. }
  196. /*
  197. * For each implemented Port, clear the P#SERR
  198. * register, by writing ones to each implemented\
  199. * bit location.
  200. */
  201. tmp = readl(&port_mmio->serr);
  202. debug("P#SERR 0x%x\n",
  203. tmp);
  204. writel(tmp, &port_mmio->serr);
  205. /* Ack any pending irq events for this port */
  206. tmp = readl(&host_mmio->is);
  207. debug("IS 0x%x\n", tmp);
  208. if (tmp)
  209. writel(tmp, &host_mmio->is);
  210. writel(1 << i, &host_mmio->is);
  211. /* set irq mask (enables interrupts) */
  212. writel(DEF_PORT_IRQ, &port_mmio->ie);
  213. /* register linkup ports */
  214. tmp = readl(&port_mmio->ssts);
  215. debug("Port %d status: 0x%x\n", i, tmp);
  216. if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
  217. uc_priv->link_port_map |= (0x01 << i);
  218. }
  219. tmp = readl(&host_mmio->ghc);
  220. debug("GHC 0x%x\n", tmp);
  221. writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
  222. tmp = readl(&host_mmio->ghc);
  223. debug("GHC 0x%x\n", tmp);
  224. return 0;
  225. }
  226. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  227. {
  228. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  229. u32 vers, cap, impl, speed;
  230. const char *speed_s;
  231. const char *scc_s;
  232. vers = readl(&host_mmio->vs);
  233. cap = uc_priv->cap;
  234. impl = uc_priv->port_map;
  235. speed = (cap & SATA_HOST_CAP_ISS_MASK)
  236. >> SATA_HOST_CAP_ISS_OFFSET;
  237. if (speed == 1)
  238. speed_s = "1.5";
  239. else if (speed == 2)
  240. speed_s = "3";
  241. else
  242. speed_s = "?";
  243. scc_s = "SATA";
  244. printf("AHCI %02x%02x.%02x%02x "
  245. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  246. (vers >> 24) & 0xff,
  247. (vers >> 16) & 0xff,
  248. (vers >> 8) & 0xff,
  249. vers & 0xff,
  250. ((cap >> 8) & 0x1f) + 1,
  251. (cap & 0x1f) + 1,
  252. speed_s,
  253. impl,
  254. scc_s);
  255. printf("flags: "
  256. "%s%s%s%s%s%s"
  257. "%s%s%s%s%s%s%s\n",
  258. cap & (1 << 31) ? "64bit " : "",
  259. cap & (1 << 30) ? "ncq " : "",
  260. cap & (1 << 28) ? "ilck " : "",
  261. cap & (1 << 27) ? "stag " : "",
  262. cap & (1 << 26) ? "pm " : "",
  263. cap & (1 << 25) ? "led " : "",
  264. cap & (1 << 24) ? "clo " : "",
  265. cap & (1 << 19) ? "nz " : "",
  266. cap & (1 << 18) ? "only " : "",
  267. cap & (1 << 17) ? "pmp " : "",
  268. cap & (1 << 15) ? "pio " : "",
  269. cap & (1 << 14) ? "slum " : "",
  270. cap & (1 << 13) ? "part " : "");
  271. }
  272. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  273. unsigned char *buf, int buf_len)
  274. {
  275. struct ahci_ioports *pp = &uc_priv->port[port];
  276. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  277. u32 sg_count, max_bytes;
  278. int i;
  279. max_bytes = MAX_DATA_BYTES_PER_SG;
  280. sg_count = ((buf_len - 1) / max_bytes) + 1;
  281. if (sg_count > AHCI_MAX_SG) {
  282. printf("Error:Too much sg!\n");
  283. return -1;
  284. }
  285. for (i = 0; i < sg_count; i++) {
  286. ahci_sg->addr =
  287. cpu_to_le32((u32)buf + i * max_bytes);
  288. ahci_sg->addr_hi = 0;
  289. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  290. (buf_len < max_bytes
  291. ? (buf_len - 1)
  292. : (max_bytes - 1)));
  293. ahci_sg++;
  294. buf_len -= max_bytes;
  295. }
  296. return sg_count;
  297. }
  298. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
  299. {
  300. struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
  301. AHCI_CMD_SLOT_SZ * cmd_slot);
  302. memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
  303. cmd_hdr->opts = cpu_to_le32(opts);
  304. cmd_hdr->status = 0;
  305. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  306. #ifdef CONFIG_PHYS_64BIT
  307. pp->cmd_slot->tbl_addr_hi =
  308. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  309. #endif
  310. }
  311. #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
  312. static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
  313. struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
  314. s32 is_write)
  315. {
  316. struct ahci_ioports *pp = &uc_priv->port[port];
  317. struct sata_port_regs *port_mmio = pp->port_mmio;
  318. u32 opts;
  319. int sg_count = 0, cmd_slot = 0;
  320. cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
  321. if (32 == cmd_slot) {
  322. printf("Can't find empty command slot!\n");
  323. return 0;
  324. }
  325. /* Check xfer length */
  326. if (buf_len > MAX_BYTES_PER_TRANS) {
  327. printf("Max transfer length is %dB\n\r",
  328. MAX_BYTES_PER_TRANS);
  329. return 0;
  330. }
  331. memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
  332. if (buf && buf_len)
  333. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  334. opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
  335. if (is_write) {
  336. opts |= 0x40;
  337. flush_cache((ulong)buf, buf_len);
  338. }
  339. ahci_fill_cmd_slot(pp, cmd_slot, opts);
  340. flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
  341. writel_with_flush(1 << cmd_slot, &port_mmio->ci);
  342. if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
  343. 0x1 << cmd_slot)) {
  344. printf("timeout exit!\n");
  345. return -1;
  346. }
  347. invalidate_dcache_range((int)(pp->cmd_slot),
  348. (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
  349. debug("ahci_exec_ata_cmd: %d byte transferred.\n",
  350. pp->cmd_slot->status);
  351. if (!is_write)
  352. invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
  353. return buf_len;
  354. }
  355. static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
  356. {
  357. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  358. struct sata_fis_h2d *cfis = &h2d;
  359. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  360. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  361. cfis->pm_port_c = 1 << 7;
  362. cfis->command = ATA_CMD_SET_FEATURES;
  363. cfis->features = SETFEATURES_XFER;
  364. cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
  365. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
  366. }
  367. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  368. {
  369. struct ahci_ioports *pp = &uc_priv->port[port];
  370. struct sata_port_regs *port_mmio = pp->port_mmio;
  371. u32 port_status;
  372. u32 mem;
  373. int timeout = 10000000;
  374. debug("Enter start port: %d\n", port);
  375. port_status = readl(&port_mmio->ssts);
  376. debug("Port %d status: %x\n", port, port_status);
  377. if ((port_status & 0xf) != 0x03) {
  378. printf("No Link on this port!\n");
  379. return -1;
  380. }
  381. mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
  382. if (!mem) {
  383. free(pp);
  384. printf("No mem for table!\n");
  385. return -ENOMEM;
  386. }
  387. mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
  388. memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  389. /*
  390. * First item in chunk of DMA memory: 32-slot command table,
  391. * 32 bytes each in size
  392. */
  393. pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  394. debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
  395. mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
  396. /*
  397. * Second item: Received-FIS area, 256-Byte aligned
  398. */
  399. pp->rx_fis = mem;
  400. mem += AHCI_RX_FIS_SZ;
  401. /*
  402. * Third item: data area for storing a single command
  403. * and its scatter-gather table
  404. */
  405. pp->cmd_tbl = mem;
  406. debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
  407. mem += AHCI_CMD_TBL_HDR;
  408. writel_with_flush(0x00004444, &port_mmio->dmacr);
  409. pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  410. writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
  411. writel_with_flush(pp->rx_fis, &port_mmio->fb);
  412. /* Enable FRE */
  413. writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
  414. &port_mmio->cmd);
  415. /* Wait device ready */
  416. while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
  417. SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
  418. && --timeout)
  419. ;
  420. if (timeout <= 0) {
  421. debug("Device not ready for BSY, DRQ and"
  422. "ERR in TFD!\n");
  423. return -1;
  424. }
  425. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  426. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  427. PORT_CMD_START, &port_mmio->cmd);
  428. debug("Exit start port %d\n", port);
  429. return 0;
  430. }
  431. static void dwc_ahsata_print_info(struct blk_desc *pdev)
  432. {
  433. printf("SATA Device Info:\n\r");
  434. #ifdef CONFIG_SYS_64BIT_LBA
  435. printf("S/N: %s\n\rProduct model number: %s\n\r"
  436. "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
  437. pdev->product, pdev->vendor, pdev->revision, pdev->lba);
  438. #else
  439. printf("S/N: %s\n\rProduct model number: %s\n\r"
  440. "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
  441. pdev->product, pdev->vendor, pdev->revision, pdev->lba);
  442. #endif
  443. }
  444. static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
  445. {
  446. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  447. struct sata_fis_h2d *cfis = &h2d;
  448. u8 port = uc_priv->hard_port_no;
  449. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  450. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  451. cfis->pm_port_c = 0x80; /* is command */
  452. cfis->command = ATA_CMD_ID_ATA;
  453. ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
  454. READ_CMD);
  455. ata_swap_buf_le16(id, ATA_ID_WORDS);
  456. }
  457. static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
  458. {
  459. uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
  460. uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
  461. debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
  462. }
  463. static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
  464. u32 blkcnt, u8 *buffer, int is_write)
  465. {
  466. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  467. struct sata_fis_h2d *cfis = &h2d;
  468. u8 port = uc_priv->hard_port_no;
  469. u32 block;
  470. block = start;
  471. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  472. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  473. cfis->pm_port_c = 0x80; /* is command */
  474. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  475. cfis->device = ATA_LBA;
  476. cfis->device |= (block >> 24) & 0xf;
  477. cfis->lba_high = (block >> 16) & 0xff;
  478. cfis->lba_mid = (block >> 8) & 0xff;
  479. cfis->lba_low = block & 0xff;
  480. cfis->sector_count = (u8)(blkcnt & 0xff);
  481. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  482. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  483. return blkcnt;
  484. else
  485. return 0;
  486. }
  487. static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
  488. {
  489. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  490. struct sata_fis_h2d *cfis = &h2d;
  491. u8 port = uc_priv->hard_port_no;
  492. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  493. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  494. cfis->pm_port_c = 0x80; /* is command */
  495. cfis->command = ATA_CMD_FLUSH;
  496. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  497. }
  498. static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
  499. lbaint_t blkcnt, u8 *buffer, int is_write)
  500. {
  501. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  502. struct sata_fis_h2d *cfis = &h2d;
  503. u8 port = uc_priv->hard_port_no;
  504. u64 block;
  505. block = (u64)start;
  506. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  507. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  508. cfis->pm_port_c = 0x80; /* is command */
  509. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  510. : ATA_CMD_READ_EXT;
  511. cfis->lba_high_exp = (block >> 40) & 0xff;
  512. cfis->lba_mid_exp = (block >> 32) & 0xff;
  513. cfis->lba_low_exp = (block >> 24) & 0xff;
  514. cfis->lba_high = (block >> 16) & 0xff;
  515. cfis->lba_mid = (block >> 8) & 0xff;
  516. cfis->lba_low = block & 0xff;
  517. cfis->device = ATA_LBA;
  518. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  519. cfis->sector_count = blkcnt & 0xff;
  520. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  521. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  522. return blkcnt;
  523. else
  524. return 0;
  525. }
  526. static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
  527. {
  528. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  529. struct sata_fis_h2d *cfis = &h2d;
  530. u8 port = uc_priv->hard_port_no;
  531. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  532. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  533. cfis->pm_port_c = 0x80; /* is command */
  534. cfis->command = ATA_CMD_FLUSH_EXT;
  535. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  536. }
  537. static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
  538. {
  539. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  540. uc_priv->flags |= SATA_FLAG_WCACHE;
  541. if (ata_id_has_flush(id))
  542. uc_priv->flags |= SATA_FLAG_FLUSH;
  543. if (ata_id_has_flush_ext(id))
  544. uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
  545. }
  546. static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
  547. lbaint_t blkcnt, const void *buffer,
  548. int is_write)
  549. {
  550. u32 start, blks;
  551. u8 *addr;
  552. int max_blks;
  553. start = blknr;
  554. blks = blkcnt;
  555. addr = (u8 *)buffer;
  556. max_blks = ATA_MAX_SECTORS_LBA48;
  557. do {
  558. if (blks > max_blks) {
  559. if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
  560. max_blks, addr,
  561. is_write))
  562. return 0;
  563. start += max_blks;
  564. blks -= max_blks;
  565. addr += ATA_SECT_SIZE * max_blks;
  566. } else {
  567. if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
  568. addr, is_write))
  569. return 0;
  570. start += blks;
  571. blks = 0;
  572. addr += ATA_SECT_SIZE * blks;
  573. }
  574. } while (blks != 0);
  575. return blkcnt;
  576. }
  577. static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
  578. lbaint_t blkcnt, const void *buffer,
  579. int is_write)
  580. {
  581. u32 start, blks;
  582. u8 *addr;
  583. int max_blks;
  584. start = blknr;
  585. blks = blkcnt;
  586. addr = (u8 *)buffer;
  587. max_blks = ATA_MAX_SECTORS;
  588. do {
  589. if (blks > max_blks) {
  590. if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
  591. max_blks, addr,
  592. is_write))
  593. return 0;
  594. start += max_blks;
  595. blks -= max_blks;
  596. addr += ATA_SECT_SIZE * max_blks;
  597. } else {
  598. if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
  599. addr, is_write))
  600. return 0;
  601. start += blks;
  602. blks = 0;
  603. addr += ATA_SECT_SIZE * blks;
  604. }
  605. } while (blks != 0);
  606. return blkcnt;
  607. }
  608. static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
  609. {
  610. u32 linkmap;
  611. int i;
  612. linkmap = uc_priv->link_port_map;
  613. if (0 == linkmap) {
  614. printf("No port device detected!\n");
  615. return -ENXIO;
  616. }
  617. for (i = 0; i < uc_priv->n_ports; i++) {
  618. if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
  619. if (ahci_port_start(uc_priv, (u8)i)) {
  620. printf("Can not start port %d\n", i);
  621. return 1;
  622. }
  623. uc_priv->hard_port_no = i;
  624. break;
  625. }
  626. }
  627. return 0;
  628. }
  629. static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
  630. struct blk_desc *pdev)
  631. {
  632. u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
  633. u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
  634. u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
  635. u64 n_sectors;
  636. u8 port = uc_priv->hard_port_no;
  637. ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
  638. /* Identify device to get information */
  639. dwc_ahsata_identify(uc_priv, id);
  640. /* Serial number */
  641. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  642. memcpy(pdev->product, serial, sizeof(serial));
  643. /* Firmware version */
  644. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  645. memcpy(pdev->revision, firmware, sizeof(firmware));
  646. /* Product model */
  647. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  648. memcpy(pdev->vendor, product, sizeof(product));
  649. /* Totoal sectors */
  650. n_sectors = ata_id_n_sectors(id);
  651. pdev->lba = (u32)n_sectors;
  652. pdev->type = DEV_TYPE_HARDDISK;
  653. pdev->blksz = ATA_SECT_SIZE;
  654. pdev->lun = 0;
  655. /* Check if support LBA48 */
  656. if (ata_id_has_lba48(id)) {
  657. pdev->lba48 = 1;
  658. debug("Device support LBA48\n\r");
  659. }
  660. /* Get the NCQ queue depth from device */
  661. uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
  662. uc_priv->flags |= ata_id_queue_depth(id);
  663. /* Get the xfer mode from device */
  664. dwc_ahsata_xfer_mode(uc_priv, id);
  665. /* Get the write cache status from device */
  666. dwc_ahsata_init_wcache(uc_priv, id);
  667. /* Set the xfer mode to highest speed */
  668. ahci_set_feature(uc_priv, port);
  669. dwc_ahsata_print_info(pdev);
  670. return 0;
  671. }
  672. /*
  673. * SATA interface between low level driver and command layer
  674. */
  675. static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
  676. struct blk_desc *desc, ulong blknr,
  677. lbaint_t blkcnt, void *buffer)
  678. {
  679. u32 rc;
  680. if (desc->lba48)
  681. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  682. READ_CMD);
  683. else
  684. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  685. READ_CMD);
  686. return rc;
  687. }
  688. static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
  689. struct blk_desc *desc, ulong blknr,
  690. lbaint_t blkcnt, const void *buffer)
  691. {
  692. u32 rc;
  693. u32 flags = uc_priv->flags;
  694. if (desc->lba48) {
  695. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  696. WRITE_CMD);
  697. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
  698. dwc_ahsata_flush_cache_ext(uc_priv);
  699. } else {
  700. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  701. WRITE_CMD);
  702. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
  703. dwc_ahsata_flush_cache(uc_priv);
  704. }
  705. return rc;
  706. }
  707. static int ahci_init_one(int pdev)
  708. {
  709. int rc;
  710. struct ahci_uc_priv *uc_priv = NULL;
  711. uc_priv = malloc(sizeof(struct ahci_uc_priv));
  712. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  713. uc_priv->dev = pdev;
  714. uc_priv->host_flags = ATA_FLAG_SATA
  715. | ATA_FLAG_NO_LEGACY
  716. | ATA_FLAG_MMIO
  717. | ATA_FLAG_PIO_DMA
  718. | ATA_FLAG_NO_ATAPI;
  719. uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
  720. /* initialize adapter */
  721. rc = ahci_host_init(uc_priv);
  722. if (rc)
  723. goto err_out;
  724. ahci_print_info(uc_priv);
  725. /* Save the uc_private struct to block device struct */
  726. sata_dev_desc[pdev].priv = uc_priv;
  727. return 0;
  728. err_out:
  729. return rc;
  730. }
  731. int init_sata(int dev)
  732. {
  733. struct ahci_uc_priv *uc_priv = NULL;
  734. #if defined(CONFIG_MX6)
  735. if (!is_mx6dq() && !is_mx6dqp())
  736. return 1;
  737. #endif
  738. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  739. printf("The sata index %d is out of ranges\n\r", dev);
  740. return -1;
  741. }
  742. ahci_init_one(dev);
  743. uc_priv = sata_dev_desc[dev].priv;
  744. return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
  745. }
  746. int reset_sata(int dev)
  747. {
  748. struct ahci_uc_priv *uc_priv;
  749. struct sata_host_regs *host_mmio;
  750. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  751. printf("The sata index %d is out of ranges\n\r", dev);
  752. return -1;
  753. }
  754. uc_priv = sata_dev_desc[dev].priv;
  755. if (NULL == uc_priv)
  756. /* not initialized, so nothing to reset */
  757. return 0;
  758. host_mmio = uc_priv->mmio_base;
  759. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  760. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  761. udelay(100);
  762. return 0;
  763. }
  764. int sata_port_status(int dev, int port)
  765. {
  766. struct sata_port_regs *port_mmio;
  767. struct ahci_uc_priv *uc_priv = NULL;
  768. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
  769. return -EINVAL;
  770. if (sata_dev_desc[dev].priv == NULL)
  771. return -ENODEV;
  772. uc_priv = sata_dev_desc[dev].priv;
  773. port_mmio = uc_priv->port[port].port_mmio;
  774. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
  775. }
  776. /*
  777. * SATA interface between low level driver and command layer
  778. */
  779. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  780. {
  781. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  782. return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  783. buffer);
  784. }
  785. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  786. {
  787. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  788. return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  789. buffer);
  790. }
  791. int scan_sata(int dev)
  792. {
  793. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  794. struct blk_desc *pdev = &sata_dev_desc[dev];
  795. return dwc_ahsata_scan_common(uc_priv, pdev);
  796. }