atngw100mkii.c 3.0 KB

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  1. /*
  2. * Copyright (C) 2010 Atmel Corporation
  3. *
  4. * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <spi.h>
  10. #include <netdev.h>
  11. #include <asm/io.h>
  12. #include <asm/sdram.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/arch/hmatrix.h>
  16. #include <asm/arch/mmu.h>
  17. #include <asm/arch/portmux.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  20. {
  21. /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
  22. .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
  23. .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
  24. .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
  25. | MMU_VMR_CACHE_NONE,
  26. }, {
  27. /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
  28. .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
  29. .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
  30. .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
  31. | MMU_VMR_CACHE_NONE,
  32. }, {
  33. /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
  34. .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
  35. .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
  36. .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
  37. | MMU_VMR_CACHE_WRBACK,
  38. },
  39. };
  40. static const struct sdram_config sdram_config = {
  41. .data_bits = SDRAM_DATA_32BIT,
  42. .row_bits = 13,
  43. .col_bits = 10,
  44. .bank_bits = 2,
  45. .cas = 3,
  46. .twr = 2,
  47. .trc = 7,
  48. .trp = 2,
  49. .trcd = 2,
  50. .tras = 5,
  51. .txsr = 6,
  52. /* 7.81 us */
  53. .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  54. };
  55. int board_early_init_f(void)
  56. {
  57. /* Enable SDRAM in the EBI mux */
  58. hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
  59. | HMATRIX_BIT(EBI_NAND_ENABLE));
  60. portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
  61. PORTMUX_DRIVE_HIGH);
  62. portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
  63. PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
  64. | PORTMUX_DRIVE_MIN);
  65. sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
  66. portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  67. #if defined(CONFIG_MACB)
  68. portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  69. portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  70. #endif
  71. #if defined(CONFIG_MMC)
  72. portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  73. #endif
  74. #if defined(CONFIG_ATMEL_SPI)
  75. portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
  76. #endif
  77. return 0;
  78. }
  79. int board_early_init_r(void)
  80. {
  81. gd->bd->bi_phy_id[0] = 0x01;
  82. gd->bd->bi_phy_id[1] = 0x03;
  83. return 0;
  84. }
  85. #ifdef CONFIG_CMD_NET
  86. int board_eth_init(bd_t *bi)
  87. {
  88. macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
  89. macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
  90. return 0;
  91. }
  92. #endif
  93. /* SPI chip select control */
  94. #ifdef CONFIG_ATMEL_SPI
  95. #define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
  96. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  97. {
  98. return bus == 0 && cs == 0;
  99. }
  100. void spi_cs_activate(struct spi_slave *slave)
  101. {
  102. gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
  103. }
  104. void spi_cs_deactivate(struct spi_slave *slave)
  105. {
  106. gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
  107. }
  108. #endif /* CONFIG_ATMEL_SPI */