atngw100.c 2.4 KB

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  1. /*
  2. * Copyright (C) 2006 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/sdram.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/gpio.h>
  11. #include <asm/arch/hmatrix.h>
  12. #include <asm/arch/mmu.h>
  13. #include <asm/arch/portmux.h>
  14. #include <netdev.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  17. {
  18. .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
  19. .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
  20. .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
  21. | MMU_VMR_CACHE_NONE,
  22. }, {
  23. .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
  24. .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
  25. .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
  26. | MMU_VMR_CACHE_WRBACK,
  27. },
  28. };
  29. static const struct sdram_config sdram_config = {
  30. .data_bits = SDRAM_DATA_16BIT,
  31. .row_bits = 13,
  32. .col_bits = 9,
  33. .bank_bits = 2,
  34. .cas = 3,
  35. .twr = 2,
  36. .trc = 7,
  37. .trp = 2,
  38. .trcd = 2,
  39. .tras = 5,
  40. .txsr = 5,
  41. /* 7.81 us */
  42. .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  43. };
  44. int board_early_init_f(void)
  45. {
  46. /* Enable SDRAM in the EBI mux */
  47. hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  48. portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
  49. sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
  50. portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  51. #if defined(CONFIG_MACB)
  52. portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  53. portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  54. #endif
  55. #if defined(CONFIG_MMC)
  56. portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  57. #endif
  58. #if defined(CONFIG_ATMEL_SPI)
  59. portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
  60. #endif
  61. return 0;
  62. }
  63. int board_early_init_r(void)
  64. {
  65. gd->bd->bi_phy_id[0] = 0x01;
  66. gd->bd->bi_phy_id[1] = 0x03;
  67. return 0;
  68. }
  69. #ifdef CONFIG_CMD_NET
  70. int board_eth_init(bd_t *bi)
  71. {
  72. macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
  73. macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
  74. return 0;
  75. }
  76. #endif
  77. /* SPI chip select control */
  78. #ifdef CONFIG_ATMEL_SPI
  79. #include <spi.h>
  80. #define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
  81. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  82. {
  83. return bus == 0 && cs == 0;
  84. }
  85. void spi_cs_activate(struct spi_slave *slave)
  86. {
  87. gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
  88. }
  89. void spi_cs_deactivate(struct spi_slave *slave)
  90. {
  91. gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
  92. }
  93. #endif /* CONFIG_ATMEL_SPI */