clk.h 4.0 KB

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  1. /*
  2. * Copyright (C) 2006 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __ASM_AVR32_ARCH_CLK_H__
  7. #define __ASM_AVR32_ARCH_CLK_H__
  8. #include <asm/arch/chip-features.h>
  9. #include <asm/arch/portmux.h>
  10. #ifdef CONFIG_PLL
  11. #define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
  12. * CONFIG_SYS_PLL0_MUL)
  13. #define MAIN_CLK_RATE PLL0_RATE
  14. #else
  15. #define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
  16. #endif
  17. static inline unsigned long get_cpu_clk_rate(void)
  18. {
  19. return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
  20. }
  21. static inline unsigned long get_hsb_clk_rate(void)
  22. {
  23. return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
  24. }
  25. static inline unsigned long get_pba_clk_rate(void)
  26. {
  27. return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
  28. }
  29. static inline unsigned long get_pbb_clk_rate(void)
  30. {
  31. return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
  32. }
  33. /* Accessors for specific devices. More will be added as needed. */
  34. static inline unsigned long get_sdram_clk_rate(void)
  35. {
  36. return get_hsb_clk_rate();
  37. }
  38. #ifdef AT32AP700x_CHIP_HAS_USART
  39. static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
  40. {
  41. return get_pba_clk_rate();
  42. }
  43. #endif
  44. #ifdef AT32AP700x_CHIP_HAS_MACB
  45. static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
  46. {
  47. return get_pbb_clk_rate();
  48. }
  49. static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
  50. {
  51. return get_hsb_clk_rate();
  52. }
  53. #endif
  54. #ifdef AT32AP700x_CHIP_HAS_MMCI
  55. static inline unsigned long get_mci_clk_rate(void)
  56. {
  57. return get_pbb_clk_rate();
  58. }
  59. #endif
  60. #ifdef AT32AP700x_CHIP_HAS_SPI
  61. static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
  62. {
  63. return get_pba_clk_rate();
  64. }
  65. #endif
  66. #ifdef AT32AP700x_CHIP_HAS_LCDC
  67. static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
  68. {
  69. return get_hsb_clk_rate();
  70. }
  71. #endif
  72. extern void clk_init(void);
  73. /* Board code may need the SDRAM base clock as a compile-time constant */
  74. #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
  75. /* Generic clock control */
  76. enum gclk_parent {
  77. GCLK_PARENT_OSC0 = 0,
  78. GCLK_PARENT_OSC1 = 1,
  79. GCLK_PARENT_PLL0 = 2,
  80. GCLK_PARENT_PLL1 = 3,
  81. };
  82. /* Some generic clocks have specific roles */
  83. #define GCLK_DAC_SAMPLE_CLK 6
  84. #define GCLK_LCDC_PIXCLK 7
  85. extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
  86. unsigned long rate, unsigned long parent_rate);
  87. /**
  88. * gclk_set_rate - configure and enable a generic clock
  89. * @id: Which GCLK[id] to enable
  90. * @parent: Parent clock feeding the GCLK
  91. * @rate: Target rate of the GCLK in Hz
  92. *
  93. * Returns the actual GCLK rate in Hz, after rounding to the nearest
  94. * supported rate.
  95. *
  96. * All three parameters are usually constant, hence the inline.
  97. */
  98. static inline unsigned long gclk_set_rate(unsigned int id,
  99. enum gclk_parent parent, unsigned long rate)
  100. {
  101. unsigned long parent_rate;
  102. if (id > 7)
  103. return 0;
  104. switch (parent) {
  105. case GCLK_PARENT_OSC0:
  106. parent_rate = CONFIG_SYS_OSC0_HZ;
  107. break;
  108. #ifdef CONFIG_SYS_OSC1_HZ
  109. case GCLK_PARENT_OSC1:
  110. parent_rate = CONFIG_SYS_OSC1_HZ;
  111. break;
  112. #endif
  113. #ifdef PLL0_RATE
  114. case GCLK_PARENT_PLL0:
  115. parent_rate = PLL0_RATE;
  116. break;
  117. #endif
  118. #ifdef PLL1_RATE
  119. case GCLK_PARENT_PLL1:
  120. parent_rate = PLL1_RATE;
  121. break;
  122. #endif
  123. default:
  124. parent_rate = 0;
  125. break;
  126. }
  127. return __gclk_set_rate(id, parent, rate, parent_rate);
  128. }
  129. /**
  130. * gclk_enable_output - enable output on a GCLK pin
  131. * @id: Which GCLK[id] pin to enable
  132. * @drive_strength: Drive strength of external GCLK pin, if applicable
  133. */
  134. static inline void gclk_enable_output(unsigned int id,
  135. unsigned long drive_strength)
  136. {
  137. switch (id) {
  138. case 0:
  139. portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
  140. PORTMUX_FUNC_A, drive_strength);
  141. break;
  142. case 1:
  143. portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
  144. PORTMUX_FUNC_A, drive_strength);
  145. break;
  146. case 2:
  147. portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
  148. PORTMUX_FUNC_A, drive_strength);
  149. break;
  150. case 3:
  151. portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
  152. PORTMUX_FUNC_A, drive_strength);
  153. break;
  154. case 4:
  155. portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
  156. PORTMUX_FUNC_A, drive_strength);
  157. break;
  158. }
  159. }
  160. #endif /* __ASM_AVR32_ARCH_CLK_H__ */