hsmc3.h 3.6 KB

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  1. /*
  2. * Register definitions for Static Memory Controller
  3. */
  4. #ifndef __CPU_AT32AP_HSMC3_H__
  5. #define __CPU_AT32AP_HSMC3_H__
  6. /* HSMC3 register offsets */
  7. #define HSMC3_SETUP0 0x0000
  8. #define HSMC3_PULSE0 0x0004
  9. #define HSMC3_CYCLE0 0x0008
  10. #define HSMC3_MODE0 0x000c
  11. #define HSMC3_SETUP1 0x0010
  12. #define HSMC3_PULSE1 0x0014
  13. #define HSMC3_CYCLE1 0x0018
  14. #define HSMC3_MODE1 0x001c
  15. #define HSMC3_SETUP2 0x0020
  16. #define HSMC3_PULSE2 0x0024
  17. #define HSMC3_CYCLE2 0x0028
  18. #define HSMC3_MODE2 0x002c
  19. #define HSMC3_SETUP3 0x0030
  20. #define HSMC3_PULSE3 0x0034
  21. #define HSMC3_CYCLE3 0x0038
  22. #define HSMC3_MODE3 0x003c
  23. #define HSMC3_SETUP4 0x0040
  24. #define HSMC3_PULSE4 0x0044
  25. #define HSMC3_CYCLE4 0x0048
  26. #define HSMC3_MODE4 0x004c
  27. #define HSMC3_SETUP5 0x0050
  28. #define HSMC3_PULSE5 0x0054
  29. #define HSMC3_CYCLE5 0x0058
  30. #define HSMC3_MODE5 0x005c
  31. /* Bitfields in SETUP0 */
  32. #define HSMC3_NWE_SETUP_OFFSET 0
  33. #define HSMC3_NWE_SETUP_SIZE 6
  34. #define HSMC3_NCS_WR_SETUP_OFFSET 8
  35. #define HSMC3_NCS_WR_SETUP_SIZE 6
  36. #define HSMC3_NRD_SETUP_OFFSET 16
  37. #define HSMC3_NRD_SETUP_SIZE 6
  38. #define HSMC3_NCS_RD_SETUP_OFFSET 24
  39. #define HSMC3_NCS_RD_SETUP_SIZE 6
  40. /* Bitfields in PULSE0 */
  41. #define HSMC3_NWE_PULSE_OFFSET 0
  42. #define HSMC3_NWE_PULSE_SIZE 7
  43. #define HSMC3_NCS_WR_PULSE_OFFSET 8
  44. #define HSMC3_NCS_WR_PULSE_SIZE 7
  45. #define HSMC3_NRD_PULSE_OFFSET 16
  46. #define HSMC3_NRD_PULSE_SIZE 7
  47. #define HSMC3_NCS_RD_PULSE_OFFSET 24
  48. #define HSMC3_NCS_RD_PULSE_SIZE 7
  49. /* Bitfields in CYCLE0 */
  50. #define HSMC3_NWE_CYCLE_OFFSET 0
  51. #define HSMC3_NWE_CYCLE_SIZE 9
  52. #define HSMC3_NRD_CYCLE_OFFSET 16
  53. #define HSMC3_NRD_CYCLE_SIZE 9
  54. /* Bitfields in MODE0 */
  55. #define HSMC3_READ_MODE_OFFSET 0
  56. #define HSMC3_READ_MODE_SIZE 1
  57. #define HSMC3_WRITE_MODE_OFFSET 1
  58. #define HSMC3_WRITE_MODE_SIZE 1
  59. #define HSMC3_EXNW_MODE_OFFSET 4
  60. #define HSMC3_EXNW_MODE_SIZE 2
  61. #define HSMC3_BAT_OFFSET 8
  62. #define HSMC3_BAT_SIZE 1
  63. #define HSMC3_DBW_OFFSET 12
  64. #define HSMC3_DBW_SIZE 2
  65. #define HSMC3_TDF_CYCLES_OFFSET 16
  66. #define HSMC3_TDF_CYCLES_SIZE 4
  67. #define HSMC3_TDF_MODE_OFFSET 20
  68. #define HSMC3_TDF_MODE_SIZE 1
  69. #define HSMC3_PMEN_OFFSET 24
  70. #define HSMC3_PMEN_SIZE 1
  71. #define HSMC3_PS_OFFSET 28
  72. #define HSMC3_PS_SIZE 2
  73. /* Bitfields in MODE1 */
  74. #define HSMC3_PD_OFFSET 28
  75. #define HSMC3_PD_SIZE 2
  76. /* Constants for READ_MODE */
  77. #define HSMC3_READ_MODE_NCS_CONTROLLED 0
  78. #define HSMC3_READ_MODE_NRD_CONTROLLED 1
  79. /* Constants for WRITE_MODE */
  80. #define HSMC3_WRITE_MODE_NCS_CONTROLLED 0
  81. #define HSMC3_WRITE_MODE_NWE_CONTROLLED 1
  82. /* Constants for EXNW_MODE */
  83. #define HSMC3_EXNW_MODE_DISABLED 0
  84. #define HSMC3_EXNW_MODE_RESERVED 1
  85. #define HSMC3_EXNW_MODE_FROZEN 2
  86. #define HSMC3_EXNW_MODE_READY 3
  87. /* Constants for BAT */
  88. #define HSMC3_BAT_BYTE_SELECT 0
  89. #define HSMC3_BAT_BYTE_WRITE 1
  90. /* Constants for DBW */
  91. #define HSMC3_DBW_8_BITS 0
  92. #define HSMC3_DBW_16_BITS 1
  93. #define HSMC3_DBW_32_BITS 2
  94. /* Bit manipulation macros */
  95. #define HSMC3_BIT(name) \
  96. (1 << HSMC3_##name##_OFFSET)
  97. #define HSMC3_BF(name,value) \
  98. (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \
  99. << HSMC3_##name##_OFFSET)
  100. #define HSMC3_BFEXT(name,value) \
  101. (((value) >> HSMC3_##name##_OFFSET) \
  102. & ((1 << HSMC3_##name##_SIZE) - 1))
  103. #define HSMC3_BFINS(name,value,old)\
  104. (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \
  105. << HSMC3_##name##_OFFSET)) \
  106. | HSMC3_BF(name,value))
  107. /* Register access macros */
  108. #define hsmc3_readl(reg) \
  109. readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg)
  110. #define hsmc3_writel(reg,value) \
  111. writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg)
  112. #endif /* __CPU_AT32AP_HSMC3_H__ */