clk.c 2.0 KB

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  1. /*
  2. * Copyright (C) 2005-2008 Atmel Corporation
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clk.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/portmux.h>
  11. #include "sm.h"
  12. void clk_init(void)
  13. {
  14. uint32_t cksel;
  15. /* in case of soft resets, disable watchdog */
  16. sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
  17. sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
  18. #ifdef CONFIG_PLL
  19. /* Initialize the PLL */
  20. sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
  21. | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
  22. | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
  23. | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
  24. | SM_BF(PLLOSC, 0)
  25. | SM_BIT(PLLEN)));
  26. /* Wait for lock */
  27. while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
  28. #endif
  29. /* Set up clocks for the CPU and all peripheral buses */
  30. cksel = 0;
  31. if (CONFIG_SYS_CLKDIV_CPU)
  32. cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
  33. if (CONFIG_SYS_CLKDIV_HSB)
  34. cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
  35. if (CONFIG_SYS_CLKDIV_PBA)
  36. cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
  37. if (CONFIG_SYS_CLKDIV_PBB)
  38. cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
  39. sm_writel(PM_CKSEL, cksel);
  40. #ifdef CONFIG_PLL
  41. /* Use PLL0 as main clock */
  42. sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
  43. #ifdef CONFIG_LCD
  44. /* Set up pixel clock for the LCDC */
  45. sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
  46. #endif
  47. #endif
  48. }
  49. unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
  50. unsigned long rate, unsigned long parent_rate)
  51. {
  52. unsigned long divider;
  53. if (rate == 0 || parent_rate == 0) {
  54. sm_writel(PM_GCCTRL(id), 0);
  55. return 0;
  56. }
  57. divider = (parent_rate + rate / 2) / rate;
  58. if (divider <= 1) {
  59. sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
  60. rate = parent_rate;
  61. } else {
  62. divider = min(255UL, divider / 2 - 1);
  63. sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
  64. | SM_BF(DIV, divider));
  65. rate = parent_rate / (2 * (divider + 1));
  66. }
  67. return rate;
  68. }