board.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <adc.h>
  7. #include <asm/arch/stm32.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/gpio.h>
  10. #include <asm/io.h>
  11. #include <bootm.h>
  12. #include <clk.h>
  13. #include <config.h>
  14. #include <dm.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass.h>
  17. #include <env.h>
  18. #include <env_internal.h>
  19. #include <g_dnl.h>
  20. #include <generic-phy.h>
  21. #include <hang.h>
  22. #include <i2c.h>
  23. #include <i2c_eeprom.h>
  24. #include <init.h>
  25. #include <led.h>
  26. #include <memalign.h>
  27. #include <misc.h>
  28. #include <mtd.h>
  29. #include <mtd_node.h>
  30. #include <netdev.h>
  31. #include <phy.h>
  32. #include <power/regulator.h>
  33. #include <remoteproc.h>
  34. #include <reset.h>
  35. #include <syscon.h>
  36. #include <usb.h>
  37. #include <usb/dwc2_udc.h>
  38. #include <watchdog.h>
  39. /* SYSCFG registers */
  40. #define SYSCFG_BOOTR 0x00
  41. #define SYSCFG_PMCSETR 0x04
  42. #define SYSCFG_IOCTRLSETR 0x18
  43. #define SYSCFG_ICNR 0x1C
  44. #define SYSCFG_CMPCR 0x20
  45. #define SYSCFG_CMPENSETR 0x24
  46. #define SYSCFG_PMCCLRR 0x44
  47. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  48. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  49. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  50. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  51. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  52. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  53. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  54. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  55. #define SYSCFG_CMPCR_READY BIT(8)
  56. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  57. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  58. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  59. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  60. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  61. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  62. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  63. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  64. /*
  65. * Get a global data pointer
  66. */
  67. DECLARE_GLOBAL_DATA_PTR;
  68. int setup_mac_address(void)
  69. {
  70. unsigned char enetaddr[6];
  71. struct udevice *dev;
  72. int off, ret;
  73. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  74. if (ret) /* ethaddr is already set */
  75. return 0;
  76. off = fdt_path_offset(gd->fdt_blob, "eeprom0");
  77. if (off < 0) {
  78. printf("%s: No eeprom0 path offset\n", __func__);
  79. return off;
  80. }
  81. ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
  82. if (ret) {
  83. printf("Cannot find EEPROM!\n");
  84. return ret;
  85. }
  86. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  87. if (ret) {
  88. printf("Error reading configuration EEPROM!\n");
  89. return ret;
  90. }
  91. if (is_valid_ethaddr(enetaddr))
  92. eth_env_set_enetaddr("ethaddr", enetaddr);
  93. return 0;
  94. }
  95. int checkboard(void)
  96. {
  97. char *mode;
  98. const char *fdt_compat;
  99. int fdt_compat_len;
  100. if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
  101. mode = "trusted with OP-TEE";
  102. else if (IS_ENABLED(CONFIG_TFABOOT))
  103. mode = "trusted";
  104. else
  105. mode = "basic";
  106. printf("Board: stm32mp1 in %s mode", mode);
  107. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  108. &fdt_compat_len);
  109. if (fdt_compat && fdt_compat_len)
  110. printf(" (%s)", fdt_compat);
  111. puts("\n");
  112. return 0;
  113. }
  114. #ifdef CONFIG_BOARD_EARLY_INIT_F
  115. static u8 brdcode __section("data");
  116. static u8 somcode __section("data");
  117. static void board_get_coding_straps(void)
  118. {
  119. struct gpio_desc gpio[4];
  120. ofnode node;
  121. int i, ret;
  122. node = ofnode_path("/config");
  123. if (!ofnode_valid(node)) {
  124. printf("%s: no /config node?\n", __func__);
  125. return;
  126. }
  127. brdcode = 0;
  128. somcode = 0;
  129. ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
  130. gpio, ARRAY_SIZE(gpio),
  131. GPIOD_IS_IN);
  132. for (i = 0; i < ret; i++)
  133. somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  134. ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
  135. gpio, ARRAY_SIZE(gpio),
  136. GPIOD_IS_IN);
  137. for (i = 0; i < ret; i++)
  138. brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  139. printf("Code: SoM:rev=%d Board:rev=%d\n", somcode, brdcode);
  140. }
  141. int board_early_init_f(void)
  142. {
  143. board_get_coding_straps();
  144. return 0;
  145. }
  146. #ifdef CONFIG_SPL_LOAD_FIT
  147. int board_fit_config_name_match(const char *name)
  148. {
  149. char test[20];
  150. snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
  151. if (!strcmp(name, test))
  152. return 0;
  153. return -EINVAL;
  154. }
  155. #endif
  156. #endif
  157. static void board_key_check(void)
  158. {
  159. #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
  160. ofnode node;
  161. struct gpio_desc gpio;
  162. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  163. node = ofnode_path("/config");
  164. if (!ofnode_valid(node)) {
  165. debug("%s: no /config node?\n", __func__);
  166. return;
  167. }
  168. #ifdef CONFIG_FASTBOOT
  169. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  170. &gpio, GPIOD_IS_IN)) {
  171. debug("%s: could not find a /config/st,fastboot-gpios\n",
  172. __func__);
  173. } else {
  174. if (dm_gpio_get_value(&gpio)) {
  175. puts("Fastboot key pressed, ");
  176. boot_mode = BOOT_FASTBOOT;
  177. }
  178. dm_gpio_free(NULL, &gpio);
  179. }
  180. #endif
  181. #ifdef CONFIG_CMD_STM32PROG
  182. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  183. &gpio, GPIOD_IS_IN)) {
  184. debug("%s: could not find a /config/st,stm32prog-gpios\n",
  185. __func__);
  186. } else {
  187. if (dm_gpio_get_value(&gpio)) {
  188. puts("STM32Programmer key pressed, ");
  189. boot_mode = BOOT_STM32PROG;
  190. }
  191. dm_gpio_free(NULL, &gpio);
  192. }
  193. #endif
  194. if (boot_mode != BOOT_NORMAL) {
  195. puts("entering download mode...\n");
  196. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  197. TAMP_BOOT_FORCED_MASK,
  198. boot_mode);
  199. }
  200. #endif
  201. }
  202. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  203. #include <usb/dwc2_udc.h>
  204. int g_dnl_board_usb_cable_connected(void)
  205. {
  206. struct udevice *dwc2_udc_otg;
  207. int ret;
  208. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  209. DM_GET_DRIVER(dwc2_udc_otg),
  210. &dwc2_udc_otg);
  211. if (!ret)
  212. debug("dwc2_udc_otg init failed\n");
  213. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  214. }
  215. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  216. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  217. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  218. {
  219. if (!strcmp(name, "usb_dnl_dfu"))
  220. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  221. else if (!strcmp(name, "usb_dnl_fastboot"))
  222. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  223. &dev->idProduct);
  224. else
  225. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  226. return 0;
  227. }
  228. #endif /* CONFIG_USB_GADGET */
  229. #ifdef CONFIG_LED
  230. static int get_led(struct udevice **dev, char *led_string)
  231. {
  232. char *led_name;
  233. int ret;
  234. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  235. if (!led_name) {
  236. pr_debug("%s: could not find %s config string\n",
  237. __func__, led_string);
  238. return -ENOENT;
  239. }
  240. ret = led_get_by_label(led_name, dev);
  241. if (ret) {
  242. debug("%s: get=%d\n", __func__, ret);
  243. return ret;
  244. }
  245. return 0;
  246. }
  247. static int setup_led(enum led_state_t cmd)
  248. {
  249. struct udevice *dev;
  250. int ret;
  251. ret = get_led(&dev, "u-boot,boot-led");
  252. if (ret)
  253. return ret;
  254. ret = led_set_state(dev, cmd);
  255. return ret;
  256. }
  257. #endif
  258. static void __maybe_unused led_error_blink(u32 nb_blink)
  259. {
  260. #ifdef CONFIG_LED
  261. int ret;
  262. struct udevice *led;
  263. u32 i;
  264. #endif
  265. if (!nb_blink)
  266. return;
  267. #ifdef CONFIG_LED
  268. ret = get_led(&led, "u-boot,error-led");
  269. if (!ret) {
  270. /* make u-boot,error-led blinking */
  271. /* if U32_MAX and 125ms interval, for 17.02 years */
  272. for (i = 0; i < 2 * nb_blink; i++) {
  273. led_set_state(led, LEDST_TOGGLE);
  274. mdelay(125);
  275. WATCHDOG_RESET();
  276. }
  277. }
  278. #endif
  279. /* infinite: the boot process must be stopped */
  280. if (nb_blink == U32_MAX)
  281. hang();
  282. }
  283. static void sysconf_init(void)
  284. {
  285. #ifndef CONFIG_TFABOOT
  286. u8 *syscfg;
  287. #ifdef CONFIG_DM_REGULATOR
  288. struct udevice *pwr_dev;
  289. struct udevice *pwr_reg;
  290. struct udevice *dev;
  291. int ret;
  292. u32 otp = 0;
  293. #endif
  294. u32 bootr;
  295. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  296. /* interconnect update : select master using the port 1 */
  297. /* LTDC = AXI_M9 */
  298. /* GPU = AXI_M8 */
  299. /* today information is hardcoded in U-Boot */
  300. writel(BIT(9), syscfg + SYSCFG_ICNR);
  301. /* disable Pull-Down for boot pin connected to VDD */
  302. bootr = readl(syscfg + SYSCFG_BOOTR);
  303. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  304. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  305. writel(bootr, syscfg + SYSCFG_BOOTR);
  306. #ifdef CONFIG_DM_REGULATOR
  307. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  308. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  309. * The customer will have to disable this for low frequencies
  310. * or if AFMUX is selected but the function not used, typically for
  311. * TRACE. Otherwise, impact on power consumption.
  312. *
  313. * WARNING:
  314. * enabling High Speed mode while VDD>2.7V
  315. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  316. * erroneously set to 1 can damage the IC!
  317. * => U-Boot set the register only if VDD < 2.7V (in DT)
  318. * but this value need to be consistent with board design
  319. */
  320. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  321. DM_GET_DRIVER(stm32mp_pwr_pmic),
  322. &pwr_dev);
  323. if (!ret) {
  324. ret = uclass_get_device_by_driver(UCLASS_MISC,
  325. DM_GET_DRIVER(stm32mp_bsec),
  326. &dev);
  327. if (ret) {
  328. pr_err("Can't find stm32mp_bsec driver\n");
  329. return;
  330. }
  331. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  332. if (ret > 0)
  333. otp = otp & BIT(13);
  334. /* get VDD = vdd-supply */
  335. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  336. &pwr_reg);
  337. /* check if VDD is Low Voltage */
  338. if (!ret) {
  339. if (regulator_get_value(pwr_reg) < 2700000) {
  340. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  341. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  342. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  343. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  344. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  345. syscfg + SYSCFG_IOCTRLSETR);
  346. if (!otp)
  347. pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  348. } else {
  349. if (otp)
  350. pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  351. }
  352. } else {
  353. debug("VDD unknown");
  354. }
  355. }
  356. #endif
  357. /* activate automatic I/O compensation
  358. * warning: need to ensure CSI enabled and ready in clock driver
  359. */
  360. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  361. while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
  362. ;
  363. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  364. #endif
  365. }
  366. static void board_init_fmc2(void)
  367. {
  368. #define STM32_FMC2_BCR1 0x0
  369. #define STM32_FMC2_BTR1 0x4
  370. #define STM32_FMC2_BWTR1 0x104
  371. #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
  372. #define STM32_FMC2_BCRx_FMCEN BIT(31)
  373. #define STM32_FMC2_BCRx_WREN BIT(12)
  374. #define STM32_FMC2_BCRx_RSVD BIT(7)
  375. #define STM32_FMC2_BCRx_FACCEN BIT(6)
  376. #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
  377. #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
  378. #define STM32_FMC2_BCRx_MUXEN BIT(1)
  379. #define STM32_FMC2_BCRx_MBKEN BIT(0)
  380. #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
  381. #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
  382. #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
  383. #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
  384. #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
  385. #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
  386. #define RCC_MP_AHB6RSTCLRR 0x218
  387. #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
  388. #define RCC_MP_AHB6ENSETR 0x19c
  389. #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
  390. const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
  391. STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
  392. STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
  393. STM32_FMC2_BCRx_MBKEN;
  394. const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
  395. STM32_FMC2_BTRx_BUSTURN(2) |
  396. STM32_FMC2_BTRx_DATAST(0x22) |
  397. STM32_FMC2_BTRx_ADDHLD(2) |
  398. STM32_FMC2_BTRx_ADDSET(2);
  399. /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
  400. writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
  401. writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
  402. /* KS8851-16MLL -- Muxed mode */
  403. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
  404. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
  405. /* AS7C34098 SRAM on X11 -- Muxed mode */
  406. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
  407. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
  408. setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
  409. }
  410. /* board dependent setup after realloc */
  411. int board_init(void)
  412. {
  413. struct udevice *dev;
  414. /* address of boot parameters */
  415. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  416. /* probe all PINCTRL for hog */
  417. for (uclass_first_device(UCLASS_PINCTRL, &dev);
  418. dev;
  419. uclass_next_device(&dev)) {
  420. pr_debug("probe pincontrol = %s\n", dev->name);
  421. }
  422. board_key_check();
  423. #ifdef CONFIG_DM_REGULATOR
  424. regulators_enable_boot_on(_DEBUG);
  425. #endif
  426. sysconf_init();
  427. board_init_fmc2();
  428. if (CONFIG_IS_ENABLED(LED))
  429. led_default_state();
  430. return 0;
  431. }
  432. int board_late_init(void)
  433. {
  434. char *boot_device;
  435. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  436. const void *fdt_compat;
  437. int fdt_compat_len;
  438. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  439. &fdt_compat_len);
  440. if (fdt_compat && fdt_compat_len) {
  441. if (strncmp(fdt_compat, "st,", 3) != 0)
  442. env_set("board_name", fdt_compat);
  443. else
  444. env_set("board_name", fdt_compat + 3);
  445. }
  446. #endif
  447. /* Check the boot-source to disable bootdelay */
  448. boot_device = env_get("boot_device");
  449. if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
  450. env_set("bootdelay", "0");
  451. #ifdef CONFIG_BOARD_EARLY_INIT_F
  452. env_set_ulong("dh_som_rev", somcode);
  453. env_set_ulong("dh_board_rev", brdcode);
  454. #endif
  455. return 0;
  456. }
  457. void board_quiesce_devices(void)
  458. {
  459. #ifdef CONFIG_LED
  460. setup_led(LEDST_OFF);
  461. #endif
  462. }
  463. /* eth init function : weak called in eqos driver */
  464. int board_interface_eth_init(struct udevice *dev,
  465. phy_interface_t interface_type)
  466. {
  467. u8 *syscfg;
  468. u32 value;
  469. bool eth_clk_sel_reg = false;
  470. bool eth_ref_clk_sel_reg = false;
  471. /* Gigabit Ethernet 125MHz clock selection. */
  472. eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  473. /* Ethernet 50Mhz RMII clock selection */
  474. eth_ref_clk_sel_reg =
  475. dev_read_bool(dev, "st,eth_ref_clk_sel");
  476. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  477. if (!syscfg)
  478. return -ENODEV;
  479. switch (interface_type) {
  480. case PHY_INTERFACE_MODE_MII:
  481. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  482. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  483. debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  484. break;
  485. case PHY_INTERFACE_MODE_GMII:
  486. if (eth_clk_sel_reg)
  487. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  488. SYSCFG_PMCSETR_ETH_CLK_SEL;
  489. else
  490. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  491. debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  492. break;
  493. case PHY_INTERFACE_MODE_RMII:
  494. if (eth_ref_clk_sel_reg)
  495. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  496. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  497. else
  498. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  499. debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  500. break;
  501. case PHY_INTERFACE_MODE_RGMII:
  502. case PHY_INTERFACE_MODE_RGMII_ID:
  503. case PHY_INTERFACE_MODE_RGMII_RXID:
  504. case PHY_INTERFACE_MODE_RGMII_TXID:
  505. if (eth_clk_sel_reg)
  506. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  507. SYSCFG_PMCSETR_ETH_CLK_SEL;
  508. else
  509. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  510. debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  511. break;
  512. default:
  513. debug("%s: Do not manage %d interface\n",
  514. __func__, interface_type);
  515. /* Do not manage others interfaces */
  516. return -EINVAL;
  517. }
  518. /* clear and set ETH configuration bits */
  519. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  520. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  521. syscfg + SYSCFG_PMCCLRR);
  522. writel(value, syscfg + SYSCFG_PMCSETR);
  523. return 0;
  524. }
  525. enum env_location env_get_location(enum env_operation op, int prio)
  526. {
  527. if (prio)
  528. return ENVL_UNKNOWN;
  529. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  530. return ENVL_SPI_FLASH;
  531. #else
  532. return ENVL_NOWHERE;
  533. #endif
  534. }
  535. #ifdef CONFIG_SYS_MTDPARTS_RUNTIME
  536. #define MTDPARTS_LEN 256
  537. #define MTDIDS_LEN 128
  538. /**
  539. * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long.
  540. * If we need to access it before the env is relocated, then we need
  541. * to use our own stack buffer. gd->env_buf will be too small.
  542. *
  543. * @param buf temporary buffer pointer MTDPARTS_LEN long
  544. * @return mtdparts variable string, NULL if not found
  545. */
  546. static const char *env_get_mtdparts(const char *str, char *buf)
  547. {
  548. if (gd->flags & GD_FLG_ENV_READY)
  549. return env_get(str);
  550. if (env_get_f(str, buf, MTDPARTS_LEN) != -1)
  551. return buf;
  552. return NULL;
  553. }
  554. /**
  555. * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev>
  556. */
  557. static void board_get_mtdparts(const char *dev,
  558. char *mtdids,
  559. char *mtdparts)
  560. {
  561. char env_name[32] = "mtdparts_";
  562. char tmp_mtdparts[MTDPARTS_LEN];
  563. const char *tmp;
  564. /* name of env variable to read = mtdparts_<dev> */
  565. strcat(env_name, dev);
  566. tmp = env_get_mtdparts(env_name, tmp_mtdparts);
  567. if (tmp) {
  568. /* mtdids: "<dev>=<dev>, ...." */
  569. if (mtdids[0] != '\0')
  570. strcat(mtdids, ",");
  571. strcat(mtdids, dev);
  572. strcat(mtdids, "=");
  573. strcat(mtdids, dev);
  574. /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
  575. if (mtdparts[0] != '\0')
  576. strncat(mtdparts, ";", MTDPARTS_LEN);
  577. else
  578. strcat(mtdparts, "mtdparts=");
  579. strncat(mtdparts, dev, MTDPARTS_LEN);
  580. strncat(mtdparts, ":", MTDPARTS_LEN);
  581. strncat(mtdparts, tmp, MTDPARTS_LEN);
  582. }
  583. }
  584. void board_mtdparts_default(const char **mtdids, const char **mtdparts)
  585. {
  586. struct udevice *dev;
  587. static char parts[3 * MTDPARTS_LEN + 1];
  588. static char ids[MTDIDS_LEN + 1];
  589. static bool mtd_initialized;
  590. if (mtd_initialized) {
  591. *mtdids = ids;
  592. *mtdparts = parts;
  593. return;
  594. }
  595. memset(parts, 0, sizeof(parts));
  596. memset(ids, 0, sizeof(ids));
  597. /* probe all MTD devices */
  598. for (uclass_first_device(UCLASS_MTD, &dev);
  599. dev;
  600. uclass_next_device(&dev)) {
  601. pr_debug("mtd device = %s\n", dev->name);
  602. }
  603. if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
  604. board_get_mtdparts("nor0", ids, parts);
  605. mtd_initialized = true;
  606. *mtdids = ids;
  607. *mtdparts = parts;
  608. debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
  609. }
  610. #endif
  611. #if defined(CONFIG_OF_BOARD_SETUP)
  612. int ft_board_setup(void *blob, bd_t *bd)
  613. {
  614. return 0;
  615. }
  616. #endif
  617. #ifdef CONFIG_SET_DFU_ALT_INFO
  618. #define DFU_ALT_BUF_LEN SZ_1K
  619. static void board_get_alt_info(const char *dev, char *buff)
  620. {
  621. char var_name[32] = "dfu_alt_info_";
  622. int ret;
  623. ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN);
  624. /* name of env variable to read = dfu_alt_info_<dev> */
  625. strcat(var_name, dev);
  626. ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN);
  627. if (ret) {
  628. if (buff[0] != '\0')
  629. strcat(buff, "&");
  630. strncat(buff, tmp_alt, DFU_ALT_BUF_LEN);
  631. }
  632. }
  633. void set_dfu_alt_info(char *interface, char *devstr)
  634. {
  635. struct udevice *dev;
  636. ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
  637. if (env_get("dfu_alt_info"))
  638. return;
  639. memset(buf, 0, sizeof(buf));
  640. /* probe all MTD devices */
  641. mtd_probe_devices();
  642. board_get_alt_info("ram", buf);
  643. if (!uclass_get_device(UCLASS_MMC, 0, &dev))
  644. board_get_alt_info("mmc0", buf);
  645. if (!uclass_get_device(UCLASS_MMC, 1, &dev))
  646. board_get_alt_info("mmc1", buf);
  647. if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
  648. board_get_alt_info("nor0", buf);
  649. env_set("dfu_alt_info", buf);
  650. puts("DFU alt info setting: done\n");
  651. }
  652. #endif
  653. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  654. {
  655. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  656. if (!rproc_is_initialized())
  657. if (rproc_init()) {
  658. printf("Remote Processor %d initialization failed\n",
  659. id);
  660. return;
  661. }
  662. ret = rproc_load(id, fw_image, fw_size);
  663. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  664. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  665. if (!ret) {
  666. rproc_start(id);
  667. env_set("copro_state", "booted");
  668. }
  669. }
  670. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);