stm32mp15xx-dhcor-u-boot.dtsi 2.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. *
  5. * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
  6. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. * Copyright (C) 2020 Marek Vasut <marex@denx.de>
  8. */
  9. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  10. #include "stm32mp15-u-boot.dtsi"
  11. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  12. / {
  13. u-boot,dm-pre-reloc;
  14. config {
  15. dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  16. };
  17. };
  18. &i2c4 {
  19. u-boot,dm-pre-reloc;
  20. };
  21. &i2c4_pins_a {
  22. u-boot,dm-pre-reloc;
  23. pins {
  24. u-boot,dm-pre-reloc;
  25. };
  26. };
  27. &pmic {
  28. u-boot,dm-pre-reloc;
  29. };
  30. &qspi {
  31. u-boot,dm-spl;
  32. };
  33. &rcc {
  34. st,clksrc = <
  35. CLK_MPU_PLL1P
  36. CLK_AXI_PLL2P
  37. CLK_MCU_PLL3P
  38. CLK_PLL12_HSE
  39. CLK_PLL3_HSE
  40. CLK_PLL4_HSE
  41. CLK_RTC_LSE
  42. CLK_MCO1_DISABLED
  43. CLK_MCO2_DISABLED
  44. >;
  45. st,clkdiv = <
  46. 1 /*MPU*/
  47. 0 /*AXI*/
  48. 0 /*MCU*/
  49. 1 /*APB1*/
  50. 1 /*APB2*/
  51. 1 /*APB3*/
  52. 1 /*APB4*/
  53. 2 /*APB5*/
  54. 23 /*RTC*/
  55. 0 /*MCO1*/
  56. 0 /*MCO2*/
  57. >;
  58. st,pkcs = <
  59. CLK_CKPER_HSE
  60. CLK_FMC_ACLK
  61. CLK_QSPI_ACLK
  62. CLK_ETH_DISABLED
  63. CLK_SDMMC12_PLL4P
  64. CLK_DSI_DSIPLL
  65. CLK_STGEN_HSE
  66. CLK_USBPHY_HSE
  67. CLK_SPI2S1_PLL3Q
  68. CLK_SPI2S23_PLL3Q
  69. CLK_SPI45_HSI
  70. CLK_SPI6_HSI
  71. CLK_I2C46_HSI
  72. CLK_SDMMC3_PLL4P
  73. CLK_USBO_USBPHY
  74. CLK_ADC_CKPER
  75. CLK_CEC_LSE
  76. CLK_I2C12_HSI
  77. CLK_I2C35_HSI
  78. CLK_UART1_HSI
  79. CLK_UART24_HSI
  80. CLK_UART35_HSI
  81. CLK_UART6_HSI
  82. CLK_UART78_HSI
  83. CLK_SPDIF_PLL4P
  84. CLK_FDCAN_PLL4R
  85. CLK_SAI1_PLL3Q
  86. CLK_SAI2_PLL3Q
  87. CLK_SAI3_PLL3Q
  88. CLK_SAI4_PLL3Q
  89. CLK_RNG1_LSI
  90. CLK_RNG2_LSI
  91. CLK_LPTIM1_PCLK1
  92. CLK_LPTIM23_PCLK3
  93. CLK_LPTIM45_LSE
  94. >;
  95. /* VCO = 1300.0 MHz => P = 650 (CPU) */
  96. pll1: st,pll@0 {
  97. compatible = "st,stm32mp1-pll";
  98. reg = <0>;
  99. cfg = < 2 80 0 0 0 PQR(1,0,0) >;
  100. frac = < 0x800 >;
  101. u-boot,dm-pre-reloc;
  102. };
  103. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  104. pll2: st,pll@1 {
  105. compatible = "st,stm32mp1-pll";
  106. reg = <1>;
  107. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  108. frac = < 0x1400 >;
  109. u-boot,dm-pre-reloc;
  110. };
  111. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  112. pll3: st,pll@2 {
  113. compatible = "st,stm32mp1-pll";
  114. reg = <2>;
  115. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  116. frac = < 0x1a04 >;
  117. u-boot,dm-pre-reloc;
  118. };
  119. /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
  120. pll4: st,pll@3 {
  121. compatible = "st,stm32mp1-pll";
  122. reg = <3>;
  123. cfg = < 1 49 5 11 5 PQR(1,1,1) >;
  124. u-boot,dm-pre-reloc;
  125. };
  126. };