p1_p2_rdb_pc.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. /*
  7. * QorIQ RDB boards configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. #include <linux/stringify.h>
  12. #if defined(CONFIG_TARGET_P1020MBG)
  13. #define CONFIG_BOARDNAME "P1020MBG-PC"
  14. #define CONFIG_VSC7385_ENET
  15. #define CONFIG_SLIC
  16. #define __SW_BOOT_MASK 0x03
  17. #define __SW_BOOT_NOR 0xe4
  18. #define __SW_BOOT_SD 0x54
  19. #define CONFIG_SYS_L2_SIZE (256 << 10)
  20. #endif
  21. #if defined(CONFIG_TARGET_P1020UTM)
  22. #define CONFIG_BOARDNAME "P1020UTM-PC"
  23. #define __SW_BOOT_MASK 0x03
  24. #define __SW_BOOT_NOR 0xe0
  25. #define __SW_BOOT_SD 0x50
  26. #define CONFIG_SYS_L2_SIZE (256 << 10)
  27. #endif
  28. #if defined(CONFIG_TARGET_P1020RDB_PC)
  29. #define CONFIG_BOARDNAME "P1020RDB-PC"
  30. #define CONFIG_NAND_FSL_ELBC
  31. #define CONFIG_VSC7385_ENET
  32. #define CONFIG_SLIC
  33. #define __SW_BOOT_MASK 0x03
  34. #define __SW_BOOT_NOR 0x5c
  35. #define __SW_BOOT_SPI 0x1c
  36. #define __SW_BOOT_SD 0x9c
  37. #define __SW_BOOT_NAND 0xec
  38. #define __SW_BOOT_PCIE 0x6c
  39. #define CONFIG_SYS_L2_SIZE (256 << 10)
  40. #endif
  41. /*
  42. * P1020RDB-PD board has user selectable switches for evaluating different
  43. * frequency and boot options for the P1020 device. The table that
  44. * follow describe the available options. The front six binary number was in
  45. * accordance with SW3[1:6].
  46. * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  47. * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  48. * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  49. * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  50. * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  51. * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  52. * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  53. */
  54. #if defined(CONFIG_TARGET_P1020RDB_PD)
  55. #define CONFIG_BOARDNAME "P1020RDB-PD"
  56. #define CONFIG_NAND_FSL_ELBC
  57. #define CONFIG_VSC7385_ENET
  58. #define CONFIG_SLIC
  59. #define __SW_BOOT_MASK 0x03
  60. #define __SW_BOOT_NOR 0x64
  61. #define __SW_BOOT_SPI 0x34
  62. #define __SW_BOOT_SD 0x24
  63. #define __SW_BOOT_NAND 0x44
  64. #define __SW_BOOT_PCIE 0x74
  65. #define CONFIG_SYS_L2_SIZE (256 << 10)
  66. /*
  67. * Dynamic MTD Partition support with mtdparts
  68. */
  69. #endif
  70. #if defined(CONFIG_TARGET_P1021RDB)
  71. #define CONFIG_BOARDNAME "P1021RDB-PC"
  72. #define CONFIG_NAND_FSL_ELBC
  73. #define CONFIG_VSC7385_ENET
  74. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  75. addresses in the LBC */
  76. #define __SW_BOOT_MASK 0x03
  77. #define __SW_BOOT_NOR 0x5c
  78. #define __SW_BOOT_SPI 0x1c
  79. #define __SW_BOOT_SD 0x9c
  80. #define __SW_BOOT_NAND 0xec
  81. #define __SW_BOOT_PCIE 0x6c
  82. #define CONFIG_SYS_L2_SIZE (256 << 10)
  83. /*
  84. * Dynamic MTD Partition support with mtdparts
  85. */
  86. #endif
  87. #if defined(CONFIG_TARGET_P1024RDB)
  88. #define CONFIG_BOARDNAME "P1024RDB"
  89. #define CONFIG_NAND_FSL_ELBC
  90. #define CONFIG_SLIC
  91. #define __SW_BOOT_MASK 0xf3
  92. #define __SW_BOOT_NOR 0x00
  93. #define __SW_BOOT_SPI 0x08
  94. #define __SW_BOOT_SD 0x04
  95. #define __SW_BOOT_NAND 0x0c
  96. #define CONFIG_SYS_L2_SIZE (256 << 10)
  97. #endif
  98. #if defined(CONFIG_TARGET_P1025RDB)
  99. #define CONFIG_BOARDNAME "P1025RDB"
  100. #define CONFIG_NAND_FSL_ELBC
  101. #define CONFIG_SLIC
  102. #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
  103. addresses in the LBC */
  104. #define __SW_BOOT_MASK 0xf3
  105. #define __SW_BOOT_NOR 0x00
  106. #define __SW_BOOT_SPI 0x08
  107. #define __SW_BOOT_SD 0x04
  108. #define __SW_BOOT_NAND 0x0c
  109. #define CONFIG_SYS_L2_SIZE (256 << 10)
  110. #endif
  111. #if defined(CONFIG_TARGET_P2020RDB)
  112. #define CONFIG_BOARDNAME "P2020RDB-PC"
  113. #define CONFIG_NAND_FSL_ELBC
  114. #define CONFIG_VSC7385_ENET
  115. #define __SW_BOOT_MASK 0x03
  116. #define __SW_BOOT_NOR 0xc8
  117. #define __SW_BOOT_SPI 0x28
  118. #define __SW_BOOT_SD 0x68 /* or 0x18 */
  119. #define __SW_BOOT_NAND 0xe8
  120. #define __SW_BOOT_PCIE 0xa8
  121. #define CONFIG_SYS_L2_SIZE (512 << 10)
  122. /*
  123. * Dynamic MTD Partition support with mtdparts
  124. */
  125. #endif
  126. #ifdef CONFIG_SDCARD
  127. #define CONFIG_SPL_FLUSH_IMAGE
  128. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  129. #define CONFIG_SPL_PAD_TO 0x20000
  130. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  131. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  132. #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
  133. #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
  134. #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
  135. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  136. #ifdef CONFIG_SPL_BUILD
  137. #define CONFIG_SPL_COMMON_INIT_DDR
  138. #endif
  139. #endif
  140. #ifdef CONFIG_SPIFLASH
  141. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  142. #define CONFIG_SPL_FLUSH_IMAGE
  143. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  144. #define CONFIG_SPL_PAD_TO 0x20000
  145. #define CONFIG_SPL_MAX_SIZE (128 * 1024)
  146. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  147. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
  148. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
  149. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
  150. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  151. #ifdef CONFIG_SPL_BUILD
  152. #define CONFIG_SPL_COMMON_INIT_DDR
  153. #endif
  154. #endif
  155. #ifdef CONFIG_MTD_RAW_NAND
  156. #ifdef CONFIG_TPL_BUILD
  157. #define CONFIG_SPL_FLUSH_IMAGE
  158. #define CONFIG_SPL_NAND_INIT
  159. #define CONFIG_SPL_COMMON_INIT_DDR
  160. #define CONFIG_SPL_MAX_SIZE (128 << 10)
  161. #define CONFIG_TPL_TEXT_BASE 0xf8f81000
  162. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  163. #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
  164. #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
  165. #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
  166. #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
  167. #elif defined(CONFIG_SPL_BUILD)
  168. #define CONFIG_SPL_INIT_MINIMAL
  169. #define CONFIG_SPL_FLUSH_IMAGE
  170. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  171. #define CONFIG_SPL_MAX_SIZE 4096
  172. #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
  173. #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
  174. #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
  175. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
  176. #endif /* not CONFIG_TPL_BUILD */
  177. #define CONFIG_SPL_PAD_TO 0x20000
  178. #define CONFIG_TPL_PAD_TO 0x20000
  179. #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  180. #endif
  181. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  182. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  183. #endif
  184. #ifndef CONFIG_SYS_MONITOR_BASE
  185. #ifdef CONFIG_TPL_BUILD
  186. #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
  187. #elif defined(CONFIG_SPL_BUILD)
  188. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  189. #else
  190. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  191. #endif
  192. #endif
  193. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  194. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  195. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  196. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  197. #define CONFIG_LBA48
  198. #if defined(CONFIG_TARGET_P2020RDB)
  199. #define CONFIG_SYS_CLK_FREQ 100000000
  200. #else
  201. #define CONFIG_SYS_CLK_FREQ 66666666
  202. #endif
  203. #define CONFIG_DDR_CLK_FREQ 66666666
  204. #define CONFIG_HWCONFIG
  205. /*
  206. * These can be toggled for performance analysis, otherwise use default.
  207. */
  208. #define CONFIG_L2_CACHE
  209. #define CONFIG_BTB
  210. #define CONFIG_ENABLE_36BIT_PHYS
  211. #define CONFIG_SYS_CCSRBAR 0xffe00000
  212. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  213. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  214. SPL code*/
  215. #ifdef CONFIG_SPL_BUILD
  216. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  217. #endif
  218. /* DDR Setup */
  219. #define CONFIG_SYS_DDR_RAW_TIMING
  220. #define CONFIG_DDR_SPD
  221. #define CONFIG_SYS_SPD_BUS_NUM 1
  222. #define SPD_EEPROM_ADDRESS 0x52
  223. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  224. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
  225. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  226. #else
  227. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
  228. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  229. #endif
  230. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  231. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  232. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  233. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  234. /* Default settings for DDR3 */
  235. #ifndef CONFIG_TARGET_P2020RDB
  236. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  237. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  238. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  239. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  240. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  241. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  242. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  243. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  244. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  245. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  246. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  247. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  248. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  249. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  250. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  251. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  252. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  253. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  254. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  255. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  256. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  257. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  258. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  259. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  260. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  261. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  262. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  263. #endif
  264. /*
  265. * Memory map
  266. *
  267. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  268. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
  269. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  270. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
  271. * (early boot only)
  272. * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
  273. * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
  274. * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
  275. * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
  276. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  277. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  278. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  279. */
  280. /*
  281. * Local Bus Definitions
  282. */
  283. #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
  284. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  285. #define CONFIG_SYS_FLASH_BASE 0xec000000
  286. #elif defined(CONFIG_TARGET_P1020UTM)
  287. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
  288. #define CONFIG_SYS_FLASH_BASE 0xee000000
  289. #else
  290. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
  291. #define CONFIG_SYS_FLASH_BASE 0xef000000
  292. #endif
  293. #ifdef CONFIG_PHYS_64BIT
  294. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  295. #else
  296. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  297. #endif
  298. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  299. | BR_PS_16 | BR_V)
  300. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  301. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  302. #define CONFIG_SYS_FLASH_QUIET_TEST
  303. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  304. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  305. #undef CONFIG_SYS_FLASH_CHECKSUM
  306. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  307. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  308. #define CONFIG_SYS_FLASH_EMPTY_INFO
  309. /* Nand Flash */
  310. #ifdef CONFIG_NAND_FSL_ELBC
  311. #define CONFIG_SYS_NAND_BASE 0xff800000
  312. #ifdef CONFIG_PHYS_64BIT
  313. #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
  314. #else
  315. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  316. #endif
  317. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  318. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  319. #if defined(CONFIG_TARGET_P1020RDB_PD)
  320. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  321. #else
  322. #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
  323. #endif
  324. #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  325. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  326. | BR_PS_8 /* Port Size = 8 bit */ \
  327. | BR_MS_FCM /* MSEL = FCM */ \
  328. | BR_V) /* valid */
  329. #if defined(CONFIG_TARGET_P1020RDB_PD)
  330. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
  331. | OR_FCM_PGS /* Large Page*/ \
  332. | OR_FCM_CSCT \
  333. | OR_FCM_CST \
  334. | OR_FCM_CHT \
  335. | OR_FCM_SCY_1 \
  336. | OR_FCM_TRLX \
  337. | OR_FCM_EHTR)
  338. #else
  339. #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
  340. | OR_FCM_CSCT \
  341. | OR_FCM_CST \
  342. | OR_FCM_CHT \
  343. | OR_FCM_SCY_1 \
  344. | OR_FCM_TRLX \
  345. | OR_FCM_EHTR)
  346. #endif
  347. #endif /* CONFIG_NAND_FSL_ELBC */
  348. #define CONFIG_SYS_INIT_RAM_LOCK
  349. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  350. #ifdef CONFIG_PHYS_64BIT
  351. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  352. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  353. /* The assembler doesn't like typecast */
  354. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  355. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  356. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  357. #else
  358. /* Initial L1 address */
  359. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  360. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  361. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  362. #endif
  363. /* Size of used area in RAM */
  364. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  365. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  366. GENERATED_GBL_DATA_SIZE)
  367. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  368. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  369. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  370. #define CONFIG_SYS_CPLD_BASE 0xffa00000
  371. #ifdef CONFIG_PHYS_64BIT
  372. #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
  373. #else
  374. #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
  375. #endif
  376. /* CPLD config size: 1Mb */
  377. #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
  378. BR_PS_8 | BR_V)
  379. #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
  380. #define CONFIG_SYS_PMC_BASE 0xff980000
  381. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  382. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  383. BR_PS_8 | BR_V)
  384. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  385. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  386. OR_GPCM_EAD)
  387. #ifdef CONFIG_MTD_RAW_NAND
  388. #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  389. #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  390. #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  391. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  392. #else
  393. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  394. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  395. #ifdef CONFIG_NAND_FSL_ELBC
  396. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  397. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  398. #endif
  399. #endif
  400. #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
  401. #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
  402. /* Vsc7385 switch */
  403. #ifdef CONFIG_VSC7385_ENET
  404. #define CONFIG_SYS_VSC7385_BASE 0xffb00000
  405. #ifdef CONFIG_PHYS_64BIT
  406. #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
  407. #else
  408. #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
  409. #endif
  410. #define CONFIG_SYS_VSC7385_BR_PRELIM \
  411. (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
  412. #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
  413. OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
  414. OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
  415. #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
  416. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
  417. /* The size of the VSC7385 firmware image */
  418. #define CONFIG_VSC7385_IMAGE_SIZE 8192
  419. #endif
  420. /*
  421. * Config the L2 Cache as L2 SRAM
  422. */
  423. #if defined(CONFIG_SPL_BUILD)
  424. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  425. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  426. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  427. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  428. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  429. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
  430. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
  431. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
  432. #if defined(CONFIG_TARGET_P2020RDB)
  433. #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
  434. #else
  435. #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
  436. #endif
  437. #elif defined(CONFIG_MTD_RAW_NAND)
  438. #ifdef CONFIG_TPL_BUILD
  439. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  440. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  441. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  442. #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
  443. #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
  444. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
  445. #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
  446. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
  447. #else
  448. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  449. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  450. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  451. #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
  452. #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  453. #endif /* CONFIG_TPL_BUILD */
  454. #endif
  455. #endif
  456. /* Serial Port - controlled on board with jumper J8
  457. * open - index 2
  458. * shorted - index 1
  459. */
  460. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  461. #define CONFIG_SYS_NS16550_SERIAL
  462. #define CONFIG_SYS_NS16550_REG_SIZE 1
  463. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  464. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  465. #define CONFIG_NS16550_MIN_FUNCTIONS
  466. #endif
  467. #define CONFIG_SYS_BAUDRATE_TABLE \
  468. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  469. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  470. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  471. /* I2C */
  472. #ifndef CONFIG_DM_I2C
  473. #define CONFIG_SYS_I2C
  474. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  475. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  476. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  477. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  478. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  479. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  480. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  481. #else
  482. #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
  483. #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
  484. #endif
  485. #define CONFIG_SYS_I2C_FSL
  486. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
  487. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  488. /*
  489. * I2C2 EEPROM
  490. */
  491. #undef CONFIG_ID_EEPROM
  492. #define CONFIG_RTC_PT7C4338
  493. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  494. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  495. /* enable read and write access to EEPROM */
  496. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  497. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  498. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  499. #if defined(CONFIG_PCI)
  500. /*
  501. * General PCI
  502. * Memory space is mapped 1-1, but I/O space must start from 0.
  503. */
  504. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  505. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  506. #ifdef CONFIG_PHYS_64BIT
  507. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  508. #else
  509. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  510. #endif
  511. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  512. #ifdef CONFIG_PHYS_64BIT
  513. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  514. #else
  515. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  516. #endif
  517. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  518. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  519. #ifdef CONFIG_PHYS_64BIT
  520. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  521. #else
  522. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  523. #endif
  524. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  525. #ifdef CONFIG_PHYS_64BIT
  526. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
  527. #else
  528. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  529. #endif
  530. #if !defined(CONFIG_DM_PCI)
  531. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  532. #define CONFIG_PCI_INDIRECT_BRIDGE
  533. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
  534. #ifdef CONFIG_PHYS_64BIT
  535. #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
  536. #else
  537. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  538. #endif
  539. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  540. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  541. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  542. #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
  543. #ifdef CONFIG_PHYS_64BIT
  544. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  545. #else
  546. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  547. #endif
  548. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  549. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  550. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  551. #endif
  552. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  553. #endif /* CONFIG_PCI */
  554. #if defined(CONFIG_TSEC_ENET)
  555. #define CONFIG_TSEC1
  556. #define CONFIG_TSEC1_NAME "eTSEC1"
  557. #define CONFIG_TSEC2
  558. #define CONFIG_TSEC2_NAME "eTSEC2"
  559. #define CONFIG_TSEC3
  560. #define CONFIG_TSEC3_NAME "eTSEC3"
  561. #define TSEC1_PHY_ADDR 2
  562. #define TSEC2_PHY_ADDR 0
  563. #define TSEC3_PHY_ADDR 1
  564. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  565. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  566. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  567. #define TSEC1_PHYIDX 0
  568. #define TSEC2_PHYIDX 0
  569. #define TSEC3_PHYIDX 0
  570. #define CONFIG_ETHPRIME "eTSEC1"
  571. #define CONFIG_HAS_ETH0
  572. #define CONFIG_HAS_ETH1
  573. #define CONFIG_HAS_ETH2
  574. #endif /* CONFIG_TSEC_ENET */
  575. #ifdef CONFIG_QE
  576. /* QE microcode/firmware address */
  577. #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
  578. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  579. #endif /* CONFIG_QE */
  580. #ifdef CONFIG_TARGET_P1025RDB
  581. /*
  582. * QE UEC ethernet configuration
  583. */
  584. #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
  585. #undef CONFIG_UEC_ETH
  586. #define CONFIG_PHY_MODE_NEED_CHANGE
  587. #define CONFIG_UEC_ETH1 /* ETH1 */
  588. #define CONFIG_HAS_ETH0
  589. #ifdef CONFIG_UEC_ETH1
  590. #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
  591. #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
  592. #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
  593. #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
  594. #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
  595. #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  596. #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
  597. #endif /* CONFIG_UEC_ETH1 */
  598. #define CONFIG_UEC_ETH5 /* ETH5 */
  599. #define CONFIG_HAS_ETH1
  600. #ifdef CONFIG_UEC_ETH5
  601. #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
  602. #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
  603. #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
  604. #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
  605. #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
  606. #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
  607. #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
  608. #endif /* CONFIG_UEC_ETH5 */
  609. #endif /* CONFIG_TARGET_P1025RDB */
  610. /*
  611. * Environment
  612. */
  613. #if defined(CONFIG_SDCARD)
  614. #define CONFIG_FSL_FIXED_MMC_LOCATION
  615. #elif defined(CONFIG_MTD_RAW_NAND)
  616. #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
  617. #ifdef CONFIG_TPL_BUILD
  618. #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
  619. #endif
  620. #elif defined(CONFIG_SYS_RAMBOOT)
  621. #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  622. #endif
  623. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  624. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  625. /*
  626. * USB
  627. */
  628. #define CONFIG_HAS_FSL_DR_USB
  629. #if defined(CONFIG_HAS_FSL_DR_USB)
  630. #ifdef CONFIG_USB_EHCI_HCD
  631. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  632. #define CONFIG_USB_EHCI_FSL
  633. #endif
  634. #endif
  635. #if defined(CONFIG_TARGET_P1020RDB_PD)
  636. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  637. #endif
  638. #ifdef CONFIG_MMC
  639. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  640. #endif
  641. #undef CONFIG_WATCHDOG /* watchdog disabled */
  642. /*
  643. * Miscellaneous configurable options
  644. */
  645. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  646. /*
  647. * For booting Linux, the board info and command line data
  648. * have to be in the first 64 MB of memory, since this is
  649. * the maximum mapped by the Linux kernel during initialization.
  650. */
  651. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  652. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  653. #if defined(CONFIG_CMD_KGDB)
  654. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  655. #endif
  656. /*
  657. * Environment Configuration
  658. */
  659. #define CONFIG_HOSTNAME "unknown"
  660. #define CONFIG_ROOTPATH "/opt/nfsroot"
  661. #define CONFIG_BOOTFILE "uImage"
  662. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  663. /* default location for tftp and bootm */
  664. #define CONFIG_LOADADDR 1000000
  665. #ifdef __SW_BOOT_NOR
  666. #define __NOR_RST_CMD \
  667. norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
  668. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  669. #endif
  670. #ifdef __SW_BOOT_SPI
  671. #define __SPI_RST_CMD \
  672. spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
  673. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  674. #endif
  675. #ifdef __SW_BOOT_SD
  676. #define __SD_RST_CMD \
  677. sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
  678. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  679. #endif
  680. #ifdef __SW_BOOT_NAND
  681. #define __NAND_RST_CMD \
  682. nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
  683. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  684. #endif
  685. #ifdef __SW_BOOT_PCIE
  686. #define __PCIE_RST_CMD \
  687. pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
  688. i2c mw 18 3 __SW_BOOT_MASK 1; reset
  689. #endif
  690. #define CONFIG_EXTRA_ENV_SETTINGS \
  691. "netdev=eth0\0" \
  692. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  693. "loadaddr=1000000\0" \
  694. "bootfile=uImage\0" \
  695. "tftpflash=tftpboot $loadaddr $uboot; " \
  696. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  697. "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  698. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  699. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  700. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  701. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
  702. "consoledev=ttyS0\0" \
  703. "ramdiskaddr=2000000\0" \
  704. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  705. "fdtaddr=1e00000\0" \
  706. "bdev=sda1\0" \
  707. "jffs2nor=mtdblock3\0" \
  708. "norbootaddr=ef080000\0" \
  709. "norfdtaddr=ef040000\0" \
  710. "jffs2nand=mtdblock9\0" \
  711. "nandbootaddr=100000\0" \
  712. "nandfdtaddr=80000\0" \
  713. "ramdisk_size=120000\0" \
  714. "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
  715. "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
  716. __stringify(__NOR_RST_CMD)"\0" \
  717. __stringify(__SPI_RST_CMD)"\0" \
  718. __stringify(__SD_RST_CMD)"\0" \
  719. __stringify(__NAND_RST_CMD)"\0" \
  720. __stringify(__PCIE_RST_CMD)"\0"
  721. #define CONFIG_NFSBOOTCOMMAND \
  722. "setenv bootargs root=/dev/nfs rw " \
  723. "nfsroot=$serverip:$rootpath " \
  724. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  725. "console=$consoledev,$baudrate $othbootargs;" \
  726. "tftp $loadaddr $bootfile;" \
  727. "tftp $fdtaddr $fdtfile;" \
  728. "bootm $loadaddr - $fdtaddr"
  729. #define CONFIG_HDBOOT \
  730. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  731. "console=$consoledev,$baudrate $othbootargs;" \
  732. "usb start;" \
  733. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  734. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  735. "bootm $loadaddr - $fdtaddr"
  736. #define CONFIG_USB_FAT_BOOT \
  737. "setenv bootargs root=/dev/ram rw " \
  738. "console=$consoledev,$baudrate $othbootargs " \
  739. "ramdisk_size=$ramdisk_size;" \
  740. "usb start;" \
  741. "fatload usb 0:2 $loadaddr $bootfile;" \
  742. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  743. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  744. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  745. #define CONFIG_USB_EXT2_BOOT \
  746. "setenv bootargs root=/dev/ram rw " \
  747. "console=$consoledev,$baudrate $othbootargs " \
  748. "ramdisk_size=$ramdisk_size;" \
  749. "usb start;" \
  750. "ext2load usb 0:4 $loadaddr $bootfile;" \
  751. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  752. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  753. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  754. #define CONFIG_NORBOOT \
  755. "setenv bootargs root=/dev/$jffs2nor rw " \
  756. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  757. "bootm $norbootaddr - $norfdtaddr"
  758. #define CONFIG_RAMBOOTCOMMAND \
  759. "setenv bootargs root=/dev/ram rw " \
  760. "console=$consoledev,$baudrate $othbootargs " \
  761. "ramdisk_size=$ramdisk_size;" \
  762. "tftp $ramdiskaddr $ramdiskfile;" \
  763. "tftp $loadaddr $bootfile;" \
  764. "tftp $fdtaddr $fdtfile;" \
  765. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  766. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  767. #endif /* __CONFIG_H */