mvpp2.c 150 KB

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  1. /*
  2. * Driver for Marvell PPv2 network controller for Armada 375 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Marcin Wojtas <mw@semihalf.com>
  7. *
  8. * U-Boot version:
  9. * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <asm/cache.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/device_compat.h>
  21. #include <dm/devres.h>
  22. #include <dm/lists.h>
  23. #include <net.h>
  24. #include <netdev.h>
  25. #include <config.h>
  26. #include <malloc.h>
  27. #include <asm/io.h>
  28. #include <linux/bitops.h>
  29. #include <linux/bug.h>
  30. #include <linux/delay.h>
  31. #include <linux/err.h>
  32. #include <linux/errno.h>
  33. #include <phy.h>
  34. #include <miiphy.h>
  35. #include <watchdog.h>
  36. #include <asm/arch/cpu.h>
  37. #include <asm/arch/soc.h>
  38. #include <linux/compat.h>
  39. #include <linux/libfdt.h>
  40. #include <linux/mbus.h>
  41. #include <asm-generic/gpio.h>
  42. #include <fdt_support.h>
  43. #include <linux/mdio.h>
  44. DECLARE_GLOBAL_DATA_PTR;
  45. #define __verify_pcpu_ptr(ptr) \
  46. do { \
  47. const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  48. (void)__vpp_verify; \
  49. } while (0)
  50. #define VERIFY_PERCPU_PTR(__p) \
  51. ({ \
  52. __verify_pcpu_ptr(__p); \
  53. (typeof(*(__p)) __kernel __force *)(__p); \
  54. })
  55. #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
  56. #define smp_processor_id() 0
  57. #define num_present_cpus() 1
  58. #define for_each_present_cpu(cpu) \
  59. for ((cpu) = 0; (cpu) < 1; (cpu)++)
  60. #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
  61. #define CONFIG_NR_CPUS 1
  62. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  63. #define WRAP (2 + ETH_HLEN + 4 + 32)
  64. #define MTU 1500
  65. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  66. /* RX Fifo Registers */
  67. #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
  68. #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
  69. #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
  70. #define MVPP2_RX_FIFO_INIT_REG 0x64
  71. /* RX DMA Top Registers */
  72. #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
  73. #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
  74. #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
  75. #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
  76. #define MVPP2_POOL_BUF_SIZE_OFFSET 5
  77. #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
  78. #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
  79. #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
  80. #define MVPP2_RXQ_POOL_SHORT_OFFS 20
  81. #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
  82. #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
  83. #define MVPP2_RXQ_POOL_LONG_OFFS 24
  84. #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
  85. #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
  86. #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
  87. #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
  88. #define MVPP2_RXQ_DISABLE_MASK BIT(31)
  89. /* Parser Registers */
  90. #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
  91. #define MVPP2_PRS_PORT_LU_MAX 0xf
  92. #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
  93. #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
  94. #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
  95. #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
  96. #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
  97. #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
  98. #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
  99. #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
  100. #define MVPP2_PRS_TCAM_IDX_REG 0x1100
  101. #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
  102. #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
  103. #define MVPP2_PRS_SRAM_IDX_REG 0x1200
  104. #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
  105. #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
  106. #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
  107. /* Classifier Registers */
  108. #define MVPP2_CLS_MODE_REG 0x1800
  109. #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
  110. #define MVPP2_CLS_PORT_WAY_REG 0x1810
  111. #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
  112. #define MVPP2_CLS_LKP_INDEX_REG 0x1814
  113. #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
  114. #define MVPP2_CLS_LKP_TBL_REG 0x1818
  115. #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
  116. #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
  117. #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
  118. #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
  119. #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
  120. #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
  121. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
  122. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
  123. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
  124. #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
  125. #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
  126. #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
  127. /* Descriptor Manager Top Registers */
  128. #define MVPP2_RXQ_NUM_REG 0x2040
  129. #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
  130. #define MVPP22_DESC_ADDR_OFFS 8
  131. #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
  132. #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
  133. #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
  134. #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
  135. #define MVPP2_RXQ_NUM_NEW_OFFSET 16
  136. #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
  137. #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
  138. #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
  139. #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
  140. #define MVPP2_RXQ_THRESH_REG 0x204c
  141. #define MVPP2_OCCUPIED_THRESH_OFFSET 0
  142. #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
  143. #define MVPP2_RXQ_INDEX_REG 0x2050
  144. #define MVPP2_TXQ_NUM_REG 0x2080
  145. #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
  146. #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
  147. #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
  148. #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
  149. #define MVPP2_TXQ_THRESH_REG 0x2094
  150. #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
  151. #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
  152. #define MVPP2_TXQ_INDEX_REG 0x2098
  153. #define MVPP2_TXQ_PREF_BUF_REG 0x209c
  154. #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
  155. #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
  156. #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
  157. #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
  158. #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
  159. #define MVPP2_TXQ_PENDING_REG 0x20a0
  160. #define MVPP2_TXQ_PENDING_MASK 0x3fff
  161. #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
  162. #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
  163. #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
  164. #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
  165. #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
  166. #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
  167. #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
  168. #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
  169. #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
  170. #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
  171. #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
  172. #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
  173. #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
  174. #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
  175. #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
  176. #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
  177. #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
  178. /* MBUS bridge registers */
  179. #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
  180. #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
  181. #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
  182. #define MVPP2_BASE_ADDR_ENABLE 0x4060
  183. /* AXI Bridge Registers */
  184. #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
  185. #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
  186. #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
  187. #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
  188. #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
  189. #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
  190. #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
  191. #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
  192. #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
  193. #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
  194. #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
  195. #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
  196. /* Values for AXI Bridge registers */
  197. #define MVPP22_AXI_ATTR_CACHE_OFFS 0
  198. #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
  199. #define MVPP22_AXI_CODE_CACHE_OFFS 0
  200. #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
  201. #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
  202. #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
  203. #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
  204. #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
  205. #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
  206. /* Interrupt Cause and Mask registers */
  207. #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
  208. #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
  209. #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
  210. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  211. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  212. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
  213. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  214. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  215. #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
  216. #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
  217. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
  218. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
  219. #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
  220. #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
  221. #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
  222. #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
  223. #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  224. #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
  225. #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
  226. #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
  227. #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
  228. #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
  229. #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
  230. #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
  231. #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
  232. #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
  233. #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  234. #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
  235. #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
  236. #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
  237. /* Buffer Manager registers */
  238. #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
  239. #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
  240. #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
  241. #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
  242. #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
  243. #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
  244. #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
  245. #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
  246. #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
  247. #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
  248. #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
  249. #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
  250. #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
  251. #define MVPP2_BM_START_MASK BIT(0)
  252. #define MVPP2_BM_STOP_MASK BIT(1)
  253. #define MVPP2_BM_STATE_MASK BIT(4)
  254. #define MVPP2_BM_LOW_THRESH_OFFS 8
  255. #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
  256. #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
  257. MVPP2_BM_LOW_THRESH_OFFS)
  258. #define MVPP2_BM_HIGH_THRESH_OFFS 16
  259. #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
  260. #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
  261. MVPP2_BM_HIGH_THRESH_OFFS)
  262. #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
  263. #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
  264. #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
  265. #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
  266. #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
  267. #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
  268. #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
  269. #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
  270. #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
  271. #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
  272. #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
  273. #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
  274. #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
  275. #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
  276. #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
  277. #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
  278. #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
  279. #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
  280. #define MVPP2_BM_VIRT_RLS_REG 0x64c0
  281. #define MVPP21_BM_MC_RLS_REG 0x64c4
  282. #define MVPP2_BM_MC_ID_MASK 0xfff
  283. #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
  284. #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
  285. #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
  286. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
  287. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
  288. #define MVPP22_BM_MC_RLS_REG 0x64d4
  289. #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
  290. #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
  291. /* TX Scheduler registers */
  292. #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
  293. #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
  294. #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
  295. #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
  296. #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
  297. #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
  298. #define MVPP2_TXP_SCHED_MTU_REG 0x801c
  299. #define MVPP2_TXP_MTU_MAX 0x7FFFF
  300. #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
  301. #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
  302. #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
  303. #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
  304. #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
  305. #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
  306. #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
  307. #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
  308. #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
  309. #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
  310. #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
  311. #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  312. #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
  313. #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
  314. /* TX general registers */
  315. #define MVPP2_TX_SNOOP_REG 0x8800
  316. #define MVPP2_TX_PORT_FLUSH_REG 0x8810
  317. #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
  318. /* LMS registers */
  319. #define MVPP2_SRC_ADDR_MIDDLE 0x24
  320. #define MVPP2_SRC_ADDR_HIGH 0x28
  321. #define MVPP2_PHY_AN_CFG0_REG 0x34
  322. #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
  323. #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
  324. #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
  325. /* Per-port registers */
  326. #define MVPP2_GMAC_CTRL_0_REG 0x0
  327. #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
  328. #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
  329. #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
  330. #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  331. #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
  332. #define MVPP2_GMAC_CTRL_1_REG 0x4
  333. #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
  334. #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
  335. #define MVPP2_GMAC_PCS_LB_EN_BIT 6
  336. #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
  337. #define MVPP2_GMAC_SA_LOW_OFFS 7
  338. #define MVPP2_GMAC_CTRL_2_REG 0x8
  339. #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
  340. #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
  341. #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
  342. #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
  343. #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
  344. #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
  345. #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
  346. #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
  347. #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
  348. #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
  349. #define MVPP2_GMAC_EN_PCS_AN BIT(2)
  350. #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
  351. #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
  352. #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
  353. #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
  354. #define MVPP2_GMAC_FC_ADV_EN BIT(9)
  355. #define MVPP2_GMAC_EN_FC_AN BIT(11)
  356. #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  357. #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
  358. #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
  359. #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
  360. #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
  361. #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
  362. #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
  363. MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
  364. #define MVPP2_GMAC_CTRL_4_REG 0x90
  365. #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
  366. #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
  367. #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
  368. #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
  369. /*
  370. * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
  371. * relative to port->base.
  372. */
  373. /* Port Mac Control0 */
  374. #define MVPP22_XLG_CTRL0_REG 0x100
  375. #define MVPP22_XLG_PORT_EN BIT(0)
  376. #define MVPP22_XLG_MAC_RESETN BIT(1)
  377. #define MVPP22_XLG_RX_FC_EN BIT(7)
  378. #define MVPP22_XLG_MIBCNT_DIS BIT(13)
  379. /* Port Mac Control1 */
  380. #define MVPP22_XLG_CTRL1_REG 0x104
  381. #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
  382. #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
  383. /* Port Interrupt Mask */
  384. #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
  385. #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
  386. /* Port Mac Control3 */
  387. #define MVPP22_XLG_CTRL3_REG 0x11c
  388. #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
  389. #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
  390. #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
  391. /* Port Mac Control4 */
  392. #define MVPP22_XLG_CTRL4_REG 0x184
  393. #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
  394. #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
  395. #define MVPP22_XLG_MODE_DMA_1G BIT(12)
  396. #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
  397. /* XPCS registers */
  398. /* Global Configuration 0 */
  399. #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
  400. #define MVPP22_XPCS_PCSRESET BIT(0)
  401. #define MVPP22_XPCS_PCSMODE_OFFS 3
  402. #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
  403. MVPP22_XPCS_PCSMODE_OFFS)
  404. #define MVPP22_XPCS_LANEACTIVE_OFFS 5
  405. #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
  406. MVPP22_XPCS_LANEACTIVE_OFFS)
  407. /* MPCS registers */
  408. #define PCS40G_COMMON_CONTROL 0x14
  409. #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
  410. #define PCS_CLOCK_RESET 0x14c
  411. #define TX_SD_CLK_RESET_MASK BIT(0)
  412. #define RX_SD_CLK_RESET_MASK BIT(1)
  413. #define MAC_CLK_RESET_MASK BIT(2)
  414. #define CLK_DIVISION_RATIO_OFFS 4
  415. #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
  416. #define CLK_DIV_PHASE_SET_MASK BIT(11)
  417. /* System Soft Reset 1 */
  418. #define GOP_SOFT_RESET_1_REG 0x108
  419. #define NETC_GOP_SOFT_RESET_OFFS 6
  420. #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
  421. NETC_GOP_SOFT_RESET_OFFS)
  422. /* Ports Control 0 */
  423. #define NETCOMP_PORTS_CONTROL_0_REG 0x110
  424. #define NETC_BUS_WIDTH_SELECT_OFFS 1
  425. #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
  426. NETC_BUS_WIDTH_SELECT_OFFS)
  427. #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
  428. #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
  429. NETC_GIG_RX_DATA_SAMPLE_OFFS)
  430. #define NETC_CLK_DIV_PHASE_OFFS 31
  431. #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
  432. /* Ports Control 1 */
  433. #define NETCOMP_PORTS_CONTROL_1_REG 0x114
  434. #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
  435. #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
  436. NETC_PORTS_ACTIVE_OFFSET(p))
  437. #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
  438. #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
  439. NETC_PORT_GIG_RF_RESET_OFFS(p))
  440. #define NETCOMP_CONTROL_0_REG 0x120
  441. #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
  442. #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
  443. NETC_GBE_PORT0_SGMII_MODE_OFFS)
  444. #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
  445. #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
  446. NETC_GBE_PORT1_SGMII_MODE_OFFS)
  447. #define NETC_GBE_PORT1_MII_MODE_OFFS 2
  448. #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
  449. NETC_GBE_PORT1_MII_MODE_OFFS)
  450. #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
  451. #define MVPP22_SMI_POLLING_EN BIT(10)
  452. #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
  453. (0x4 * (port)))
  454. #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  455. /* Descriptor ring Macros */
  456. #define MVPP2_QUEUE_NEXT_DESC(q, index) \
  457. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  458. /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
  459. #define MVPP22_SMI 0x1200
  460. /* Additional PPv2.2 offsets */
  461. #define MVPP22_MPCS 0x007000
  462. #define MVPP22_XPCS 0x007400
  463. #define MVPP22_PORT_BASE 0x007e00
  464. #define MVPP22_PORT_OFFSET 0x001000
  465. #define MVPP22_RFU1 0x318000
  466. /* Maximum number of ports */
  467. #define MVPP22_GOP_MAC_NUM 4
  468. /* Sets the field located at the specified in data */
  469. #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
  470. #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
  471. #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
  472. /* Net Complex */
  473. enum mv_netc_topology {
  474. MV_NETC_GE_MAC2_SGMII = BIT(0),
  475. MV_NETC_GE_MAC3_SGMII = BIT(1),
  476. MV_NETC_GE_MAC3_RGMII = BIT(2),
  477. };
  478. enum mv_netc_phase {
  479. MV_NETC_FIRST_PHASE,
  480. MV_NETC_SECOND_PHASE,
  481. };
  482. enum mv_netc_sgmii_xmi_mode {
  483. MV_NETC_GBE_SGMII,
  484. MV_NETC_GBE_XMII,
  485. };
  486. enum mv_netc_mii_mode {
  487. MV_NETC_GBE_RGMII,
  488. MV_NETC_GBE_MII,
  489. };
  490. enum mv_netc_lanes {
  491. MV_NETC_LANE_23,
  492. MV_NETC_LANE_45,
  493. };
  494. /* Various constants */
  495. /* Coalescing */
  496. #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
  497. #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
  498. #define MVPP2_RX_COAL_PKTS 32
  499. #define MVPP2_RX_COAL_USEC 100
  500. /* The two bytes Marvell header. Either contains a special value used
  501. * by Marvell switches when a specific hardware mode is enabled (not
  502. * supported by this driver) or is filled automatically by zeroes on
  503. * the RX side. Those two bytes being at the front of the Ethernet
  504. * header, they allow to have the IP header aligned on a 4 bytes
  505. * boundary automatically: the hardware skips those two bytes on its
  506. * own.
  507. */
  508. #define MVPP2_MH_SIZE 2
  509. #define MVPP2_ETH_TYPE_LEN 2
  510. #define MVPP2_PPPOE_HDR_SIZE 8
  511. #define MVPP2_VLAN_TAG_LEN 4
  512. /* Lbtd 802.3 type */
  513. #define MVPP2_IP_LBDT_TYPE 0xfffa
  514. #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
  515. #define MVPP2_TX_CSUM_MAX_SIZE 9800
  516. /* Timeout constants */
  517. #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
  518. #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
  519. #define MVPP2_TX_MTU_MAX 0x7ffff
  520. /* Maximum number of T-CONTs of PON port */
  521. #define MVPP2_MAX_TCONT 16
  522. /* Maximum number of supported ports */
  523. #define MVPP2_MAX_PORTS 4
  524. /* Maximum number of TXQs used by single port */
  525. #define MVPP2_MAX_TXQ 8
  526. /* Default number of TXQs in use */
  527. #define MVPP2_DEFAULT_TXQ 1
  528. /* Default number of RXQs in use */
  529. #define MVPP2_DEFAULT_RXQ 1
  530. #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
  531. /* Max number of Rx descriptors */
  532. #define MVPP2_MAX_RXD 16
  533. /* Max number of Tx descriptors */
  534. #define MVPP2_MAX_TXD 16
  535. /* Amount of Tx descriptors that can be reserved at once by CPU */
  536. #define MVPP2_CPU_DESC_CHUNK 16
  537. /* Max number of Tx descriptors in each aggregated queue */
  538. #define MVPP2_AGGR_TXQ_SIZE 16
  539. /* Descriptor aligned size */
  540. #define MVPP2_DESC_ALIGNED_SIZE 32
  541. /* Descriptor alignment mask */
  542. #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
  543. /* RX FIFO constants */
  544. #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
  545. #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
  546. #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
  547. #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
  548. #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
  549. #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
  550. #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
  551. #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
  552. #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
  553. /* TX general registers */
  554. #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
  555. #define MVPP22_TX_FIFO_SIZE_MASK 0xf
  556. /* TX FIFO constants */
  557. #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
  558. #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
  559. /* RX buffer constants */
  560. #define MVPP2_SKB_SHINFO_SIZE \
  561. 0
  562. #define MVPP2_RX_PKT_SIZE(mtu) \
  563. ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
  564. ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
  565. #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
  566. #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
  567. #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
  568. ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
  569. #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
  570. /* IPv6 max L3 address size */
  571. #define MVPP2_MAX_L3_ADDR_SIZE 16
  572. /* Port flags */
  573. #define MVPP2_F_LOOPBACK BIT(0)
  574. /* Marvell tag types */
  575. enum mvpp2_tag_type {
  576. MVPP2_TAG_TYPE_NONE = 0,
  577. MVPP2_TAG_TYPE_MH = 1,
  578. MVPP2_TAG_TYPE_DSA = 2,
  579. MVPP2_TAG_TYPE_EDSA = 3,
  580. MVPP2_TAG_TYPE_VLAN = 4,
  581. MVPP2_TAG_TYPE_LAST = 5
  582. };
  583. /* Parser constants */
  584. #define MVPP2_PRS_TCAM_SRAM_SIZE 256
  585. #define MVPP2_PRS_TCAM_WORDS 6
  586. #define MVPP2_PRS_SRAM_WORDS 4
  587. #define MVPP2_PRS_FLOW_ID_SIZE 64
  588. #define MVPP2_PRS_FLOW_ID_MASK 0x3f
  589. #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
  590. #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
  591. #define MVPP2_PRS_IPV4_HEAD 0x40
  592. #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
  593. #define MVPP2_PRS_IPV4_MC 0xe0
  594. #define MVPP2_PRS_IPV4_MC_MASK 0xf0
  595. #define MVPP2_PRS_IPV4_BC_MASK 0xff
  596. #define MVPP2_PRS_IPV4_IHL 0x5
  597. #define MVPP2_PRS_IPV4_IHL_MASK 0xf
  598. #define MVPP2_PRS_IPV6_MC 0xff
  599. #define MVPP2_PRS_IPV6_MC_MASK 0xff
  600. #define MVPP2_PRS_IPV6_HOP_MASK 0xff
  601. #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
  602. #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
  603. #define MVPP2_PRS_DBL_VLANS_MAX 100
  604. /* Tcam structure:
  605. * - lookup ID - 4 bits
  606. * - port ID - 1 byte
  607. * - additional information - 1 byte
  608. * - header data - 8 bytes
  609. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
  610. */
  611. #define MVPP2_PRS_AI_BITS 8
  612. #define MVPP2_PRS_PORT_MASK 0xff
  613. #define MVPP2_PRS_LU_MASK 0xf
  614. #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
  615. (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
  616. #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
  617. (((offs) * 2) - ((offs) % 2) + 2)
  618. #define MVPP2_PRS_TCAM_AI_BYTE 16
  619. #define MVPP2_PRS_TCAM_PORT_BYTE 17
  620. #define MVPP2_PRS_TCAM_LU_BYTE 20
  621. #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
  622. #define MVPP2_PRS_TCAM_INV_WORD 5
  623. /* Tcam entries ID */
  624. #define MVPP2_PE_DROP_ALL 0
  625. #define MVPP2_PE_FIRST_FREE_TID 1
  626. #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
  627. #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
  628. #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
  629. #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
  630. #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
  631. #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
  632. #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
  633. #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
  634. #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
  635. #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
  636. #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
  637. #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
  638. #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
  639. #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
  640. #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
  641. #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
  642. #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
  643. #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
  644. #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
  645. #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
  646. #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
  647. #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
  648. #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
  649. #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
  650. #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  651. /* Sram structure
  652. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
  653. */
  654. #define MVPP2_PRS_SRAM_RI_OFFS 0
  655. #define MVPP2_PRS_SRAM_RI_WORD 0
  656. #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
  657. #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
  658. #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
  659. #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
  660. #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
  661. #define MVPP2_PRS_SRAM_UDF_OFFS 73
  662. #define MVPP2_PRS_SRAM_UDF_BITS 8
  663. #define MVPP2_PRS_SRAM_UDF_MASK 0xff
  664. #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
  665. #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
  666. #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
  667. #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
  668. #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
  669. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
  670. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
  671. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
  672. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
  673. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
  674. #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
  675. #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
  676. #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
  677. #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
  678. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
  679. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
  680. #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
  681. #define MVPP2_PRS_SRAM_AI_OFFS 90
  682. #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
  683. #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
  684. #define MVPP2_PRS_SRAM_AI_MASK 0xff
  685. #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
  686. #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
  687. #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
  688. #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
  689. /* Sram result info bits assignment */
  690. #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
  691. #define MVPP2_PRS_RI_DSA_MASK 0x2
  692. #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
  693. #define MVPP2_PRS_RI_VLAN_NONE 0x0
  694. #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
  695. #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
  696. #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
  697. #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
  698. #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
  699. #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
  700. #define MVPP2_PRS_RI_L2_UCAST 0x0
  701. #define MVPP2_PRS_RI_L2_MCAST BIT(9)
  702. #define MVPP2_PRS_RI_L2_BCAST BIT(10)
  703. #define MVPP2_PRS_RI_PPPOE_MASK 0x800
  704. #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
  705. #define MVPP2_PRS_RI_L3_UN 0x0
  706. #define MVPP2_PRS_RI_L3_IP4 BIT(12)
  707. #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
  708. #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
  709. #define MVPP2_PRS_RI_L3_IP6 BIT(14)
  710. #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
  711. #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
  712. #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
  713. #define MVPP2_PRS_RI_L3_UCAST 0x0
  714. #define MVPP2_PRS_RI_L3_MCAST BIT(15)
  715. #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
  716. #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
  717. #define MVPP2_PRS_RI_UDF3_MASK 0x300000
  718. #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
  719. #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
  720. #define MVPP2_PRS_RI_L4_TCP BIT(22)
  721. #define MVPP2_PRS_RI_L4_UDP BIT(23)
  722. #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
  723. #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
  724. #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
  725. #define MVPP2_PRS_RI_DROP_MASK 0x80000000
  726. /* Sram additional info bits assignment */
  727. #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
  728. #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
  729. #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
  730. #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
  731. #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
  732. #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
  733. #define MVPP2_PRS_SINGLE_VLAN_AI 0
  734. #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
  735. /* DSA/EDSA type */
  736. #define MVPP2_PRS_TAGGED true
  737. #define MVPP2_PRS_UNTAGGED false
  738. #define MVPP2_PRS_EDSA true
  739. #define MVPP2_PRS_DSA false
  740. /* MAC entries, shadow udf */
  741. enum mvpp2_prs_udf {
  742. MVPP2_PRS_UDF_MAC_DEF,
  743. MVPP2_PRS_UDF_MAC_RANGE,
  744. MVPP2_PRS_UDF_L2_DEF,
  745. MVPP2_PRS_UDF_L2_DEF_COPY,
  746. MVPP2_PRS_UDF_L2_USER,
  747. };
  748. /* Lookup ID */
  749. enum mvpp2_prs_lookup {
  750. MVPP2_PRS_LU_MH,
  751. MVPP2_PRS_LU_MAC,
  752. MVPP2_PRS_LU_DSA,
  753. MVPP2_PRS_LU_VLAN,
  754. MVPP2_PRS_LU_L2,
  755. MVPP2_PRS_LU_PPPOE,
  756. MVPP2_PRS_LU_IP4,
  757. MVPP2_PRS_LU_IP6,
  758. MVPP2_PRS_LU_FLOWS,
  759. MVPP2_PRS_LU_LAST,
  760. };
  761. /* L3 cast enum */
  762. enum mvpp2_prs_l3_cast {
  763. MVPP2_PRS_L3_UNI_CAST,
  764. MVPP2_PRS_L3_MULTI_CAST,
  765. MVPP2_PRS_L3_BROAD_CAST
  766. };
  767. /* Classifier constants */
  768. #define MVPP2_CLS_FLOWS_TBL_SIZE 512
  769. #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
  770. #define MVPP2_CLS_LKP_TBL_SIZE 64
  771. /* BM constants */
  772. #define MVPP2_BM_POOLS_NUM 1
  773. #define MVPP2_BM_LONG_BUF_NUM 16
  774. #define MVPP2_BM_SHORT_BUF_NUM 16
  775. #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
  776. #define MVPP2_BM_POOL_PTR_ALIGN 128
  777. #define MVPP2_BM_SWF_LONG_POOL(port) 0
  778. /* BM cookie (32 bits) definition */
  779. #define MVPP2_BM_COOKIE_POOL_OFFS 8
  780. #define MVPP2_BM_COOKIE_CPU_OFFS 24
  781. /* BM short pool packet size
  782. * These value assure that for SWF the total number
  783. * of bytes allocated for each buffer will be 512
  784. */
  785. #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
  786. enum mvpp2_bm_type {
  787. MVPP2_BM_FREE,
  788. MVPP2_BM_SWF_LONG,
  789. MVPP2_BM_SWF_SHORT
  790. };
  791. /* Definitions */
  792. /* Shared Packet Processor resources */
  793. struct mvpp2 {
  794. /* Shared registers' base addresses */
  795. void __iomem *base;
  796. void __iomem *lms_base;
  797. void __iomem *iface_base;
  798. void __iomem *mpcs_base;
  799. void __iomem *xpcs_base;
  800. void __iomem *rfu1_base;
  801. u32 netc_config;
  802. /* List of pointers to port structures */
  803. struct mvpp2_port **port_list;
  804. /* Aggregated TXQs */
  805. struct mvpp2_tx_queue *aggr_txqs;
  806. /* BM pools */
  807. struct mvpp2_bm_pool *bm_pools;
  808. /* PRS shadow table */
  809. struct mvpp2_prs_shadow *prs_shadow;
  810. /* PRS auxiliary table for double vlan entries control */
  811. bool *prs_double_vlans;
  812. /* Tclk value */
  813. u32 tclk;
  814. /* HW version */
  815. enum { MVPP21, MVPP22 } hw_version;
  816. /* Maximum number of RXQs per port */
  817. unsigned int max_port_rxqs;
  818. int probe_done;
  819. u8 num_ports;
  820. };
  821. struct mvpp2_pcpu_stats {
  822. u64 rx_packets;
  823. u64 rx_bytes;
  824. u64 tx_packets;
  825. u64 tx_bytes;
  826. };
  827. struct mvpp2_port {
  828. u8 id;
  829. /* Index of the port from the "group of ports" complex point
  830. * of view
  831. */
  832. int gop_id;
  833. int irq;
  834. struct mvpp2 *priv;
  835. /* Per-port registers' base address */
  836. void __iomem *base;
  837. struct mvpp2_rx_queue **rxqs;
  838. struct mvpp2_tx_queue **txqs;
  839. int pkt_size;
  840. u32 pending_cause_rx;
  841. /* Per-CPU port control */
  842. struct mvpp2_port_pcpu __percpu *pcpu;
  843. /* Flags */
  844. unsigned long flags;
  845. u16 tx_ring_size;
  846. u16 rx_ring_size;
  847. struct mvpp2_pcpu_stats __percpu *stats;
  848. struct phy_device *phy_dev;
  849. phy_interface_t phy_interface;
  850. int phyaddr;
  851. struct udevice *mdio_dev;
  852. struct mii_dev *bus;
  853. #if CONFIG_IS_ENABLED(DM_GPIO)
  854. struct gpio_desc phy_reset_gpio;
  855. struct gpio_desc phy_tx_disable_gpio;
  856. #endif
  857. int init;
  858. unsigned int link;
  859. unsigned int duplex;
  860. unsigned int speed;
  861. unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
  862. struct mvpp2_bm_pool *pool_long;
  863. struct mvpp2_bm_pool *pool_short;
  864. /* Index of first port's physical RXQ */
  865. u8 first_rxq;
  866. u8 dev_addr[ETH_ALEN];
  867. };
  868. /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
  869. * layout of the transmit and reception DMA descriptors, and their
  870. * layout is therefore defined by the hardware design
  871. */
  872. #define MVPP2_TXD_L3_OFF_SHIFT 0
  873. #define MVPP2_TXD_IP_HLEN_SHIFT 8
  874. #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
  875. #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
  876. #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
  877. #define MVPP2_TXD_PADDING_DISABLE BIT(23)
  878. #define MVPP2_TXD_L4_UDP BIT(24)
  879. #define MVPP2_TXD_L3_IP6 BIT(26)
  880. #define MVPP2_TXD_L_DESC BIT(28)
  881. #define MVPP2_TXD_F_DESC BIT(29)
  882. #define MVPP2_RXD_ERR_SUMMARY BIT(15)
  883. #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
  884. #define MVPP2_RXD_ERR_CRC 0x0
  885. #define MVPP2_RXD_ERR_OVERRUN BIT(13)
  886. #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
  887. #define MVPP2_RXD_BM_POOL_ID_OFFS 16
  888. #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
  889. #define MVPP2_RXD_HWF_SYNC BIT(21)
  890. #define MVPP2_RXD_L4_CSUM_OK BIT(22)
  891. #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
  892. #define MVPP2_RXD_L4_TCP BIT(25)
  893. #define MVPP2_RXD_L4_UDP BIT(26)
  894. #define MVPP2_RXD_L3_IP4 BIT(28)
  895. #define MVPP2_RXD_L3_IP6 BIT(30)
  896. #define MVPP2_RXD_BUF_HDR BIT(31)
  897. /* HW TX descriptor for PPv2.1 */
  898. struct mvpp21_tx_desc {
  899. u32 command; /* Options used by HW for packet transmitting.*/
  900. u8 packet_offset; /* the offset from the buffer beginning */
  901. u8 phys_txq; /* destination queue ID */
  902. u16 data_size; /* data size of transmitted packet in bytes */
  903. u32 buf_dma_addr; /* physical addr of transmitted buffer */
  904. u32 buf_cookie; /* cookie for access to TX buffer in tx path */
  905. u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
  906. u32 reserved2; /* reserved (for future use) */
  907. };
  908. /* HW RX descriptor for PPv2.1 */
  909. struct mvpp21_rx_desc {
  910. u32 status; /* info about received packet */
  911. u16 reserved1; /* parser_info (for future use, PnC) */
  912. u16 data_size; /* size of received packet in bytes */
  913. u32 buf_dma_addr; /* physical address of the buffer */
  914. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  915. u16 reserved2; /* gem_port_id (for future use, PON) */
  916. u16 reserved3; /* csum_l4 (for future use, PnC) */
  917. u8 reserved4; /* bm_qset (for future use, BM) */
  918. u8 reserved5;
  919. u16 reserved6; /* classify_info (for future use, PnC) */
  920. u32 reserved7; /* flow_id (for future use, PnC) */
  921. u32 reserved8;
  922. };
  923. /* HW TX descriptor for PPv2.2 */
  924. struct mvpp22_tx_desc {
  925. u32 command;
  926. u8 packet_offset;
  927. u8 phys_txq;
  928. u16 data_size;
  929. u64 reserved1;
  930. u64 buf_dma_addr_ptp;
  931. u64 buf_cookie_misc;
  932. };
  933. /* HW RX descriptor for PPv2.2 */
  934. struct mvpp22_rx_desc {
  935. u32 status;
  936. u16 reserved1;
  937. u16 data_size;
  938. u32 reserved2;
  939. u32 reserved3;
  940. u64 buf_dma_addr_key_hash;
  941. u64 buf_cookie_misc;
  942. };
  943. /* Opaque type used by the driver to manipulate the HW TX and RX
  944. * descriptors
  945. */
  946. struct mvpp2_tx_desc {
  947. union {
  948. struct mvpp21_tx_desc pp21;
  949. struct mvpp22_tx_desc pp22;
  950. };
  951. };
  952. struct mvpp2_rx_desc {
  953. union {
  954. struct mvpp21_rx_desc pp21;
  955. struct mvpp22_rx_desc pp22;
  956. };
  957. };
  958. /* Per-CPU Tx queue control */
  959. struct mvpp2_txq_pcpu {
  960. int cpu;
  961. /* Number of Tx DMA descriptors in the descriptor ring */
  962. int size;
  963. /* Number of currently used Tx DMA descriptor in the
  964. * descriptor ring
  965. */
  966. int count;
  967. /* Number of Tx DMA descriptors reserved for each CPU */
  968. int reserved_num;
  969. /* Index of last TX DMA descriptor that was inserted */
  970. int txq_put_index;
  971. /* Index of the TX DMA descriptor to be cleaned up */
  972. int txq_get_index;
  973. };
  974. struct mvpp2_tx_queue {
  975. /* Physical number of this Tx queue */
  976. u8 id;
  977. /* Logical number of this Tx queue */
  978. u8 log_id;
  979. /* Number of Tx DMA descriptors in the descriptor ring */
  980. int size;
  981. /* Number of currently used Tx DMA descriptor in the descriptor ring */
  982. int count;
  983. /* Per-CPU control of physical Tx queues */
  984. struct mvpp2_txq_pcpu __percpu *pcpu;
  985. u32 done_pkts_coal;
  986. /* Virtual address of thex Tx DMA descriptors array */
  987. struct mvpp2_tx_desc *descs;
  988. /* DMA address of the Tx DMA descriptors array */
  989. dma_addr_t descs_dma;
  990. /* Index of the last Tx DMA descriptor */
  991. int last_desc;
  992. /* Index of the next Tx DMA descriptor to process */
  993. int next_desc_to_proc;
  994. };
  995. struct mvpp2_rx_queue {
  996. /* RX queue number, in the range 0-31 for physical RXQs */
  997. u8 id;
  998. /* Num of rx descriptors in the rx descriptor ring */
  999. int size;
  1000. u32 pkts_coal;
  1001. u32 time_coal;
  1002. /* Virtual address of the RX DMA descriptors array */
  1003. struct mvpp2_rx_desc *descs;
  1004. /* DMA address of the RX DMA descriptors array */
  1005. dma_addr_t descs_dma;
  1006. /* Index of the last RX DMA descriptor */
  1007. int last_desc;
  1008. /* Index of the next RX DMA descriptor to process */
  1009. int next_desc_to_proc;
  1010. /* ID of port to which physical RXQ is mapped */
  1011. int port;
  1012. /* Port's logic RXQ number to which physical RXQ is mapped */
  1013. int logic_rxq;
  1014. };
  1015. union mvpp2_prs_tcam_entry {
  1016. u32 word[MVPP2_PRS_TCAM_WORDS];
  1017. u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
  1018. };
  1019. union mvpp2_prs_sram_entry {
  1020. u32 word[MVPP2_PRS_SRAM_WORDS];
  1021. u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
  1022. };
  1023. struct mvpp2_prs_entry {
  1024. u32 index;
  1025. union mvpp2_prs_tcam_entry tcam;
  1026. union mvpp2_prs_sram_entry sram;
  1027. };
  1028. struct mvpp2_prs_shadow {
  1029. bool valid;
  1030. bool finish;
  1031. /* Lookup ID */
  1032. int lu;
  1033. /* User defined offset */
  1034. int udf;
  1035. /* Result info */
  1036. u32 ri;
  1037. u32 ri_mask;
  1038. };
  1039. struct mvpp2_cls_flow_entry {
  1040. u32 index;
  1041. u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
  1042. };
  1043. struct mvpp2_cls_lookup_entry {
  1044. u32 lkpid;
  1045. u32 way;
  1046. u32 data;
  1047. };
  1048. struct mvpp2_bm_pool {
  1049. /* Pool number in the range 0-7 */
  1050. int id;
  1051. enum mvpp2_bm_type type;
  1052. /* Buffer Pointers Pool External (BPPE) size */
  1053. int size;
  1054. /* Number of buffers for this pool */
  1055. int buf_num;
  1056. /* Pool buffer size */
  1057. int buf_size;
  1058. /* Packet size */
  1059. int pkt_size;
  1060. /* BPPE virtual base address */
  1061. unsigned long *virt_addr;
  1062. /* BPPE DMA base address */
  1063. dma_addr_t dma_addr;
  1064. /* Ports using BM pool */
  1065. u32 port_map;
  1066. };
  1067. /* Static declaractions */
  1068. /* Number of RXQs used by single port */
  1069. static int rxq_number = MVPP2_DEFAULT_RXQ;
  1070. /* Number of TXQs used by single port */
  1071. static int txq_number = MVPP2_DEFAULT_TXQ;
  1072. static int base_id;
  1073. #define MVPP2_DRIVER_NAME "mvpp2"
  1074. #define MVPP2_DRIVER_VERSION "1.0"
  1075. /*
  1076. * U-Boot internal data, mostly uncached buffers for descriptors and data
  1077. */
  1078. struct buffer_location {
  1079. struct mvpp2_tx_desc *aggr_tx_descs;
  1080. struct mvpp2_tx_desc *tx_descs;
  1081. struct mvpp2_rx_desc *rx_descs;
  1082. unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
  1083. unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
  1084. int first_rxq;
  1085. };
  1086. /*
  1087. * All 4 interfaces use the same global buffer, since only one interface
  1088. * can be enabled at once
  1089. */
  1090. static struct buffer_location buffer_loc;
  1091. static int buffer_loc_init;
  1092. /*
  1093. * Page table entries are set to 1MB, or multiples of 1MB
  1094. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  1095. */
  1096. #define BD_SPACE (1 << 20)
  1097. /* Utility/helper methods */
  1098. static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  1099. {
  1100. writel(data, priv->base + offset);
  1101. }
  1102. static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  1103. {
  1104. return readl(priv->base + offset);
  1105. }
  1106. static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
  1107. struct mvpp2_tx_desc *tx_desc,
  1108. dma_addr_t dma_addr)
  1109. {
  1110. if (port->priv->hw_version == MVPP21) {
  1111. tx_desc->pp21.buf_dma_addr = dma_addr;
  1112. } else {
  1113. u64 val = (u64)dma_addr;
  1114. tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
  1115. tx_desc->pp22.buf_dma_addr_ptp |= val;
  1116. }
  1117. }
  1118. static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  1119. struct mvpp2_tx_desc *tx_desc,
  1120. size_t size)
  1121. {
  1122. if (port->priv->hw_version == MVPP21)
  1123. tx_desc->pp21.data_size = size;
  1124. else
  1125. tx_desc->pp22.data_size = size;
  1126. }
  1127. static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
  1128. struct mvpp2_tx_desc *tx_desc,
  1129. unsigned int txq)
  1130. {
  1131. if (port->priv->hw_version == MVPP21)
  1132. tx_desc->pp21.phys_txq = txq;
  1133. else
  1134. tx_desc->pp22.phys_txq = txq;
  1135. }
  1136. static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
  1137. struct mvpp2_tx_desc *tx_desc,
  1138. unsigned int command)
  1139. {
  1140. if (port->priv->hw_version == MVPP21)
  1141. tx_desc->pp21.command = command;
  1142. else
  1143. tx_desc->pp22.command = command;
  1144. }
  1145. static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
  1146. struct mvpp2_tx_desc *tx_desc,
  1147. unsigned int offset)
  1148. {
  1149. if (port->priv->hw_version == MVPP21)
  1150. tx_desc->pp21.packet_offset = offset;
  1151. else
  1152. tx_desc->pp22.packet_offset = offset;
  1153. }
  1154. static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
  1155. struct mvpp2_rx_desc *rx_desc)
  1156. {
  1157. if (port->priv->hw_version == MVPP21)
  1158. return rx_desc->pp21.buf_dma_addr;
  1159. else
  1160. return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
  1161. }
  1162. static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
  1163. struct mvpp2_rx_desc *rx_desc)
  1164. {
  1165. if (port->priv->hw_version == MVPP21)
  1166. return rx_desc->pp21.buf_cookie;
  1167. else
  1168. return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
  1169. }
  1170. static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
  1171. struct mvpp2_rx_desc *rx_desc)
  1172. {
  1173. if (port->priv->hw_version == MVPP21)
  1174. return rx_desc->pp21.data_size;
  1175. else
  1176. return rx_desc->pp22.data_size;
  1177. }
  1178. static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
  1179. struct mvpp2_rx_desc *rx_desc)
  1180. {
  1181. if (port->priv->hw_version == MVPP21)
  1182. return rx_desc->pp21.status;
  1183. else
  1184. return rx_desc->pp22.status;
  1185. }
  1186. static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
  1187. {
  1188. txq_pcpu->txq_get_index++;
  1189. if (txq_pcpu->txq_get_index == txq_pcpu->size)
  1190. txq_pcpu->txq_get_index = 0;
  1191. }
  1192. /* Get number of physical egress port */
  1193. static inline int mvpp2_egress_port(struct mvpp2_port *port)
  1194. {
  1195. return MVPP2_MAX_TCONT + port->id;
  1196. }
  1197. /* Get number of physical TXQ */
  1198. static inline int mvpp2_txq_phys(int port, int txq)
  1199. {
  1200. return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
  1201. }
  1202. /* Parser configuration routines */
  1203. /* Update parser tcam and sram hw entries */
  1204. static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1205. {
  1206. int i;
  1207. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1208. return -EINVAL;
  1209. /* Clear entry invalidation bit */
  1210. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
  1211. /* Write tcam index - indirect access */
  1212. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1213. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1214. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
  1215. /* Write sram index - indirect access */
  1216. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1217. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1218. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
  1219. return 0;
  1220. }
  1221. /* Read tcam entry from hw */
  1222. static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1223. {
  1224. int i;
  1225. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1226. return -EINVAL;
  1227. /* Write tcam index - indirect access */
  1228. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1229. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
  1230. MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
  1231. if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
  1232. return MVPP2_PRS_TCAM_ENTRY_INVALID;
  1233. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1234. pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
  1235. /* Write sram index - indirect access */
  1236. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1237. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1238. pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
  1239. return 0;
  1240. }
  1241. /* Invalidate tcam hw entry */
  1242. static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
  1243. {
  1244. /* Write index - indirect access */
  1245. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1246. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
  1247. MVPP2_PRS_TCAM_INV_MASK);
  1248. }
  1249. /* Enable shadow table entry and set its lookup ID */
  1250. static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
  1251. {
  1252. priv->prs_shadow[index].valid = true;
  1253. priv->prs_shadow[index].lu = lu;
  1254. }
  1255. /* Update ri fields in shadow table entry */
  1256. static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
  1257. unsigned int ri, unsigned int ri_mask)
  1258. {
  1259. priv->prs_shadow[index].ri_mask = ri_mask;
  1260. priv->prs_shadow[index].ri = ri;
  1261. }
  1262. /* Update lookup field in tcam sw entry */
  1263. static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
  1264. {
  1265. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
  1266. pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
  1267. pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
  1268. }
  1269. /* Update mask for single port in tcam sw entry */
  1270. static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
  1271. unsigned int port, bool add)
  1272. {
  1273. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1274. if (add)
  1275. pe->tcam.byte[enable_off] &= ~(1 << port);
  1276. else
  1277. pe->tcam.byte[enable_off] |= 1 << port;
  1278. }
  1279. /* Update port map in tcam sw entry */
  1280. static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
  1281. unsigned int ports)
  1282. {
  1283. unsigned char port_mask = MVPP2_PRS_PORT_MASK;
  1284. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1285. pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
  1286. pe->tcam.byte[enable_off] &= ~port_mask;
  1287. pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
  1288. }
  1289. /* Obtain port map from tcam sw entry */
  1290. static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
  1291. {
  1292. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1293. return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
  1294. }
  1295. /* Set byte of data and its enable bits in tcam sw entry */
  1296. static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
  1297. unsigned int offs, unsigned char byte,
  1298. unsigned char enable)
  1299. {
  1300. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
  1301. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
  1302. }
  1303. /* Get byte of data and its enable bits from tcam sw entry */
  1304. static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
  1305. unsigned int offs, unsigned char *byte,
  1306. unsigned char *enable)
  1307. {
  1308. *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
  1309. *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
  1310. }
  1311. /* Set ethertype in tcam sw entry */
  1312. static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
  1313. unsigned short ethertype)
  1314. {
  1315. mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
  1316. mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
  1317. }
  1318. /* Set bits in sram sw entry */
  1319. static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
  1320. int val)
  1321. {
  1322. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
  1323. }
  1324. /* Clear bits in sram sw entry */
  1325. static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
  1326. int val)
  1327. {
  1328. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
  1329. }
  1330. /* Update ri bits in sram sw entry */
  1331. static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
  1332. unsigned int bits, unsigned int mask)
  1333. {
  1334. unsigned int i;
  1335. for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
  1336. int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
  1337. if (!(mask & BIT(i)))
  1338. continue;
  1339. if (bits & BIT(i))
  1340. mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
  1341. else
  1342. mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
  1343. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
  1344. }
  1345. }
  1346. /* Update ai bits in sram sw entry */
  1347. static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
  1348. unsigned int bits, unsigned int mask)
  1349. {
  1350. unsigned int i;
  1351. int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
  1352. for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
  1353. if (!(mask & BIT(i)))
  1354. continue;
  1355. if (bits & BIT(i))
  1356. mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
  1357. else
  1358. mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
  1359. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
  1360. }
  1361. }
  1362. /* Read ai bits from sram sw entry */
  1363. static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
  1364. {
  1365. u8 bits;
  1366. int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
  1367. int ai_en_off = ai_off + 1;
  1368. int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
  1369. bits = (pe->sram.byte[ai_off] >> ai_shift) |
  1370. (pe->sram.byte[ai_en_off] << (8 - ai_shift));
  1371. return bits;
  1372. }
  1373. /* In sram sw entry set lookup ID field of the tcam key to be used in the next
  1374. * lookup interation
  1375. */
  1376. static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
  1377. unsigned int lu)
  1378. {
  1379. int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
  1380. mvpp2_prs_sram_bits_clear(pe, sram_next_off,
  1381. MVPP2_PRS_SRAM_NEXT_LU_MASK);
  1382. mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
  1383. }
  1384. /* In the sram sw entry set sign and value of the next lookup offset
  1385. * and the offset value generated to the classifier
  1386. */
  1387. static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
  1388. unsigned int op)
  1389. {
  1390. /* Set sign */
  1391. if (shift < 0) {
  1392. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1393. shift = 0 - shift;
  1394. } else {
  1395. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1396. }
  1397. /* Set value */
  1398. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
  1399. (unsigned char)shift;
  1400. /* Reset and set operation */
  1401. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
  1402. MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
  1403. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
  1404. /* Set base offset as current */
  1405. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1406. }
  1407. /* In the sram sw entry set sign and value of the user defined offset
  1408. * generated to the classifier
  1409. */
  1410. static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
  1411. unsigned int type, int offset,
  1412. unsigned int op)
  1413. {
  1414. /* Set sign */
  1415. if (offset < 0) {
  1416. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1417. offset = 0 - offset;
  1418. } else {
  1419. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1420. }
  1421. /* Set value */
  1422. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
  1423. MVPP2_PRS_SRAM_UDF_MASK);
  1424. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
  1425. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1426. MVPP2_PRS_SRAM_UDF_BITS)] &=
  1427. ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1428. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1429. MVPP2_PRS_SRAM_UDF_BITS)] |=
  1430. (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1431. /* Set offset type */
  1432. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
  1433. MVPP2_PRS_SRAM_UDF_TYPE_MASK);
  1434. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
  1435. /* Set offset operation */
  1436. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
  1437. MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
  1438. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
  1439. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1440. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
  1441. ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
  1442. (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1443. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1444. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
  1445. (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1446. /* Set base offset as current */
  1447. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1448. }
  1449. /* Find parser flow entry */
  1450. static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
  1451. {
  1452. struct mvpp2_prs_entry *pe;
  1453. int tid;
  1454. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1455. if (!pe)
  1456. return NULL;
  1457. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1458. /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
  1459. for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
  1460. u8 bits;
  1461. if (!priv->prs_shadow[tid].valid ||
  1462. priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
  1463. continue;
  1464. pe->index = tid;
  1465. mvpp2_prs_hw_read(priv, pe);
  1466. bits = mvpp2_prs_sram_ai_get(pe);
  1467. /* Sram store classification lookup ID in AI bits [5:0] */
  1468. if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
  1469. return pe;
  1470. }
  1471. kfree(pe);
  1472. return NULL;
  1473. }
  1474. /* Return first free tcam index, seeking from start to end */
  1475. static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
  1476. unsigned char end)
  1477. {
  1478. int tid;
  1479. if (start > end)
  1480. swap(start, end);
  1481. if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
  1482. end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
  1483. for (tid = start; tid <= end; tid++) {
  1484. if (!priv->prs_shadow[tid].valid)
  1485. return tid;
  1486. }
  1487. return -EINVAL;
  1488. }
  1489. /* Enable/disable dropping all mac da's */
  1490. static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
  1491. {
  1492. struct mvpp2_prs_entry pe;
  1493. if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
  1494. /* Entry exist - update port only */
  1495. pe.index = MVPP2_PE_DROP_ALL;
  1496. mvpp2_prs_hw_read(priv, &pe);
  1497. } else {
  1498. /* Entry doesn't exist - create new */
  1499. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1500. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1501. pe.index = MVPP2_PE_DROP_ALL;
  1502. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1503. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1504. MVPP2_PRS_RI_DROP_MASK);
  1505. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1506. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1507. /* Update shadow table */
  1508. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1509. /* Mask all ports */
  1510. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1511. }
  1512. /* Update port mask */
  1513. mvpp2_prs_tcam_port_set(&pe, port, add);
  1514. mvpp2_prs_hw_write(priv, &pe);
  1515. }
  1516. /* Set port to promiscuous mode */
  1517. static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
  1518. {
  1519. struct mvpp2_prs_entry pe;
  1520. /* Promiscuous mode - Accept unknown packets */
  1521. if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
  1522. /* Entry exist - update port only */
  1523. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1524. mvpp2_prs_hw_read(priv, &pe);
  1525. } else {
  1526. /* Entry doesn't exist - create new */
  1527. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1528. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1529. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1530. /* Continue - set next lookup */
  1531. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1532. /* Set result info bits */
  1533. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
  1534. MVPP2_PRS_RI_L2_CAST_MASK);
  1535. /* Shift to ethertype */
  1536. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1537. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1538. /* Mask all ports */
  1539. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1540. /* Update shadow table */
  1541. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1542. }
  1543. /* Update port mask */
  1544. mvpp2_prs_tcam_port_set(&pe, port, add);
  1545. mvpp2_prs_hw_write(priv, &pe);
  1546. }
  1547. /* Accept multicast */
  1548. static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
  1549. bool add)
  1550. {
  1551. struct mvpp2_prs_entry pe;
  1552. unsigned char da_mc;
  1553. /* Ethernet multicast address first byte is
  1554. * 0x01 for IPv4 and 0x33 for IPv6
  1555. */
  1556. da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
  1557. if (priv->prs_shadow[index].valid) {
  1558. /* Entry exist - update port only */
  1559. pe.index = index;
  1560. mvpp2_prs_hw_read(priv, &pe);
  1561. } else {
  1562. /* Entry doesn't exist - create new */
  1563. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1564. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1565. pe.index = index;
  1566. /* Continue - set next lookup */
  1567. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1568. /* Set result info bits */
  1569. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
  1570. MVPP2_PRS_RI_L2_CAST_MASK);
  1571. /* Update tcam entry data first byte */
  1572. mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
  1573. /* Shift to ethertype */
  1574. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1575. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1576. /* Mask all ports */
  1577. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1578. /* Update shadow table */
  1579. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1580. }
  1581. /* Update port mask */
  1582. mvpp2_prs_tcam_port_set(&pe, port, add);
  1583. mvpp2_prs_hw_write(priv, &pe);
  1584. }
  1585. /* Parser per-port initialization */
  1586. static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
  1587. int lu_max, int offset)
  1588. {
  1589. u32 val;
  1590. /* Set lookup ID */
  1591. val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
  1592. val &= ~MVPP2_PRS_PORT_LU_MASK(port);
  1593. val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
  1594. mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
  1595. /* Set maximum number of loops for packet received from port */
  1596. val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
  1597. val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
  1598. val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
  1599. mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
  1600. /* Set initial offset for packet header extraction for the first
  1601. * searching loop
  1602. */
  1603. val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
  1604. val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
  1605. val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
  1606. mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
  1607. }
  1608. /* Default flow entries initialization for all ports */
  1609. static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
  1610. {
  1611. struct mvpp2_prs_entry pe;
  1612. int port;
  1613. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  1614. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1615. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1616. pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
  1617. /* Mask all ports */
  1618. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1619. /* Set flow ID*/
  1620. mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
  1621. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1622. /* Update shadow table and hw entry */
  1623. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
  1624. mvpp2_prs_hw_write(priv, &pe);
  1625. }
  1626. }
  1627. /* Set default entry for Marvell Header field */
  1628. static void mvpp2_prs_mh_init(struct mvpp2 *priv)
  1629. {
  1630. struct mvpp2_prs_entry pe;
  1631. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1632. pe.index = MVPP2_PE_MH_DEFAULT;
  1633. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
  1634. mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
  1635. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1636. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1637. /* Unmask all ports */
  1638. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1639. /* Update shadow table and hw entry */
  1640. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
  1641. mvpp2_prs_hw_write(priv, &pe);
  1642. }
  1643. /* Set default entires (place holder) for promiscuous, non-promiscuous and
  1644. * multicast MAC addresses
  1645. */
  1646. static void mvpp2_prs_mac_init(struct mvpp2 *priv)
  1647. {
  1648. struct mvpp2_prs_entry pe;
  1649. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1650. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1651. pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
  1652. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1653. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1654. MVPP2_PRS_RI_DROP_MASK);
  1655. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1656. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1657. /* Unmask all ports */
  1658. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1659. /* Update shadow table and hw entry */
  1660. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1661. mvpp2_prs_hw_write(priv, &pe);
  1662. /* place holders only - no ports */
  1663. mvpp2_prs_mac_drop_all_set(priv, 0, false);
  1664. mvpp2_prs_mac_promisc_set(priv, 0, false);
  1665. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
  1666. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
  1667. }
  1668. /* Match basic ethertypes */
  1669. static int mvpp2_prs_etype_init(struct mvpp2 *priv)
  1670. {
  1671. struct mvpp2_prs_entry pe;
  1672. int tid;
  1673. /* Ethertype: PPPoE */
  1674. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1675. MVPP2_PE_LAST_FREE_TID);
  1676. if (tid < 0)
  1677. return tid;
  1678. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1679. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1680. pe.index = tid;
  1681. mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
  1682. mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
  1683. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1684. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
  1685. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
  1686. MVPP2_PRS_RI_PPPOE_MASK);
  1687. /* Update shadow table and hw entry */
  1688. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1689. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1690. priv->prs_shadow[pe.index].finish = false;
  1691. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
  1692. MVPP2_PRS_RI_PPPOE_MASK);
  1693. mvpp2_prs_hw_write(priv, &pe);
  1694. /* Ethertype: ARP */
  1695. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1696. MVPP2_PE_LAST_FREE_TID);
  1697. if (tid < 0)
  1698. return tid;
  1699. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1700. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1701. pe.index = tid;
  1702. mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
  1703. /* Generate flow in the next iteration*/
  1704. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1705. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1706. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
  1707. MVPP2_PRS_RI_L3_PROTO_MASK);
  1708. /* Set L3 offset */
  1709. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1710. MVPP2_ETH_TYPE_LEN,
  1711. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1712. /* Update shadow table and hw entry */
  1713. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1714. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1715. priv->prs_shadow[pe.index].finish = true;
  1716. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
  1717. MVPP2_PRS_RI_L3_PROTO_MASK);
  1718. mvpp2_prs_hw_write(priv, &pe);
  1719. /* Ethertype: LBTD */
  1720. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1721. MVPP2_PE_LAST_FREE_TID);
  1722. if (tid < 0)
  1723. return tid;
  1724. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1725. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1726. pe.index = tid;
  1727. mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
  1728. /* Generate flow in the next iteration*/
  1729. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1730. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1731. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1732. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1733. MVPP2_PRS_RI_CPU_CODE_MASK |
  1734. MVPP2_PRS_RI_UDF3_MASK);
  1735. /* Set L3 offset */
  1736. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1737. MVPP2_ETH_TYPE_LEN,
  1738. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1739. /* Update shadow table and hw entry */
  1740. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1741. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1742. priv->prs_shadow[pe.index].finish = true;
  1743. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1744. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1745. MVPP2_PRS_RI_CPU_CODE_MASK |
  1746. MVPP2_PRS_RI_UDF3_MASK);
  1747. mvpp2_prs_hw_write(priv, &pe);
  1748. /* Ethertype: IPv4 without options */
  1749. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1750. MVPP2_PE_LAST_FREE_TID);
  1751. if (tid < 0)
  1752. return tid;
  1753. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1754. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1755. pe.index = tid;
  1756. mvpp2_prs_match_etype(&pe, 0, PROT_IP);
  1757. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1758. MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
  1759. MVPP2_PRS_IPV4_HEAD_MASK |
  1760. MVPP2_PRS_IPV4_IHL_MASK);
  1761. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
  1762. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
  1763. MVPP2_PRS_RI_L3_PROTO_MASK);
  1764. /* Skip eth_type + 4 bytes of IP header */
  1765. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
  1766. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1767. /* Set L3 offset */
  1768. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1769. MVPP2_ETH_TYPE_LEN,
  1770. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1771. /* Update shadow table and hw entry */
  1772. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1773. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1774. priv->prs_shadow[pe.index].finish = false;
  1775. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
  1776. MVPP2_PRS_RI_L3_PROTO_MASK);
  1777. mvpp2_prs_hw_write(priv, &pe);
  1778. /* Ethertype: IPv4 with options */
  1779. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1780. MVPP2_PE_LAST_FREE_TID);
  1781. if (tid < 0)
  1782. return tid;
  1783. pe.index = tid;
  1784. /* Clear tcam data before updating */
  1785. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1786. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1787. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1788. MVPP2_PRS_IPV4_HEAD,
  1789. MVPP2_PRS_IPV4_HEAD_MASK);
  1790. /* Clear ri before updating */
  1791. pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
  1792. pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
  1793. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
  1794. MVPP2_PRS_RI_L3_PROTO_MASK);
  1795. /* Update shadow table and hw entry */
  1796. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1797. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1798. priv->prs_shadow[pe.index].finish = false;
  1799. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
  1800. MVPP2_PRS_RI_L3_PROTO_MASK);
  1801. mvpp2_prs_hw_write(priv, &pe);
  1802. /* Ethertype: IPv6 without options */
  1803. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1804. MVPP2_PE_LAST_FREE_TID);
  1805. if (tid < 0)
  1806. return tid;
  1807. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1808. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1809. pe.index = tid;
  1810. mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
  1811. /* Skip DIP of IPV6 header */
  1812. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
  1813. MVPP2_MAX_L3_ADDR_SIZE,
  1814. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1815. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
  1816. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
  1817. MVPP2_PRS_RI_L3_PROTO_MASK);
  1818. /* Set L3 offset */
  1819. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1820. MVPP2_ETH_TYPE_LEN,
  1821. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1822. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1823. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1824. priv->prs_shadow[pe.index].finish = false;
  1825. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
  1826. MVPP2_PRS_RI_L3_PROTO_MASK);
  1827. mvpp2_prs_hw_write(priv, &pe);
  1828. /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
  1829. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1830. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1831. pe.index = MVPP2_PE_ETH_TYPE_UN;
  1832. /* Unmask all ports */
  1833. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1834. /* Generate flow in the next iteration*/
  1835. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1836. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1837. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
  1838. MVPP2_PRS_RI_L3_PROTO_MASK);
  1839. /* Set L3 offset even it's unknown L3 */
  1840. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1841. MVPP2_ETH_TYPE_LEN,
  1842. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1843. /* Update shadow table and hw entry */
  1844. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1845. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1846. priv->prs_shadow[pe.index].finish = true;
  1847. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
  1848. MVPP2_PRS_RI_L3_PROTO_MASK);
  1849. mvpp2_prs_hw_write(priv, &pe);
  1850. return 0;
  1851. }
  1852. /* Parser default initialization */
  1853. static int mvpp2_prs_default_init(struct udevice *dev,
  1854. struct mvpp2 *priv)
  1855. {
  1856. int err, index, i;
  1857. /* Enable tcam table */
  1858. mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
  1859. /* Clear all tcam and sram entries */
  1860. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
  1861. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1862. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1863. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
  1864. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
  1865. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1866. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
  1867. }
  1868. /* Invalidate all tcam entries */
  1869. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
  1870. mvpp2_prs_hw_inv(priv, index);
  1871. priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
  1872. sizeof(struct mvpp2_prs_shadow),
  1873. GFP_KERNEL);
  1874. if (!priv->prs_shadow)
  1875. return -ENOMEM;
  1876. /* Always start from lookup = 0 */
  1877. for (index = 0; index < MVPP2_MAX_PORTS; index++)
  1878. mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
  1879. MVPP2_PRS_PORT_LU_MAX, 0);
  1880. mvpp2_prs_def_flow_init(priv);
  1881. mvpp2_prs_mh_init(priv);
  1882. mvpp2_prs_mac_init(priv);
  1883. err = mvpp2_prs_etype_init(priv);
  1884. if (err)
  1885. return err;
  1886. return 0;
  1887. }
  1888. /* Compare MAC DA with tcam entry data */
  1889. static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
  1890. const u8 *da, unsigned char *mask)
  1891. {
  1892. unsigned char tcam_byte, tcam_mask;
  1893. int index;
  1894. for (index = 0; index < ETH_ALEN; index++) {
  1895. mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
  1896. if (tcam_mask != mask[index])
  1897. return false;
  1898. if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
  1899. return false;
  1900. }
  1901. return true;
  1902. }
  1903. /* Find tcam entry with matched pair <MAC DA, port> */
  1904. static struct mvpp2_prs_entry *
  1905. mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
  1906. unsigned char *mask, int udf_type)
  1907. {
  1908. struct mvpp2_prs_entry *pe;
  1909. int tid;
  1910. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1911. if (!pe)
  1912. return NULL;
  1913. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1914. /* Go through the all entires with MVPP2_PRS_LU_MAC */
  1915. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1916. tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
  1917. unsigned int entry_pmap;
  1918. if (!priv->prs_shadow[tid].valid ||
  1919. (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
  1920. (priv->prs_shadow[tid].udf != udf_type))
  1921. continue;
  1922. pe->index = tid;
  1923. mvpp2_prs_hw_read(priv, pe);
  1924. entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
  1925. if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
  1926. entry_pmap == pmap)
  1927. return pe;
  1928. }
  1929. kfree(pe);
  1930. return NULL;
  1931. }
  1932. /* Update parser's mac da entry */
  1933. static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
  1934. const u8 *da, bool add)
  1935. {
  1936. struct mvpp2_prs_entry *pe;
  1937. unsigned int pmap, len, ri;
  1938. unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  1939. int tid;
  1940. /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
  1941. pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
  1942. MVPP2_PRS_UDF_MAC_DEF);
  1943. /* No such entry */
  1944. if (!pe) {
  1945. if (!add)
  1946. return 0;
  1947. /* Create new TCAM entry */
  1948. /* Find first range mac entry*/
  1949. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1950. tid <= MVPP2_PE_LAST_FREE_TID; tid++)
  1951. if (priv->prs_shadow[tid].valid &&
  1952. (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
  1953. (priv->prs_shadow[tid].udf ==
  1954. MVPP2_PRS_UDF_MAC_RANGE))
  1955. break;
  1956. /* Go through the all entries from first to last */
  1957. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1958. tid - 1);
  1959. if (tid < 0)
  1960. return tid;
  1961. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1962. if (!pe)
  1963. return -1;
  1964. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1965. pe->index = tid;
  1966. /* Mask all ports */
  1967. mvpp2_prs_tcam_port_map_set(pe, 0);
  1968. }
  1969. /* Update port mask */
  1970. mvpp2_prs_tcam_port_set(pe, port, add);
  1971. /* Invalidate the entry if no ports are left enabled */
  1972. pmap = mvpp2_prs_tcam_port_map_get(pe);
  1973. if (pmap == 0) {
  1974. if (add) {
  1975. kfree(pe);
  1976. return -1;
  1977. }
  1978. mvpp2_prs_hw_inv(priv, pe->index);
  1979. priv->prs_shadow[pe->index].valid = false;
  1980. kfree(pe);
  1981. return 0;
  1982. }
  1983. /* Continue - set next lookup */
  1984. mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
  1985. /* Set match on DA */
  1986. len = ETH_ALEN;
  1987. while (len--)
  1988. mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
  1989. /* Set result info bits */
  1990. ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
  1991. mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1992. MVPP2_PRS_RI_MAC_ME_MASK);
  1993. mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1994. MVPP2_PRS_RI_MAC_ME_MASK);
  1995. /* Shift to ethertype */
  1996. mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
  1997. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1998. /* Update shadow table and hw entry */
  1999. priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
  2000. mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
  2001. mvpp2_prs_hw_write(priv, pe);
  2002. kfree(pe);
  2003. return 0;
  2004. }
  2005. static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
  2006. {
  2007. int err;
  2008. /* Remove old parser entry */
  2009. err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
  2010. false);
  2011. if (err)
  2012. return err;
  2013. /* Add new parser entry */
  2014. err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
  2015. if (err)
  2016. return err;
  2017. /* Set addr in the device */
  2018. memcpy(port->dev_addr, da, ETH_ALEN);
  2019. return 0;
  2020. }
  2021. /* Set prs flow for the port */
  2022. static int mvpp2_prs_def_flow(struct mvpp2_port *port)
  2023. {
  2024. struct mvpp2_prs_entry *pe;
  2025. int tid;
  2026. pe = mvpp2_prs_flow_find(port->priv, port->id);
  2027. /* Such entry not exist */
  2028. if (!pe) {
  2029. /* Go through the all entires from last to first */
  2030. tid = mvpp2_prs_tcam_first_free(port->priv,
  2031. MVPP2_PE_LAST_FREE_TID,
  2032. MVPP2_PE_FIRST_FREE_TID);
  2033. if (tid < 0)
  2034. return tid;
  2035. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  2036. if (!pe)
  2037. return -ENOMEM;
  2038. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  2039. pe->index = tid;
  2040. /* Set flow ID*/
  2041. mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
  2042. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  2043. /* Update shadow table */
  2044. mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
  2045. }
  2046. mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
  2047. mvpp2_prs_hw_write(port->priv, pe);
  2048. kfree(pe);
  2049. return 0;
  2050. }
  2051. /* Classifier configuration routines */
  2052. /* Update classification flow table registers */
  2053. static void mvpp2_cls_flow_write(struct mvpp2 *priv,
  2054. struct mvpp2_cls_flow_entry *fe)
  2055. {
  2056. mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
  2057. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
  2058. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
  2059. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
  2060. }
  2061. /* Update classification lookup table register */
  2062. static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
  2063. struct mvpp2_cls_lookup_entry *le)
  2064. {
  2065. u32 val;
  2066. val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
  2067. mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
  2068. mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
  2069. }
  2070. /* Classifier default initialization */
  2071. static void mvpp2_cls_init(struct mvpp2 *priv)
  2072. {
  2073. struct mvpp2_cls_lookup_entry le;
  2074. struct mvpp2_cls_flow_entry fe;
  2075. int index;
  2076. /* Enable classifier */
  2077. mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
  2078. /* Clear classifier flow table */
  2079. memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
  2080. for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
  2081. fe.index = index;
  2082. mvpp2_cls_flow_write(priv, &fe);
  2083. }
  2084. /* Clear classifier lookup table */
  2085. le.data = 0;
  2086. for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
  2087. le.lkpid = index;
  2088. le.way = 0;
  2089. mvpp2_cls_lookup_write(priv, &le);
  2090. le.way = 1;
  2091. mvpp2_cls_lookup_write(priv, &le);
  2092. }
  2093. }
  2094. static void mvpp2_cls_port_config(struct mvpp2_port *port)
  2095. {
  2096. struct mvpp2_cls_lookup_entry le;
  2097. u32 val;
  2098. /* Set way for the port */
  2099. val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
  2100. val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
  2101. mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
  2102. /* Pick the entry to be accessed in lookup ID decoding table
  2103. * according to the way and lkpid.
  2104. */
  2105. le.lkpid = port->id;
  2106. le.way = 0;
  2107. le.data = 0;
  2108. /* Set initial CPU queue for receiving packets */
  2109. le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
  2110. le.data |= port->first_rxq;
  2111. /* Disable classification engines */
  2112. le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
  2113. /* Update lookup ID table entry */
  2114. mvpp2_cls_lookup_write(port->priv, &le);
  2115. }
  2116. /* Set CPU queue number for oversize packets */
  2117. static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
  2118. {
  2119. u32 val;
  2120. mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
  2121. port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
  2122. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
  2123. (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
  2124. val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
  2125. val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
  2126. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
  2127. }
  2128. /* Buffer Manager configuration routines */
  2129. /* Create pool */
  2130. static int mvpp2_bm_pool_create(struct udevice *dev,
  2131. struct mvpp2 *priv,
  2132. struct mvpp2_bm_pool *bm_pool, int size)
  2133. {
  2134. u32 val;
  2135. /* Number of buffer pointers must be a multiple of 16, as per
  2136. * hardware constraints
  2137. */
  2138. if (!IS_ALIGNED(size, 16))
  2139. return -EINVAL;
  2140. bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
  2141. bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
  2142. if (!bm_pool->virt_addr)
  2143. return -ENOMEM;
  2144. if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
  2145. MVPP2_BM_POOL_PTR_ALIGN)) {
  2146. dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
  2147. bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
  2148. return -ENOMEM;
  2149. }
  2150. mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
  2151. lower_32_bits(bm_pool->dma_addr));
  2152. if (priv->hw_version == MVPP22)
  2153. mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
  2154. (upper_32_bits(bm_pool->dma_addr) &
  2155. MVPP22_BM_POOL_BASE_HIGH_MASK));
  2156. mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
  2157. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2158. val |= MVPP2_BM_START_MASK;
  2159. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2160. bm_pool->type = MVPP2_BM_FREE;
  2161. bm_pool->size = size;
  2162. bm_pool->pkt_size = 0;
  2163. bm_pool->buf_num = 0;
  2164. return 0;
  2165. }
  2166. /* Set pool buffer size */
  2167. static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
  2168. struct mvpp2_bm_pool *bm_pool,
  2169. int buf_size)
  2170. {
  2171. u32 val;
  2172. bm_pool->buf_size = buf_size;
  2173. val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
  2174. mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
  2175. }
  2176. /* Free all buffers from the pool */
  2177. static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
  2178. struct mvpp2_bm_pool *bm_pool)
  2179. {
  2180. int i;
  2181. for (i = 0; i < bm_pool->buf_num; i++) {
  2182. /* Allocate buffer back from the buffer manager */
  2183. mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
  2184. }
  2185. bm_pool->buf_num = 0;
  2186. }
  2187. /* Cleanup pool */
  2188. static int mvpp2_bm_pool_destroy(struct udevice *dev,
  2189. struct mvpp2 *priv,
  2190. struct mvpp2_bm_pool *bm_pool)
  2191. {
  2192. u32 val;
  2193. mvpp2_bm_bufs_free(dev, priv, bm_pool);
  2194. if (bm_pool->buf_num) {
  2195. dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
  2196. return 0;
  2197. }
  2198. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2199. val |= MVPP2_BM_STOP_MASK;
  2200. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2201. return 0;
  2202. }
  2203. static int mvpp2_bm_pools_init(struct udevice *dev,
  2204. struct mvpp2 *priv)
  2205. {
  2206. int i, err, size;
  2207. struct mvpp2_bm_pool *bm_pool;
  2208. /* Create all pools with maximum size */
  2209. size = MVPP2_BM_POOL_SIZE_MAX;
  2210. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2211. bm_pool = &priv->bm_pools[i];
  2212. bm_pool->id = i;
  2213. err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
  2214. if (err)
  2215. goto err_unroll_pools;
  2216. mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
  2217. }
  2218. return 0;
  2219. err_unroll_pools:
  2220. dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
  2221. for (i = i - 1; i >= 0; i--)
  2222. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  2223. return err;
  2224. }
  2225. static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
  2226. {
  2227. int i, err;
  2228. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2229. /* Mask BM all interrupts */
  2230. mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
  2231. /* Clear BM cause register */
  2232. mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
  2233. }
  2234. /* Allocate and initialize BM pools */
  2235. priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
  2236. sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
  2237. if (!priv->bm_pools)
  2238. return -ENOMEM;
  2239. err = mvpp2_bm_pools_init(dev, priv);
  2240. if (err < 0)
  2241. return err;
  2242. return 0;
  2243. }
  2244. /* Attach long pool to rxq */
  2245. static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
  2246. int lrxq, int long_pool)
  2247. {
  2248. u32 val, mask;
  2249. int prxq;
  2250. /* Get queue physical ID */
  2251. prxq = port->rxqs[lrxq]->id;
  2252. if (port->priv->hw_version == MVPP21)
  2253. mask = MVPP21_RXQ_POOL_LONG_MASK;
  2254. else
  2255. mask = MVPP22_RXQ_POOL_LONG_MASK;
  2256. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  2257. val &= ~mask;
  2258. val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
  2259. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  2260. }
  2261. /* Set pool number in a BM cookie */
  2262. static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
  2263. {
  2264. u32 bm;
  2265. bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
  2266. bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
  2267. return bm;
  2268. }
  2269. /* Get pool number from a BM cookie */
  2270. static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
  2271. {
  2272. return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
  2273. }
  2274. /* Release buffer to BM */
  2275. static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
  2276. dma_addr_t buf_dma_addr,
  2277. unsigned long buf_phys_addr)
  2278. {
  2279. if (port->priv->hw_version == MVPP22) {
  2280. u32 val = 0;
  2281. if (sizeof(dma_addr_t) == 8)
  2282. val |= upper_32_bits(buf_dma_addr) &
  2283. MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
  2284. if (sizeof(phys_addr_t) == 8)
  2285. val |= (upper_32_bits(buf_phys_addr)
  2286. << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
  2287. MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
  2288. mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
  2289. }
  2290. /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
  2291. * returned in the "cookie" field of the RX
  2292. * descriptor. Instead of storing the virtual address, we
  2293. * store the physical address
  2294. */
  2295. mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
  2296. mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
  2297. }
  2298. /* Refill BM pool */
  2299. static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  2300. dma_addr_t dma_addr,
  2301. phys_addr_t phys_addr)
  2302. {
  2303. int pool = mvpp2_bm_cookie_pool_get(bm);
  2304. mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
  2305. }
  2306. /* Allocate buffers for the pool */
  2307. static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
  2308. struct mvpp2_bm_pool *bm_pool, int buf_num)
  2309. {
  2310. int i;
  2311. if (buf_num < 0 ||
  2312. (buf_num + bm_pool->buf_num > bm_pool->size)) {
  2313. netdev_err(port->dev,
  2314. "cannot allocate %d buffers for pool %d\n",
  2315. buf_num, bm_pool->id);
  2316. return 0;
  2317. }
  2318. for (i = 0; i < buf_num; i++) {
  2319. mvpp2_bm_pool_put(port, bm_pool->id,
  2320. (dma_addr_t)buffer_loc.rx_buffer[i],
  2321. (unsigned long)buffer_loc.rx_buffer[i]);
  2322. }
  2323. /* Update BM driver with number of buffers added to pool */
  2324. bm_pool->buf_num += i;
  2325. return i;
  2326. }
  2327. /* Notify the driver that BM pool is being used as specific type and return the
  2328. * pool pointer on success
  2329. */
  2330. static struct mvpp2_bm_pool *
  2331. mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
  2332. int pkt_size)
  2333. {
  2334. struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
  2335. int num;
  2336. if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
  2337. netdev_err(port->dev, "mixing pool types is forbidden\n");
  2338. return NULL;
  2339. }
  2340. if (new_pool->type == MVPP2_BM_FREE)
  2341. new_pool->type = type;
  2342. /* Allocate buffers in case BM pool is used as long pool, but packet
  2343. * size doesn't match MTU or BM pool hasn't being used yet
  2344. */
  2345. if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
  2346. (new_pool->pkt_size == 0)) {
  2347. int pkts_num;
  2348. /* Set default buffer number or free all the buffers in case
  2349. * the pool is not empty
  2350. */
  2351. pkts_num = new_pool->buf_num;
  2352. if (pkts_num == 0)
  2353. pkts_num = type == MVPP2_BM_SWF_LONG ?
  2354. MVPP2_BM_LONG_BUF_NUM :
  2355. MVPP2_BM_SHORT_BUF_NUM;
  2356. else
  2357. mvpp2_bm_bufs_free(NULL,
  2358. port->priv, new_pool);
  2359. new_pool->pkt_size = pkt_size;
  2360. /* Allocate buffers for this pool */
  2361. num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
  2362. if (num != pkts_num) {
  2363. dev_err(dev, "pool %d: %d of %d allocated\n",
  2364. new_pool->id, num, pkts_num);
  2365. return NULL;
  2366. }
  2367. }
  2368. return new_pool;
  2369. }
  2370. /* Initialize pools for swf */
  2371. static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
  2372. {
  2373. int rxq;
  2374. if (!port->pool_long) {
  2375. port->pool_long =
  2376. mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
  2377. MVPP2_BM_SWF_LONG,
  2378. port->pkt_size);
  2379. if (!port->pool_long)
  2380. return -ENOMEM;
  2381. port->pool_long->port_map |= (1 << port->id);
  2382. for (rxq = 0; rxq < rxq_number; rxq++)
  2383. mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
  2384. }
  2385. return 0;
  2386. }
  2387. /* Port configuration routines */
  2388. static void mvpp2_port_mii_set(struct mvpp2_port *port)
  2389. {
  2390. u32 val;
  2391. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2392. switch (port->phy_interface) {
  2393. case PHY_INTERFACE_MODE_SGMII:
  2394. val |= MVPP2_GMAC_INBAND_AN_MASK;
  2395. break;
  2396. case PHY_INTERFACE_MODE_RGMII:
  2397. case PHY_INTERFACE_MODE_RGMII_ID:
  2398. val |= MVPP2_GMAC_PORT_RGMII_MASK;
  2399. default:
  2400. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2401. }
  2402. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2403. }
  2404. static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
  2405. {
  2406. u32 val;
  2407. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2408. val |= MVPP2_GMAC_FC_ADV_EN;
  2409. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2410. }
  2411. static void mvpp2_port_enable(struct mvpp2_port *port)
  2412. {
  2413. u32 val;
  2414. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2415. val |= MVPP2_GMAC_PORT_EN_MASK;
  2416. val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
  2417. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2418. }
  2419. static void mvpp2_port_disable(struct mvpp2_port *port)
  2420. {
  2421. u32 val;
  2422. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2423. val &= ~(MVPP2_GMAC_PORT_EN_MASK);
  2424. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2425. }
  2426. /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
  2427. static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
  2428. {
  2429. u32 val;
  2430. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
  2431. ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2432. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2433. }
  2434. /* Configure loopback port */
  2435. static void mvpp2_port_loopback_set(struct mvpp2_port *port)
  2436. {
  2437. u32 val;
  2438. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2439. if (port->speed == 1000)
  2440. val |= MVPP2_GMAC_GMII_LB_EN_MASK;
  2441. else
  2442. val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
  2443. if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
  2444. val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  2445. else
  2446. val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
  2447. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2448. }
  2449. static void mvpp2_port_reset(struct mvpp2_port *port)
  2450. {
  2451. u32 val;
  2452. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2453. ~MVPP2_GMAC_PORT_RESET_MASK;
  2454. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2455. while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2456. MVPP2_GMAC_PORT_RESET_MASK)
  2457. continue;
  2458. }
  2459. /* Change maximum receive size of the port */
  2460. static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
  2461. {
  2462. u32 val;
  2463. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2464. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2465. val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
  2466. MVPP2_GMAC_MAX_RX_SIZE_OFFS);
  2467. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2468. }
  2469. /* PPv2.2 GoP/GMAC config */
  2470. /* Set the MAC to reset or exit from reset */
  2471. static int gop_gmac_reset(struct mvpp2_port *port, int reset)
  2472. {
  2473. u32 val;
  2474. /* read - modify - write */
  2475. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2476. if (reset)
  2477. val |= MVPP2_GMAC_PORT_RESET_MASK;
  2478. else
  2479. val &= ~MVPP2_GMAC_PORT_RESET_MASK;
  2480. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2481. return 0;
  2482. }
  2483. /*
  2484. * gop_gpcs_mode_cfg
  2485. *
  2486. * Configure port to working with Gig PCS or don't.
  2487. */
  2488. static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
  2489. {
  2490. u32 val;
  2491. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2492. if (en)
  2493. val |= MVPP2_GMAC_PCS_ENABLE_MASK;
  2494. else
  2495. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2496. /* enable / disable PCS on this port */
  2497. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2498. return 0;
  2499. }
  2500. static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
  2501. {
  2502. u32 val;
  2503. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2504. if (en)
  2505. val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2506. else
  2507. val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2508. /* enable / disable PCS on this port */
  2509. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2510. return 0;
  2511. }
  2512. static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
  2513. {
  2514. u32 val, thresh;
  2515. /*
  2516. * Configure minimal level of the Tx FIFO before the lower part
  2517. * starts to read a packet
  2518. */
  2519. thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  2520. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2521. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2522. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2523. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2524. /* Disable bypass of sync module */
  2525. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2526. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2527. /* configure DP clock select according to mode */
  2528. val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2529. /* configure QSGMII bypass according to mode */
  2530. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2531. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2532. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2533. /*
  2534. * Configure GIG MAC to 1000Base-X mode connected to a fiber
  2535. * transceiver
  2536. */
  2537. val |= MVPP2_GMAC_PORT_TYPE_MASK;
  2538. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2539. /* configure AN 0x9268 */
  2540. val = MVPP2_GMAC_EN_PCS_AN |
  2541. MVPP2_GMAC_AN_BYPASS_EN |
  2542. MVPP2_GMAC_CONFIG_MII_SPEED |
  2543. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2544. MVPP2_GMAC_FC_ADV_EN |
  2545. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2546. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2547. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2548. }
  2549. static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
  2550. {
  2551. u32 val, thresh;
  2552. /*
  2553. * Configure minimal level of the Tx FIFO before the lower part
  2554. * starts to read a packet
  2555. */
  2556. thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
  2557. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2558. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2559. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2560. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2561. /* Disable bypass of sync module */
  2562. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2563. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2564. /* configure DP clock select according to mode */
  2565. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2566. /* configure QSGMII bypass according to mode */
  2567. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2568. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2569. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2570. /* configure GIG MAC to SGMII mode */
  2571. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2572. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2573. /* configure AN */
  2574. val = MVPP2_GMAC_EN_PCS_AN |
  2575. MVPP2_GMAC_AN_BYPASS_EN |
  2576. MVPP2_GMAC_AN_SPEED_EN |
  2577. MVPP2_GMAC_EN_FC_AN |
  2578. MVPP2_GMAC_AN_DUPLEX_EN |
  2579. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2580. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2581. }
  2582. static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
  2583. {
  2584. u32 val, thresh;
  2585. /*
  2586. * Configure minimal level of the Tx FIFO before the lower part
  2587. * starts to read a packet
  2588. */
  2589. thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
  2590. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2591. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2592. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2593. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2594. /* Disable bypass of sync module */
  2595. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2596. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2597. /* configure DP clock select according to mode */
  2598. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2599. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2600. val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
  2601. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2602. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2603. /* configure GIG MAC to SGMII mode */
  2604. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2605. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2606. /* configure AN 0xb8e8 */
  2607. val = MVPP2_GMAC_AN_BYPASS_EN |
  2608. MVPP2_GMAC_AN_SPEED_EN |
  2609. MVPP2_GMAC_EN_FC_AN |
  2610. MVPP2_GMAC_AN_DUPLEX_EN |
  2611. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2612. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2613. }
  2614. /* Set the internal mux's to the required MAC in the GOP */
  2615. static int gop_gmac_mode_cfg(struct mvpp2_port *port)
  2616. {
  2617. u32 val;
  2618. /* Set TX FIFO thresholds */
  2619. switch (port->phy_interface) {
  2620. case PHY_INTERFACE_MODE_SGMII:
  2621. if (port->phy_speed == 2500)
  2622. gop_gmac_sgmii2_5_cfg(port);
  2623. else
  2624. gop_gmac_sgmii_cfg(port);
  2625. break;
  2626. case PHY_INTERFACE_MODE_RGMII:
  2627. case PHY_INTERFACE_MODE_RGMII_ID:
  2628. gop_gmac_rgmii_cfg(port);
  2629. break;
  2630. default:
  2631. return -1;
  2632. }
  2633. /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
  2634. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2635. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2636. val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
  2637. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2638. /* PeriodicXonEn disable */
  2639. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2640. val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2641. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2642. return 0;
  2643. }
  2644. static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
  2645. {
  2646. u32 val;
  2647. /* relevant only for MAC0 (XLG0 and GMAC0) */
  2648. if (port->gop_id > 0)
  2649. return;
  2650. /* configure 1Gig MAC mode */
  2651. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2652. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2653. val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
  2654. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2655. }
  2656. static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
  2657. {
  2658. u32 val;
  2659. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2660. if (reset)
  2661. val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
  2662. else
  2663. val |= MVPP2_GMAC_SGMII_MODE_MASK;
  2664. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2665. return 0;
  2666. }
  2667. /* Set the internal mux's to the required PCS in the PI */
  2668. static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
  2669. {
  2670. u32 val;
  2671. int lane;
  2672. switch (num_of_lanes) {
  2673. case 1:
  2674. lane = 0;
  2675. break;
  2676. case 2:
  2677. lane = 1;
  2678. break;
  2679. case 4:
  2680. lane = 2;
  2681. break;
  2682. default:
  2683. return -1;
  2684. }
  2685. /* configure XG MAC mode */
  2686. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2687. val &= ~MVPP22_XPCS_PCSMODE_MASK;
  2688. val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
  2689. val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
  2690. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2691. return 0;
  2692. }
  2693. static int gop_mpcs_mode(struct mvpp2_port *port)
  2694. {
  2695. u32 val;
  2696. /* configure PCS40G COMMON CONTROL */
  2697. val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2698. val &= ~FORWARD_ERROR_CORRECTION_MASK;
  2699. writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2700. /* configure PCS CLOCK RESET */
  2701. val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
  2702. val &= ~CLK_DIVISION_RATIO_MASK;
  2703. val |= 1 << CLK_DIVISION_RATIO_OFFS;
  2704. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2705. val &= ~CLK_DIV_PHASE_SET_MASK;
  2706. val |= MAC_CLK_RESET_MASK;
  2707. val |= RX_SD_CLK_RESET_MASK;
  2708. val |= TX_SD_CLK_RESET_MASK;
  2709. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2710. return 0;
  2711. }
  2712. /* Set the internal mux's to the required MAC in the GOP */
  2713. static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
  2714. {
  2715. u32 val;
  2716. /* configure 10G MAC mode */
  2717. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2718. val |= MVPP22_XLG_RX_FC_EN;
  2719. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2720. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2721. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2722. val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
  2723. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2724. /* read - modify - write */
  2725. val = readl(port->base + MVPP22_XLG_CTRL4_REG);
  2726. val &= ~MVPP22_XLG_MODE_DMA_1G;
  2727. val |= MVPP22_XLG_FORWARD_PFC_EN;
  2728. val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
  2729. val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
  2730. writel(val, port->base + MVPP22_XLG_CTRL4_REG);
  2731. /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
  2732. val = readl(port->base + MVPP22_XLG_CTRL1_REG);
  2733. val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
  2734. val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
  2735. writel(val, port->base + MVPP22_XLG_CTRL1_REG);
  2736. /* unmask link change interrupt */
  2737. val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2738. val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
  2739. val |= 1; /* unmask summary bit */
  2740. writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2741. return 0;
  2742. }
  2743. /* Set PCS to reset or exit from reset */
  2744. static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
  2745. {
  2746. u32 val;
  2747. /* read - modify - write */
  2748. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2749. if (reset)
  2750. val &= ~MVPP22_XPCS_PCSRESET;
  2751. else
  2752. val |= MVPP22_XPCS_PCSRESET;
  2753. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2754. return 0;
  2755. }
  2756. /* Set the MAC to reset or exit from reset */
  2757. static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
  2758. {
  2759. u32 val;
  2760. /* read - modify - write */
  2761. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2762. if (reset)
  2763. val &= ~MVPP22_XLG_MAC_RESETN;
  2764. else
  2765. val |= MVPP22_XLG_MAC_RESETN;
  2766. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2767. return 0;
  2768. }
  2769. /*
  2770. * gop_port_init
  2771. *
  2772. * Init physical port. Configures the port mode and all it's elements
  2773. * accordingly.
  2774. * Does not verify that the selected mode/port number is valid at the
  2775. * core level.
  2776. */
  2777. static int gop_port_init(struct mvpp2_port *port)
  2778. {
  2779. int mac_num = port->gop_id;
  2780. int num_of_act_lanes;
  2781. if (mac_num >= MVPP22_GOP_MAC_NUM) {
  2782. netdev_err(NULL, "%s: illegal port number %d", __func__,
  2783. mac_num);
  2784. return -1;
  2785. }
  2786. switch (port->phy_interface) {
  2787. case PHY_INTERFACE_MODE_RGMII:
  2788. case PHY_INTERFACE_MODE_RGMII_ID:
  2789. gop_gmac_reset(port, 1);
  2790. /* configure PCS */
  2791. gop_gpcs_mode_cfg(port, 0);
  2792. gop_bypass_clk_cfg(port, 1);
  2793. /* configure MAC */
  2794. gop_gmac_mode_cfg(port);
  2795. /* pcs unreset */
  2796. gop_gpcs_reset(port, 0);
  2797. /* mac unreset */
  2798. gop_gmac_reset(port, 0);
  2799. break;
  2800. case PHY_INTERFACE_MODE_SGMII:
  2801. /* configure PCS */
  2802. gop_gpcs_mode_cfg(port, 1);
  2803. /* configure MAC */
  2804. gop_gmac_mode_cfg(port);
  2805. /* select proper Mac mode */
  2806. gop_xlg_2_gig_mac_cfg(port);
  2807. /* pcs unreset */
  2808. gop_gpcs_reset(port, 0);
  2809. /* mac unreset */
  2810. gop_gmac_reset(port, 0);
  2811. break;
  2812. case PHY_INTERFACE_MODE_SFI:
  2813. num_of_act_lanes = 2;
  2814. mac_num = 0;
  2815. /* configure PCS */
  2816. gop_xpcs_mode(port, num_of_act_lanes);
  2817. gop_mpcs_mode(port);
  2818. /* configure MAC */
  2819. gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
  2820. /* pcs unreset */
  2821. gop_xpcs_reset(port, 0);
  2822. /* mac unreset */
  2823. gop_xlg_mac_reset(port, 0);
  2824. break;
  2825. default:
  2826. netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
  2827. __func__, port->phy_interface);
  2828. return -1;
  2829. }
  2830. return 0;
  2831. }
  2832. static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
  2833. {
  2834. u32 val;
  2835. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2836. if (enable) {
  2837. /* Enable port and MIB counters update */
  2838. val |= MVPP22_XLG_PORT_EN;
  2839. val &= ~MVPP22_XLG_MIBCNT_DIS;
  2840. } else {
  2841. /* Disable port */
  2842. val &= ~MVPP22_XLG_PORT_EN;
  2843. }
  2844. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2845. }
  2846. static void gop_port_enable(struct mvpp2_port *port, int enable)
  2847. {
  2848. switch (port->phy_interface) {
  2849. case PHY_INTERFACE_MODE_RGMII:
  2850. case PHY_INTERFACE_MODE_RGMII_ID:
  2851. case PHY_INTERFACE_MODE_SGMII:
  2852. if (enable)
  2853. mvpp2_port_enable(port);
  2854. else
  2855. mvpp2_port_disable(port);
  2856. break;
  2857. case PHY_INTERFACE_MODE_SFI:
  2858. gop_xlg_mac_port_enable(port, enable);
  2859. break;
  2860. default:
  2861. netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
  2862. port->phy_interface);
  2863. return;
  2864. }
  2865. }
  2866. /* RFU1 functions */
  2867. static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
  2868. {
  2869. return readl(priv->rfu1_base + offset);
  2870. }
  2871. static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
  2872. {
  2873. writel(data, priv->rfu1_base + offset);
  2874. }
  2875. static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
  2876. {
  2877. u32 val = 0;
  2878. if (gop_id == 2) {
  2879. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2880. val |= MV_NETC_GE_MAC2_SGMII;
  2881. }
  2882. if (gop_id == 3) {
  2883. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2884. val |= MV_NETC_GE_MAC3_SGMII;
  2885. else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
  2886. phy_type == PHY_INTERFACE_MODE_RGMII_ID)
  2887. val |= MV_NETC_GE_MAC3_RGMII;
  2888. }
  2889. return val;
  2890. }
  2891. static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
  2892. {
  2893. u32 reg;
  2894. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2895. reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
  2896. val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
  2897. val &= NETC_PORTS_ACTIVE_MASK(gop_id);
  2898. reg |= val;
  2899. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2900. }
  2901. static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
  2902. {
  2903. u32 reg;
  2904. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2905. reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
  2906. val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
  2907. val &= NETC_GBE_PORT1_MII_MODE_MASK;
  2908. reg |= val;
  2909. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2910. }
  2911. static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
  2912. {
  2913. u32 reg;
  2914. reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
  2915. reg &= ~NETC_GOP_SOFT_RESET_MASK;
  2916. val <<= NETC_GOP_SOFT_RESET_OFFS;
  2917. val &= NETC_GOP_SOFT_RESET_MASK;
  2918. reg |= val;
  2919. gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
  2920. }
  2921. static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
  2922. {
  2923. u32 reg;
  2924. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2925. reg &= ~NETC_CLK_DIV_PHASE_MASK;
  2926. val <<= NETC_CLK_DIV_PHASE_OFFS;
  2927. val &= NETC_CLK_DIV_PHASE_MASK;
  2928. reg |= val;
  2929. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2930. }
  2931. static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
  2932. {
  2933. u32 reg;
  2934. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2935. reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
  2936. val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
  2937. val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
  2938. reg |= val;
  2939. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2940. }
  2941. static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
  2942. u32 val)
  2943. {
  2944. u32 reg, mask, offset;
  2945. if (gop_id == 2) {
  2946. mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
  2947. offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
  2948. } else {
  2949. mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
  2950. offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
  2951. }
  2952. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2953. reg &= ~mask;
  2954. val <<= offset;
  2955. val &= mask;
  2956. reg |= val;
  2957. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2958. }
  2959. static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
  2960. {
  2961. u32 reg;
  2962. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2963. reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
  2964. val <<= NETC_BUS_WIDTH_SELECT_OFFS;
  2965. val &= NETC_BUS_WIDTH_SELECT_MASK;
  2966. reg |= val;
  2967. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2968. }
  2969. static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
  2970. {
  2971. u32 reg;
  2972. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2973. reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
  2974. val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
  2975. val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
  2976. reg |= val;
  2977. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2978. }
  2979. static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
  2980. enum mv_netc_phase phase)
  2981. {
  2982. switch (phase) {
  2983. case MV_NETC_FIRST_PHASE:
  2984. /* Set Bus Width to HB mode = 1 */
  2985. gop_netc_bus_width_select(priv, 1);
  2986. /* Select RGMII mode */
  2987. gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
  2988. break;
  2989. case MV_NETC_SECOND_PHASE:
  2990. /* De-assert the relevant port HB reset */
  2991. gop_netc_port_rf_reset(priv, gop_id, 1);
  2992. break;
  2993. }
  2994. }
  2995. static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
  2996. enum mv_netc_phase phase)
  2997. {
  2998. switch (phase) {
  2999. case MV_NETC_FIRST_PHASE:
  3000. /* Set Bus Width to HB mode = 1 */
  3001. gop_netc_bus_width_select(priv, 1);
  3002. /* Select SGMII mode */
  3003. if (gop_id >= 1) {
  3004. gop_netc_gbe_sgmii_mode_select(priv, gop_id,
  3005. MV_NETC_GBE_SGMII);
  3006. }
  3007. /* Configure the sample stages */
  3008. gop_netc_sample_stages_timing(priv, 0);
  3009. /* Configure the ComPhy Selector */
  3010. /* gop_netc_com_phy_selector_config(netComplex); */
  3011. break;
  3012. case MV_NETC_SECOND_PHASE:
  3013. /* De-assert the relevant port HB reset */
  3014. gop_netc_port_rf_reset(priv, gop_id, 1);
  3015. break;
  3016. }
  3017. }
  3018. static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
  3019. {
  3020. u32 c = priv->netc_config;
  3021. if (c & MV_NETC_GE_MAC2_SGMII)
  3022. gop_netc_mac_to_sgmii(priv, 2, phase);
  3023. else
  3024. gop_netc_mac_to_xgmii(priv, 2, phase);
  3025. if (c & MV_NETC_GE_MAC3_SGMII) {
  3026. gop_netc_mac_to_sgmii(priv, 3, phase);
  3027. } else {
  3028. gop_netc_mac_to_xgmii(priv, 3, phase);
  3029. if (c & MV_NETC_GE_MAC3_RGMII)
  3030. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
  3031. else
  3032. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
  3033. }
  3034. /* Activate gop ports 0, 2, 3 */
  3035. gop_netc_active_port(priv, 0, 1);
  3036. gop_netc_active_port(priv, 2, 1);
  3037. gop_netc_active_port(priv, 3, 1);
  3038. if (phase == MV_NETC_SECOND_PHASE) {
  3039. /* Enable the GOP internal clock logic */
  3040. gop_netc_gop_clock_logic_set(priv, 1);
  3041. /* De-assert GOP unit reset */
  3042. gop_netc_gop_reset(priv, 1);
  3043. }
  3044. return 0;
  3045. }
  3046. /* Set defaults to the MVPP2 port */
  3047. static void mvpp2_defaults_set(struct mvpp2_port *port)
  3048. {
  3049. int tx_port_num, val, queue, ptxq, lrxq;
  3050. if (port->priv->hw_version == MVPP21) {
  3051. /* Configure port to loopback if needed */
  3052. if (port->flags & MVPP2_F_LOOPBACK)
  3053. mvpp2_port_loopback_set(port);
  3054. /* Update TX FIFO MIN Threshold */
  3055. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3056. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  3057. /* Min. TX threshold must be less than minimal packet length */
  3058. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
  3059. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3060. }
  3061. /* Disable Legacy WRR, Disable EJP, Release from reset */
  3062. tx_port_num = mvpp2_egress_port(port);
  3063. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
  3064. tx_port_num);
  3065. mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
  3066. /* Close bandwidth for all queues */
  3067. for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
  3068. ptxq = mvpp2_txq_phys(port->id, queue);
  3069. mvpp2_write(port->priv,
  3070. MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
  3071. }
  3072. /* Set refill period to 1 usec, refill tokens
  3073. * and bucket size to maximum
  3074. */
  3075. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
  3076. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
  3077. val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
  3078. val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
  3079. val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
  3080. mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
  3081. val = MVPP2_TXP_TOKEN_SIZE_MAX;
  3082. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3083. /* Set MaximumLowLatencyPacketSize value to 256 */
  3084. mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
  3085. MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
  3086. MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
  3087. /* Enable Rx cache snoop */
  3088. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3089. queue = port->rxqs[lrxq]->id;
  3090. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3091. val |= MVPP2_SNOOP_PKT_SIZE_MASK |
  3092. MVPP2_SNOOP_BUF_HDR_MASK;
  3093. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3094. }
  3095. }
  3096. /* Enable/disable receiving packets */
  3097. static void mvpp2_ingress_enable(struct mvpp2_port *port)
  3098. {
  3099. u32 val;
  3100. int lrxq, queue;
  3101. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3102. queue = port->rxqs[lrxq]->id;
  3103. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3104. val &= ~MVPP2_RXQ_DISABLE_MASK;
  3105. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3106. }
  3107. }
  3108. static void mvpp2_ingress_disable(struct mvpp2_port *port)
  3109. {
  3110. u32 val;
  3111. int lrxq, queue;
  3112. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3113. queue = port->rxqs[lrxq]->id;
  3114. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3115. val |= MVPP2_RXQ_DISABLE_MASK;
  3116. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3117. }
  3118. }
  3119. /* Enable transmit via physical egress queue
  3120. * - HW starts take descriptors from DRAM
  3121. */
  3122. static void mvpp2_egress_enable(struct mvpp2_port *port)
  3123. {
  3124. u32 qmap;
  3125. int queue;
  3126. int tx_port_num = mvpp2_egress_port(port);
  3127. /* Enable all initialized TXs. */
  3128. qmap = 0;
  3129. for (queue = 0; queue < txq_number; queue++) {
  3130. struct mvpp2_tx_queue *txq = port->txqs[queue];
  3131. if (txq->descs != NULL)
  3132. qmap |= (1 << queue);
  3133. }
  3134. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3135. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
  3136. }
  3137. /* Disable transmit via physical egress queue
  3138. * - HW doesn't take descriptors from DRAM
  3139. */
  3140. static void mvpp2_egress_disable(struct mvpp2_port *port)
  3141. {
  3142. u32 reg_data;
  3143. int delay;
  3144. int tx_port_num = mvpp2_egress_port(port);
  3145. /* Issue stop command for active channels only */
  3146. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3147. reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
  3148. MVPP2_TXP_SCHED_ENQ_MASK;
  3149. if (reg_data != 0)
  3150. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
  3151. (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
  3152. /* Wait for all Tx activity to terminate. */
  3153. delay = 0;
  3154. do {
  3155. if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
  3156. netdev_warn(port->dev,
  3157. "Tx stop timed out, status=0x%08x\n",
  3158. reg_data);
  3159. break;
  3160. }
  3161. mdelay(1);
  3162. delay++;
  3163. /* Check port TX Command register that all
  3164. * Tx queues are stopped
  3165. */
  3166. reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
  3167. } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
  3168. }
  3169. /* Rx descriptors helper methods */
  3170. /* Get number of Rx descriptors occupied by received packets */
  3171. static inline int
  3172. mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
  3173. {
  3174. u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
  3175. return val & MVPP2_RXQ_OCCUPIED_MASK;
  3176. }
  3177. /* Update Rx queue status with the number of occupied and available
  3178. * Rx descriptor slots.
  3179. */
  3180. static inline void
  3181. mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
  3182. int used_count, int free_count)
  3183. {
  3184. /* Decrement the number of used descriptors and increment count
  3185. * increment the number of free descriptors.
  3186. */
  3187. u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
  3188. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
  3189. }
  3190. /* Get pointer to next RX descriptor to be processed by SW */
  3191. static inline struct mvpp2_rx_desc *
  3192. mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
  3193. {
  3194. int rx_desc = rxq->next_desc_to_proc;
  3195. rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
  3196. prefetch(rxq->descs + rxq->next_desc_to_proc);
  3197. return rxq->descs + rx_desc;
  3198. }
  3199. /* Set rx queue offset */
  3200. static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
  3201. int prxq, int offset)
  3202. {
  3203. u32 val;
  3204. /* Convert offset from bytes to units of 32 bytes */
  3205. offset = offset >> 5;
  3206. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  3207. val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
  3208. /* Offset is in */
  3209. val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
  3210. MVPP2_RXQ_PACKET_OFFSET_MASK);
  3211. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  3212. }
  3213. /* Obtain BM cookie information from descriptor */
  3214. static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
  3215. struct mvpp2_rx_desc *rx_desc)
  3216. {
  3217. int cpu = smp_processor_id();
  3218. int pool;
  3219. pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
  3220. MVPP2_RXD_BM_POOL_ID_MASK) >>
  3221. MVPP2_RXD_BM_POOL_ID_OFFS;
  3222. return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
  3223. ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
  3224. }
  3225. /* Tx descriptors helper methods */
  3226. /* Get number of Tx descriptors waiting to be transmitted by HW */
  3227. static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
  3228. struct mvpp2_tx_queue *txq)
  3229. {
  3230. u32 val;
  3231. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3232. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3233. return val & MVPP2_TXQ_PENDING_MASK;
  3234. }
  3235. /* Get pointer to next Tx descriptor to be processed (send) by HW */
  3236. static struct mvpp2_tx_desc *
  3237. mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
  3238. {
  3239. int tx_desc = txq->next_desc_to_proc;
  3240. txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
  3241. return txq->descs + tx_desc;
  3242. }
  3243. /* Update HW with number of aggregated Tx descriptors to be sent */
  3244. static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
  3245. {
  3246. /* aggregated access - relevant TXQ number is written in TX desc */
  3247. mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
  3248. }
  3249. /* Get number of sent descriptors and decrement counter.
  3250. * The number of sent descriptors is returned.
  3251. * Per-CPU access
  3252. */
  3253. static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
  3254. struct mvpp2_tx_queue *txq)
  3255. {
  3256. u32 val;
  3257. /* Reading status reg resets transmitted descriptor counter */
  3258. val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
  3259. return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
  3260. MVPP2_TRANSMITTED_COUNT_OFFSET;
  3261. }
  3262. static void mvpp2_txq_sent_counter_clear(void *arg)
  3263. {
  3264. struct mvpp2_port *port = arg;
  3265. int queue;
  3266. for (queue = 0; queue < txq_number; queue++) {
  3267. int id = port->txqs[queue]->id;
  3268. mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
  3269. }
  3270. }
  3271. /* Set max sizes for Tx queues */
  3272. static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
  3273. {
  3274. u32 val, size, mtu;
  3275. int txq, tx_port_num;
  3276. mtu = port->pkt_size * 8;
  3277. if (mtu > MVPP2_TXP_MTU_MAX)
  3278. mtu = MVPP2_TXP_MTU_MAX;
  3279. /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
  3280. mtu = 3 * mtu;
  3281. /* Indirect access to registers */
  3282. tx_port_num = mvpp2_egress_port(port);
  3283. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3284. /* Set MTU */
  3285. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
  3286. val &= ~MVPP2_TXP_MTU_MAX;
  3287. val |= mtu;
  3288. mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
  3289. /* TXP token size and all TXQs token size must be larger that MTU */
  3290. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
  3291. size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
  3292. if (size < mtu) {
  3293. size = mtu;
  3294. val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
  3295. val |= size;
  3296. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3297. }
  3298. for (txq = 0; txq < txq_number; txq++) {
  3299. val = mvpp2_read(port->priv,
  3300. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
  3301. size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
  3302. if (size < mtu) {
  3303. size = mtu;
  3304. val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
  3305. val |= size;
  3306. mvpp2_write(port->priv,
  3307. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
  3308. val);
  3309. }
  3310. }
  3311. }
  3312. /* Free Tx queue skbuffs */
  3313. static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
  3314. struct mvpp2_tx_queue *txq,
  3315. struct mvpp2_txq_pcpu *txq_pcpu, int num)
  3316. {
  3317. int i;
  3318. for (i = 0; i < num; i++)
  3319. mvpp2_txq_inc_get(txq_pcpu);
  3320. }
  3321. static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
  3322. u32 cause)
  3323. {
  3324. int queue = fls(cause) - 1;
  3325. return port->rxqs[queue];
  3326. }
  3327. static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
  3328. u32 cause)
  3329. {
  3330. int queue = fls(cause) - 1;
  3331. return port->txqs[queue];
  3332. }
  3333. /* Rx/Tx queue initialization/cleanup methods */
  3334. /* Allocate and initialize descriptors for aggr TXQ */
  3335. static int mvpp2_aggr_txq_init(struct udevice *dev,
  3336. struct mvpp2_tx_queue *aggr_txq,
  3337. int desc_num, int cpu,
  3338. struct mvpp2 *priv)
  3339. {
  3340. u32 txq_dma;
  3341. /* Allocate memory for TX descriptors */
  3342. aggr_txq->descs = buffer_loc.aggr_tx_descs;
  3343. aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
  3344. if (!aggr_txq->descs)
  3345. return -ENOMEM;
  3346. /* Make sure descriptor address is cache line size aligned */
  3347. BUG_ON(aggr_txq->descs !=
  3348. PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3349. aggr_txq->last_desc = aggr_txq->size - 1;
  3350. /* Aggr TXQ no reset WA */
  3351. aggr_txq->next_desc_to_proc = mvpp2_read(priv,
  3352. MVPP2_AGGR_TXQ_INDEX_REG(cpu));
  3353. /* Set Tx descriptors queue starting address indirect
  3354. * access
  3355. */
  3356. if (priv->hw_version == MVPP21)
  3357. txq_dma = aggr_txq->descs_dma;
  3358. else
  3359. txq_dma = aggr_txq->descs_dma >>
  3360. MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
  3361. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
  3362. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
  3363. return 0;
  3364. }
  3365. /* Create a specified Rx queue */
  3366. static int mvpp2_rxq_init(struct mvpp2_port *port,
  3367. struct mvpp2_rx_queue *rxq)
  3368. {
  3369. u32 rxq_dma;
  3370. rxq->size = port->rx_ring_size;
  3371. /* Allocate memory for RX descriptors */
  3372. rxq->descs = buffer_loc.rx_descs;
  3373. rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
  3374. if (!rxq->descs)
  3375. return -ENOMEM;
  3376. BUG_ON(rxq->descs !=
  3377. PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3378. rxq->last_desc = rxq->size - 1;
  3379. /* Zero occupied and non-occupied counters - direct access */
  3380. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3381. /* Set Rx descriptors queue starting address - indirect access */
  3382. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3383. if (port->priv->hw_version == MVPP21)
  3384. rxq_dma = rxq->descs_dma;
  3385. else
  3386. rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
  3387. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
  3388. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
  3389. mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
  3390. /* Set Offset */
  3391. mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
  3392. /* Add number of descriptors ready for receiving packets */
  3393. mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
  3394. return 0;
  3395. }
  3396. /* Push packets received by the RXQ to BM pool */
  3397. static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
  3398. struct mvpp2_rx_queue *rxq)
  3399. {
  3400. int rx_received, i;
  3401. rx_received = mvpp2_rxq_received(port, rxq->id);
  3402. if (!rx_received)
  3403. return;
  3404. for (i = 0; i < rx_received; i++) {
  3405. struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
  3406. u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
  3407. mvpp2_pool_refill(port, bm,
  3408. mvpp2_rxdesc_dma_addr_get(port, rx_desc),
  3409. mvpp2_rxdesc_cookie_get(port, rx_desc));
  3410. }
  3411. mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
  3412. }
  3413. /* Cleanup Rx queue */
  3414. static void mvpp2_rxq_deinit(struct mvpp2_port *port,
  3415. struct mvpp2_rx_queue *rxq)
  3416. {
  3417. mvpp2_rxq_drop_pkts(port, rxq);
  3418. rxq->descs = NULL;
  3419. rxq->last_desc = 0;
  3420. rxq->next_desc_to_proc = 0;
  3421. rxq->descs_dma = 0;
  3422. /* Clear Rx descriptors queue starting address and size;
  3423. * free descriptor number
  3424. */
  3425. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3426. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3427. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
  3428. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
  3429. }
  3430. /* Create and initialize a Tx queue */
  3431. static int mvpp2_txq_init(struct mvpp2_port *port,
  3432. struct mvpp2_tx_queue *txq)
  3433. {
  3434. u32 val;
  3435. int cpu, desc, desc_per_txq, tx_port_num;
  3436. struct mvpp2_txq_pcpu *txq_pcpu;
  3437. txq->size = port->tx_ring_size;
  3438. /* Allocate memory for Tx descriptors */
  3439. txq->descs = buffer_loc.tx_descs;
  3440. txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
  3441. if (!txq->descs)
  3442. return -ENOMEM;
  3443. /* Make sure descriptor address is cache line size aligned */
  3444. BUG_ON(txq->descs !=
  3445. PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3446. txq->last_desc = txq->size - 1;
  3447. /* Set Tx descriptors queue starting address - indirect access */
  3448. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3449. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
  3450. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
  3451. MVPP2_TXQ_DESC_SIZE_MASK);
  3452. mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
  3453. mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
  3454. txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
  3455. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3456. val &= ~MVPP2_TXQ_PENDING_MASK;
  3457. mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
  3458. /* Calculate base address in prefetch buffer. We reserve 16 descriptors
  3459. * for each existing TXQ.
  3460. * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
  3461. * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
  3462. */
  3463. desc_per_txq = 16;
  3464. desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
  3465. (txq->log_id * desc_per_txq);
  3466. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
  3467. MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
  3468. MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
  3469. /* WRR / EJP configuration - indirect access */
  3470. tx_port_num = mvpp2_egress_port(port);
  3471. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3472. val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
  3473. val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
  3474. val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
  3475. val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
  3476. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
  3477. val = MVPP2_TXQ_TOKEN_SIZE_MAX;
  3478. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
  3479. val);
  3480. for_each_present_cpu(cpu) {
  3481. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3482. txq_pcpu->size = txq->size;
  3483. }
  3484. return 0;
  3485. }
  3486. /* Free allocated TXQ resources */
  3487. static void mvpp2_txq_deinit(struct mvpp2_port *port,
  3488. struct mvpp2_tx_queue *txq)
  3489. {
  3490. txq->descs = NULL;
  3491. txq->last_desc = 0;
  3492. txq->next_desc_to_proc = 0;
  3493. txq->descs_dma = 0;
  3494. /* Set minimum bandwidth for disabled TXQs */
  3495. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
  3496. /* Set Tx descriptors queue starting address and size */
  3497. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3498. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
  3499. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
  3500. }
  3501. /* Cleanup Tx ports */
  3502. static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
  3503. {
  3504. struct mvpp2_txq_pcpu *txq_pcpu;
  3505. int delay, pending, cpu;
  3506. u32 val;
  3507. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3508. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  3509. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  3510. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3511. /* The napi queue has been stopped so wait for all packets
  3512. * to be transmitted.
  3513. */
  3514. delay = 0;
  3515. do {
  3516. if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
  3517. netdev_warn(port->dev,
  3518. "port %d: cleaning queue %d timed out\n",
  3519. port->id, txq->log_id);
  3520. break;
  3521. }
  3522. mdelay(1);
  3523. delay++;
  3524. pending = mvpp2_txq_pend_desc_num_get(port, txq);
  3525. } while (pending);
  3526. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  3527. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3528. for_each_present_cpu(cpu) {
  3529. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3530. /* Release all packets */
  3531. mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
  3532. /* Reset queue */
  3533. txq_pcpu->count = 0;
  3534. txq_pcpu->txq_put_index = 0;
  3535. txq_pcpu->txq_get_index = 0;
  3536. }
  3537. }
  3538. /* Cleanup all Tx queues */
  3539. static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
  3540. {
  3541. struct mvpp2_tx_queue *txq;
  3542. int queue;
  3543. u32 val;
  3544. val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
  3545. /* Reset Tx ports and delete Tx queues */
  3546. val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3547. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3548. for (queue = 0; queue < txq_number; queue++) {
  3549. txq = port->txqs[queue];
  3550. mvpp2_txq_clean(port, txq);
  3551. mvpp2_txq_deinit(port, txq);
  3552. }
  3553. mvpp2_txq_sent_counter_clear(port);
  3554. val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3555. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3556. }
  3557. /* Cleanup all Rx queues */
  3558. static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
  3559. {
  3560. int queue;
  3561. for (queue = 0; queue < rxq_number; queue++)
  3562. mvpp2_rxq_deinit(port, port->rxqs[queue]);
  3563. }
  3564. /* Init all Rx queues for port */
  3565. static int mvpp2_setup_rxqs(struct mvpp2_port *port)
  3566. {
  3567. int queue, err;
  3568. for (queue = 0; queue < rxq_number; queue++) {
  3569. err = mvpp2_rxq_init(port, port->rxqs[queue]);
  3570. if (err)
  3571. goto err_cleanup;
  3572. }
  3573. return 0;
  3574. err_cleanup:
  3575. mvpp2_cleanup_rxqs(port);
  3576. return err;
  3577. }
  3578. /* Init all tx queues for port */
  3579. static int mvpp2_setup_txqs(struct mvpp2_port *port)
  3580. {
  3581. struct mvpp2_tx_queue *txq;
  3582. int queue, err;
  3583. for (queue = 0; queue < txq_number; queue++) {
  3584. txq = port->txqs[queue];
  3585. err = mvpp2_txq_init(port, txq);
  3586. if (err)
  3587. goto err_cleanup;
  3588. }
  3589. mvpp2_txq_sent_counter_clear(port);
  3590. return 0;
  3591. err_cleanup:
  3592. mvpp2_cleanup_txqs(port);
  3593. return err;
  3594. }
  3595. /* Adjust link */
  3596. static void mvpp2_link_event(struct mvpp2_port *port)
  3597. {
  3598. struct phy_device *phydev = port->phy_dev;
  3599. int status_change = 0;
  3600. u32 val;
  3601. if (phydev->link) {
  3602. if ((port->speed != phydev->speed) ||
  3603. (port->duplex != phydev->duplex)) {
  3604. u32 val;
  3605. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3606. val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
  3607. MVPP2_GMAC_CONFIG_GMII_SPEED |
  3608. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  3609. MVPP2_GMAC_AN_SPEED_EN |
  3610. MVPP2_GMAC_AN_DUPLEX_EN);
  3611. if (phydev->duplex)
  3612. val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
  3613. if (phydev->speed == SPEED_1000)
  3614. val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
  3615. else if (phydev->speed == SPEED_100)
  3616. val |= MVPP2_GMAC_CONFIG_MII_SPEED;
  3617. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3618. port->duplex = phydev->duplex;
  3619. port->speed = phydev->speed;
  3620. }
  3621. }
  3622. if (phydev->link != port->link) {
  3623. if (!phydev->link) {
  3624. port->duplex = -1;
  3625. port->speed = 0;
  3626. }
  3627. port->link = phydev->link;
  3628. status_change = 1;
  3629. }
  3630. if (status_change) {
  3631. if (phydev->link) {
  3632. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3633. val |= (MVPP2_GMAC_FORCE_LINK_PASS |
  3634. MVPP2_GMAC_FORCE_LINK_DOWN);
  3635. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3636. mvpp2_egress_enable(port);
  3637. mvpp2_ingress_enable(port);
  3638. } else {
  3639. mvpp2_ingress_disable(port);
  3640. mvpp2_egress_disable(port);
  3641. }
  3642. }
  3643. }
  3644. /* Main RX/TX processing routines */
  3645. /* Display more error info */
  3646. static void mvpp2_rx_error(struct mvpp2_port *port,
  3647. struct mvpp2_rx_desc *rx_desc)
  3648. {
  3649. u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
  3650. size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
  3651. switch (status & MVPP2_RXD_ERR_CODE_MASK) {
  3652. case MVPP2_RXD_ERR_CRC:
  3653. netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
  3654. status, sz);
  3655. break;
  3656. case MVPP2_RXD_ERR_OVERRUN:
  3657. netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
  3658. status, sz);
  3659. break;
  3660. case MVPP2_RXD_ERR_RESOURCE:
  3661. netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
  3662. status, sz);
  3663. break;
  3664. }
  3665. }
  3666. /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
  3667. static int mvpp2_rx_refill(struct mvpp2_port *port,
  3668. struct mvpp2_bm_pool *bm_pool,
  3669. u32 bm, dma_addr_t dma_addr)
  3670. {
  3671. mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
  3672. return 0;
  3673. }
  3674. /* Set hw internals when starting port */
  3675. static void mvpp2_start_dev(struct mvpp2_port *port)
  3676. {
  3677. switch (port->phy_interface) {
  3678. case PHY_INTERFACE_MODE_RGMII:
  3679. case PHY_INTERFACE_MODE_RGMII_ID:
  3680. case PHY_INTERFACE_MODE_SGMII:
  3681. mvpp2_gmac_max_rx_size_set(port);
  3682. default:
  3683. break;
  3684. }
  3685. mvpp2_txp_max_tx_size_set(port);
  3686. if (port->priv->hw_version == MVPP21)
  3687. mvpp2_port_enable(port);
  3688. else
  3689. gop_port_enable(port, 1);
  3690. }
  3691. /* Set hw internals when stopping port */
  3692. static void mvpp2_stop_dev(struct mvpp2_port *port)
  3693. {
  3694. /* Stop new packets from arriving to RXQs */
  3695. mvpp2_ingress_disable(port);
  3696. mvpp2_egress_disable(port);
  3697. if (port->priv->hw_version == MVPP21)
  3698. mvpp2_port_disable(port);
  3699. else
  3700. gop_port_enable(port, 0);
  3701. }
  3702. static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
  3703. {
  3704. struct phy_device *phy_dev;
  3705. if (!port->init || port->link == 0) {
  3706. phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
  3707. dev, port->phy_interface);
  3708. /*
  3709. * If the phy doesn't match with any existing u-boot drivers the
  3710. * phy framework will connect it to generic one which
  3711. * uid == 0xffffffff. In this case act as if the phy wouldn't be
  3712. * declared in dts. Otherwise in case of 3310 (for which the
  3713. * driver doesn't exist) the link will not be correctly
  3714. * detected. Removing phy entry from dts in case of 3310 is not
  3715. * an option because it is required for the phy_fw_down
  3716. * procedure.
  3717. */
  3718. if (phy_dev &&
  3719. phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
  3720. netdev_warn(port->dev,
  3721. "Marking phy as invalid, link will not be checked\n");
  3722. /* set phy_addr to invalid value */
  3723. port->phyaddr = PHY_MAX_ADDR;
  3724. mvpp2_egress_enable(port);
  3725. mvpp2_ingress_enable(port);
  3726. return;
  3727. }
  3728. port->phy_dev = phy_dev;
  3729. if (!phy_dev) {
  3730. netdev_err(port->dev, "cannot connect to phy\n");
  3731. return;
  3732. }
  3733. phy_dev->supported &= PHY_GBIT_FEATURES;
  3734. phy_dev->advertising = phy_dev->supported;
  3735. port->phy_dev = phy_dev;
  3736. port->link = 0;
  3737. port->duplex = 0;
  3738. port->speed = 0;
  3739. phy_config(phy_dev);
  3740. phy_startup(phy_dev);
  3741. if (!phy_dev->link)
  3742. printf("%s: No link\n", phy_dev->dev->name);
  3743. else
  3744. port->init = 1;
  3745. } else {
  3746. mvpp2_egress_enable(port);
  3747. mvpp2_ingress_enable(port);
  3748. }
  3749. }
  3750. static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
  3751. {
  3752. unsigned char mac_bcast[ETH_ALEN] = {
  3753. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3754. int err;
  3755. err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
  3756. if (err) {
  3757. netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
  3758. return err;
  3759. }
  3760. err = mvpp2_prs_mac_da_accept(port->priv, port->id,
  3761. port->dev_addr, true);
  3762. if (err) {
  3763. netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
  3764. return err;
  3765. }
  3766. err = mvpp2_prs_def_flow(port);
  3767. if (err) {
  3768. netdev_err(dev, "mvpp2_prs_def_flow failed\n");
  3769. return err;
  3770. }
  3771. /* Allocate the Rx/Tx queues */
  3772. err = mvpp2_setup_rxqs(port);
  3773. if (err) {
  3774. netdev_err(port->dev, "cannot allocate Rx queues\n");
  3775. return err;
  3776. }
  3777. err = mvpp2_setup_txqs(port);
  3778. if (err) {
  3779. netdev_err(port->dev, "cannot allocate Tx queues\n");
  3780. return err;
  3781. }
  3782. if (port->phyaddr < PHY_MAX_ADDR) {
  3783. mvpp2_phy_connect(dev, port);
  3784. mvpp2_link_event(port);
  3785. } else {
  3786. mvpp2_egress_enable(port);
  3787. mvpp2_ingress_enable(port);
  3788. }
  3789. mvpp2_start_dev(port);
  3790. return 0;
  3791. }
  3792. /* No Device ops here in U-Boot */
  3793. /* Driver initialization */
  3794. static void mvpp2_port_power_up(struct mvpp2_port *port)
  3795. {
  3796. struct mvpp2 *priv = port->priv;
  3797. /* On PPv2.2 the GoP / interface configuration has already been done */
  3798. if (priv->hw_version == MVPP21)
  3799. mvpp2_port_mii_set(port);
  3800. mvpp2_port_periodic_xon_disable(port);
  3801. if (priv->hw_version == MVPP21)
  3802. mvpp2_port_fc_adv_enable(port);
  3803. mvpp2_port_reset(port);
  3804. }
  3805. /* Initialize port HW */
  3806. static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
  3807. {
  3808. struct mvpp2 *priv = port->priv;
  3809. struct mvpp2_txq_pcpu *txq_pcpu;
  3810. int queue, cpu, err;
  3811. if (port->first_rxq + rxq_number >
  3812. MVPP2_MAX_PORTS * priv->max_port_rxqs)
  3813. return -EINVAL;
  3814. /* Disable port */
  3815. mvpp2_egress_disable(port);
  3816. if (priv->hw_version == MVPP21)
  3817. mvpp2_port_disable(port);
  3818. else
  3819. gop_port_enable(port, 0);
  3820. port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
  3821. GFP_KERNEL);
  3822. if (!port->txqs)
  3823. return -ENOMEM;
  3824. /* Associate physical Tx queues to this port and initialize.
  3825. * The mapping is predefined.
  3826. */
  3827. for (queue = 0; queue < txq_number; queue++) {
  3828. int queue_phy_id = mvpp2_txq_phys(port->id, queue);
  3829. struct mvpp2_tx_queue *txq;
  3830. txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
  3831. if (!txq)
  3832. return -ENOMEM;
  3833. txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
  3834. GFP_KERNEL);
  3835. if (!txq->pcpu)
  3836. return -ENOMEM;
  3837. txq->id = queue_phy_id;
  3838. txq->log_id = queue;
  3839. txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
  3840. for_each_present_cpu(cpu) {
  3841. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3842. txq_pcpu->cpu = cpu;
  3843. }
  3844. port->txqs[queue] = txq;
  3845. }
  3846. port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
  3847. GFP_KERNEL);
  3848. if (!port->rxqs)
  3849. return -ENOMEM;
  3850. /* Allocate and initialize Rx queue for this port */
  3851. for (queue = 0; queue < rxq_number; queue++) {
  3852. struct mvpp2_rx_queue *rxq;
  3853. /* Map physical Rx queue to port's logical Rx queue */
  3854. rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
  3855. if (!rxq)
  3856. return -ENOMEM;
  3857. /* Map this Rx queue to a physical queue */
  3858. rxq->id = port->first_rxq + queue;
  3859. rxq->port = port->id;
  3860. rxq->logic_rxq = queue;
  3861. port->rxqs[queue] = rxq;
  3862. }
  3863. /* Create Rx descriptor rings */
  3864. for (queue = 0; queue < rxq_number; queue++) {
  3865. struct mvpp2_rx_queue *rxq = port->rxqs[queue];
  3866. rxq->size = port->rx_ring_size;
  3867. rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
  3868. rxq->time_coal = MVPP2_RX_COAL_USEC;
  3869. }
  3870. mvpp2_ingress_disable(port);
  3871. /* Port default configuration */
  3872. mvpp2_defaults_set(port);
  3873. /* Port's classifier configuration */
  3874. mvpp2_cls_oversize_rxq_set(port);
  3875. mvpp2_cls_port_config(port);
  3876. /* Provide an initial Rx packet size */
  3877. port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
  3878. /* Initialize pools for swf */
  3879. err = mvpp2_swf_bm_pool_init(port);
  3880. if (err)
  3881. return err;
  3882. return 0;
  3883. }
  3884. static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
  3885. {
  3886. int port_node = dev_of_offset(dev);
  3887. const char *phy_mode_str;
  3888. int phy_node;
  3889. u32 id;
  3890. u32 phyaddr = 0;
  3891. int phy_mode = -1;
  3892. int ret;
  3893. phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
  3894. if (phy_node > 0) {
  3895. int parent;
  3896. phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
  3897. if (phyaddr < 0) {
  3898. dev_err(&pdev->dev, "could not find phy address\n");
  3899. return -1;
  3900. }
  3901. parent = fdt_parent_offset(gd->fdt_blob, phy_node);
  3902. ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
  3903. &port->mdio_dev);
  3904. if (ret)
  3905. return ret;
  3906. } else {
  3907. /* phy_addr is set to invalid value */
  3908. phyaddr = PHY_MAX_ADDR;
  3909. }
  3910. phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
  3911. if (phy_mode_str)
  3912. phy_mode = phy_get_interface_by_name(phy_mode_str);
  3913. if (phy_mode == -1) {
  3914. dev_err(&pdev->dev, "incorrect phy mode\n");
  3915. return -EINVAL;
  3916. }
  3917. id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
  3918. if (id == -1) {
  3919. dev_err(&pdev->dev, "missing port-id value\n");
  3920. return -EINVAL;
  3921. }
  3922. #if CONFIG_IS_ENABLED(DM_GPIO)
  3923. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  3924. &port->phy_reset_gpio, GPIOD_IS_OUT);
  3925. gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
  3926. &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
  3927. #endif
  3928. /*
  3929. * ToDo:
  3930. * Not sure if this DT property "phy-speed" will get accepted, so
  3931. * this might change later
  3932. */
  3933. /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
  3934. port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
  3935. "phy-speed", 1000);
  3936. port->id = id;
  3937. if (port->priv->hw_version == MVPP21)
  3938. port->first_rxq = port->id * rxq_number;
  3939. else
  3940. port->first_rxq = port->id * port->priv->max_port_rxqs;
  3941. port->phy_interface = phy_mode;
  3942. port->phyaddr = phyaddr;
  3943. return 0;
  3944. }
  3945. #if CONFIG_IS_ENABLED(DM_GPIO)
  3946. /* Port GPIO initialization */
  3947. static void mvpp2_gpio_init(struct mvpp2_port *port)
  3948. {
  3949. if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
  3950. dm_gpio_set_value(&port->phy_reset_gpio, 1);
  3951. mdelay(10);
  3952. dm_gpio_set_value(&port->phy_reset_gpio, 0);
  3953. }
  3954. if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
  3955. dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
  3956. }
  3957. #endif
  3958. /* Ports initialization */
  3959. static int mvpp2_port_probe(struct udevice *dev,
  3960. struct mvpp2_port *port,
  3961. int port_node,
  3962. struct mvpp2 *priv)
  3963. {
  3964. int err;
  3965. port->tx_ring_size = MVPP2_MAX_TXD;
  3966. port->rx_ring_size = MVPP2_MAX_RXD;
  3967. err = mvpp2_port_init(dev, port);
  3968. if (err < 0) {
  3969. dev_err(&pdev->dev, "failed to init port %d\n", port->id);
  3970. return err;
  3971. }
  3972. mvpp2_port_power_up(port);
  3973. #if CONFIG_IS_ENABLED(DM_GPIO)
  3974. mvpp2_gpio_init(port);
  3975. #endif
  3976. priv->port_list[port->id] = port;
  3977. priv->num_ports++;
  3978. return 0;
  3979. }
  3980. /* Initialize decoding windows */
  3981. static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
  3982. struct mvpp2 *priv)
  3983. {
  3984. u32 win_enable;
  3985. int i;
  3986. for (i = 0; i < 6; i++) {
  3987. mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
  3988. mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
  3989. if (i < 4)
  3990. mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
  3991. }
  3992. win_enable = 0;
  3993. for (i = 0; i < dram->num_cs; i++) {
  3994. const struct mbus_dram_window *cs = dram->cs + i;
  3995. mvpp2_write(priv, MVPP2_WIN_BASE(i),
  3996. (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
  3997. dram->mbus_dram_target_id);
  3998. mvpp2_write(priv, MVPP2_WIN_SIZE(i),
  3999. (cs->size - 1) & 0xffff0000);
  4000. win_enable |= (1 << i);
  4001. }
  4002. mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
  4003. }
  4004. /* Initialize Rx FIFO's */
  4005. static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
  4006. {
  4007. int port;
  4008. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4009. if (priv->hw_version == MVPP22) {
  4010. if (port == 0) {
  4011. mvpp2_write(priv,
  4012. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4013. MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
  4014. mvpp2_write(priv,
  4015. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4016. MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
  4017. } else if (port == 1) {
  4018. mvpp2_write(priv,
  4019. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4020. MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
  4021. mvpp2_write(priv,
  4022. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4023. MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
  4024. } else {
  4025. mvpp2_write(priv,
  4026. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4027. MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
  4028. mvpp2_write(priv,
  4029. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4030. MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
  4031. }
  4032. } else {
  4033. mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4034. MVPP21_RX_FIFO_PORT_DATA_SIZE);
  4035. mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4036. MVPP21_RX_FIFO_PORT_ATTR_SIZE);
  4037. }
  4038. }
  4039. mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
  4040. MVPP2_RX_FIFO_PORT_MIN_PKT);
  4041. mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
  4042. }
  4043. /* Initialize Tx FIFO's */
  4044. static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
  4045. {
  4046. int port, val;
  4047. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4048. /* Port 0 supports 10KB TX FIFO */
  4049. if (port == 0) {
  4050. val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
  4051. MVPP22_TX_FIFO_SIZE_MASK;
  4052. } else {
  4053. val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
  4054. MVPP22_TX_FIFO_SIZE_MASK;
  4055. }
  4056. mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
  4057. }
  4058. }
  4059. static void mvpp2_axi_init(struct mvpp2 *priv)
  4060. {
  4061. u32 val, rdval, wrval;
  4062. mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
  4063. /* AXI Bridge Configuration */
  4064. rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4065. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4066. rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4067. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4068. wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4069. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4070. wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4071. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4072. /* BM */
  4073. mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
  4074. mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
  4075. /* Descriptors */
  4076. mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
  4077. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
  4078. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
  4079. mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
  4080. /* Buffer Data */
  4081. mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
  4082. mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
  4083. val = MVPP22_AXI_CODE_CACHE_NON_CACHE
  4084. << MVPP22_AXI_CODE_CACHE_OFFS;
  4085. val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
  4086. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4087. mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
  4088. mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
  4089. val = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4090. << MVPP22_AXI_CODE_CACHE_OFFS;
  4091. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4092. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4093. mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
  4094. val = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4095. << MVPP22_AXI_CODE_CACHE_OFFS;
  4096. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4097. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4098. mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
  4099. }
  4100. /* Initialize network controller common part HW */
  4101. static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
  4102. {
  4103. const struct mbus_dram_target_info *dram_target_info;
  4104. int err, i;
  4105. u32 val;
  4106. /* Checks for hardware constraints (U-Boot uses only one rxq) */
  4107. if ((rxq_number > priv->max_port_rxqs) ||
  4108. (txq_number > MVPP2_MAX_TXQ)) {
  4109. dev_err(&pdev->dev, "invalid queue size parameter\n");
  4110. return -EINVAL;
  4111. }
  4112. if (priv->hw_version == MVPP22)
  4113. mvpp2_axi_init(priv);
  4114. else {
  4115. /* MBUS windows configuration */
  4116. dram_target_info = mvebu_mbus_dram_info();
  4117. if (dram_target_info)
  4118. mvpp2_conf_mbus_windows(dram_target_info, priv);
  4119. }
  4120. if (priv->hw_version == MVPP21) {
  4121. /* Disable HW PHY polling */
  4122. val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4123. val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
  4124. writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4125. } else {
  4126. /* Enable HW PHY polling */
  4127. val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4128. val |= MVPP22_SMI_POLLING_EN;
  4129. writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4130. }
  4131. /* Allocate and initialize aggregated TXQs */
  4132. priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
  4133. sizeof(struct mvpp2_tx_queue),
  4134. GFP_KERNEL);
  4135. if (!priv->aggr_txqs)
  4136. return -ENOMEM;
  4137. for_each_present_cpu(i) {
  4138. priv->aggr_txqs[i].id = i;
  4139. priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
  4140. err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
  4141. MVPP2_AGGR_TXQ_SIZE, i, priv);
  4142. if (err < 0)
  4143. return err;
  4144. }
  4145. /* Rx Fifo Init */
  4146. mvpp2_rx_fifo_init(priv);
  4147. /* Tx Fifo Init */
  4148. if (priv->hw_version == MVPP22)
  4149. mvpp2_tx_fifo_init(priv);
  4150. if (priv->hw_version == MVPP21)
  4151. writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
  4152. priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
  4153. /* Allow cache snoop when transmiting packets */
  4154. mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
  4155. /* Buffer Manager initialization */
  4156. err = mvpp2_bm_init(dev, priv);
  4157. if (err < 0)
  4158. return err;
  4159. /* Parser default initialization */
  4160. err = mvpp2_prs_default_init(dev, priv);
  4161. if (err < 0)
  4162. return err;
  4163. /* Classifier default initialization */
  4164. mvpp2_cls_init(priv);
  4165. return 0;
  4166. }
  4167. static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
  4168. {
  4169. struct mvpp2_port *port = dev_get_priv(dev);
  4170. struct mvpp2_rx_desc *rx_desc;
  4171. struct mvpp2_bm_pool *bm_pool;
  4172. dma_addr_t dma_addr;
  4173. u32 bm, rx_status;
  4174. int pool, rx_bytes, err;
  4175. int rx_received;
  4176. struct mvpp2_rx_queue *rxq;
  4177. u8 *data;
  4178. if (port->phyaddr < PHY_MAX_ADDR)
  4179. if (!port->phy_dev->link)
  4180. return 0;
  4181. /* Process RX packets */
  4182. rxq = port->rxqs[0];
  4183. /* Get number of received packets and clamp the to-do */
  4184. rx_received = mvpp2_rxq_received(port, rxq->id);
  4185. /* Return if no packets are received */
  4186. if (!rx_received)
  4187. return 0;
  4188. rx_desc = mvpp2_rxq_next_desc_get(rxq);
  4189. rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
  4190. rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
  4191. rx_bytes -= MVPP2_MH_SIZE;
  4192. dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
  4193. bm = mvpp2_bm_cookie_build(port, rx_desc);
  4194. pool = mvpp2_bm_cookie_pool_get(bm);
  4195. bm_pool = &port->priv->bm_pools[pool];
  4196. /* In case of an error, release the requested buffer pointer
  4197. * to the Buffer Manager. This request process is controlled
  4198. * by the hardware, and the information about the buffer is
  4199. * comprised by the RX descriptor.
  4200. */
  4201. if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
  4202. mvpp2_rx_error(port, rx_desc);
  4203. /* Return the buffer to the pool */
  4204. mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
  4205. return 0;
  4206. }
  4207. err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
  4208. if (err) {
  4209. netdev_err(port->dev, "failed to refill BM pools\n");
  4210. return 0;
  4211. }
  4212. /* Update Rx queue management counters */
  4213. mb();
  4214. mvpp2_rxq_status_update(port, rxq->id, 1, 1);
  4215. /* give packet to stack - skip on first n bytes */
  4216. data = (u8 *)dma_addr + 2 + 32;
  4217. if (rx_bytes <= 0)
  4218. return 0;
  4219. /*
  4220. * No cache invalidation needed here, since the rx_buffer's are
  4221. * located in a uncached memory region
  4222. */
  4223. *packetp = data;
  4224. return rx_bytes;
  4225. }
  4226. static int mvpp2_send(struct udevice *dev, void *packet, int length)
  4227. {
  4228. struct mvpp2_port *port = dev_get_priv(dev);
  4229. struct mvpp2_tx_queue *txq, *aggr_txq;
  4230. struct mvpp2_tx_desc *tx_desc;
  4231. int tx_done;
  4232. int timeout;
  4233. if (port->phyaddr < PHY_MAX_ADDR)
  4234. if (!port->phy_dev->link)
  4235. return 0;
  4236. txq = port->txqs[0];
  4237. aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
  4238. /* Get a descriptor for the first part of the packet */
  4239. tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
  4240. mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
  4241. mvpp2_txdesc_size_set(port, tx_desc, length);
  4242. mvpp2_txdesc_offset_set(port, tx_desc,
  4243. (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
  4244. mvpp2_txdesc_dma_addr_set(port, tx_desc,
  4245. (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
  4246. /* First and Last descriptor */
  4247. mvpp2_txdesc_cmd_set(port, tx_desc,
  4248. MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
  4249. | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
  4250. /* Flush tx data */
  4251. flush_dcache_range((unsigned long)packet,
  4252. (unsigned long)packet + ALIGN(length, PKTALIGN));
  4253. /* Enable transmit */
  4254. mb();
  4255. mvpp2_aggr_txq_pend_desc_add(port, 1);
  4256. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  4257. timeout = 0;
  4258. do {
  4259. if (timeout++ > 10000) {
  4260. printf("timeout: packet not sent from aggregated to phys TXQ\n");
  4261. return 0;
  4262. }
  4263. tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
  4264. } while (tx_done);
  4265. timeout = 0;
  4266. do {
  4267. if (timeout++ > 10000) {
  4268. printf("timeout: packet not sent\n");
  4269. return 0;
  4270. }
  4271. tx_done = mvpp2_txq_sent_desc_proc(port, txq);
  4272. } while (!tx_done);
  4273. return 0;
  4274. }
  4275. static int mvpp2_start(struct udevice *dev)
  4276. {
  4277. struct eth_pdata *pdata = dev_get_platdata(dev);
  4278. struct mvpp2_port *port = dev_get_priv(dev);
  4279. /* Load current MAC address */
  4280. memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
  4281. /* Reconfigure parser accept the original MAC address */
  4282. mvpp2_prs_update_mac_da(port, port->dev_addr);
  4283. switch (port->phy_interface) {
  4284. case PHY_INTERFACE_MODE_RGMII:
  4285. case PHY_INTERFACE_MODE_RGMII_ID:
  4286. case PHY_INTERFACE_MODE_SGMII:
  4287. mvpp2_port_power_up(port);
  4288. default:
  4289. break;
  4290. }
  4291. mvpp2_open(dev, port);
  4292. return 0;
  4293. }
  4294. static void mvpp2_stop(struct udevice *dev)
  4295. {
  4296. struct mvpp2_port *port = dev_get_priv(dev);
  4297. mvpp2_stop_dev(port);
  4298. mvpp2_cleanup_rxqs(port);
  4299. mvpp2_cleanup_txqs(port);
  4300. }
  4301. static int mvpp2_write_hwaddr(struct udevice *dev)
  4302. {
  4303. struct mvpp2_port *port = dev_get_priv(dev);
  4304. return mvpp2_prs_update_mac_da(port, port->dev_addr);
  4305. }
  4306. static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
  4307. {
  4308. writel(port->phyaddr, port->priv->iface_base +
  4309. MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
  4310. return 0;
  4311. }
  4312. static int mvpp2_base_probe(struct udevice *dev)
  4313. {
  4314. struct mvpp2 *priv = dev_get_priv(dev);
  4315. void *bd_space;
  4316. u32 size = 0;
  4317. int i;
  4318. /* Save hw-version */
  4319. priv->hw_version = dev_get_driver_data(dev);
  4320. /*
  4321. * U-Boot special buffer handling:
  4322. *
  4323. * Allocate buffer area for descs and rx_buffers. This is only
  4324. * done once for all interfaces. As only one interface can
  4325. * be active. Make this area DMA-safe by disabling the D-cache
  4326. */
  4327. if (!buffer_loc_init) {
  4328. /* Align buffer area for descs and rx_buffers to 1MiB */
  4329. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  4330. mmu_set_region_dcache_behaviour((unsigned long)bd_space,
  4331. BD_SPACE, DCACHE_OFF);
  4332. buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
  4333. size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
  4334. buffer_loc.tx_descs =
  4335. (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
  4336. size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
  4337. buffer_loc.rx_descs =
  4338. (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
  4339. size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
  4340. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  4341. buffer_loc.bm_pool[i] =
  4342. (unsigned long *)((unsigned long)bd_space + size);
  4343. if (priv->hw_version == MVPP21)
  4344. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
  4345. else
  4346. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
  4347. }
  4348. for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
  4349. buffer_loc.rx_buffer[i] =
  4350. (unsigned long *)((unsigned long)bd_space + size);
  4351. size += RX_BUFFER_SIZE;
  4352. }
  4353. /* Clear the complete area so that all descriptors are cleared */
  4354. memset(bd_space, 0, size);
  4355. buffer_loc_init = 1;
  4356. }
  4357. /* Save base addresses for later use */
  4358. priv->base = (void *)devfdt_get_addr_index(dev, 0);
  4359. if (IS_ERR(priv->base))
  4360. return PTR_ERR(priv->base);
  4361. if (priv->hw_version == MVPP21) {
  4362. priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
  4363. if (IS_ERR(priv->lms_base))
  4364. return PTR_ERR(priv->lms_base);
  4365. } else {
  4366. priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
  4367. if (IS_ERR(priv->iface_base))
  4368. return PTR_ERR(priv->iface_base);
  4369. /* Store common base addresses for all ports */
  4370. priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
  4371. priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
  4372. priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
  4373. }
  4374. if (priv->hw_version == MVPP21)
  4375. priv->max_port_rxqs = 8;
  4376. else
  4377. priv->max_port_rxqs = 32;
  4378. return 0;
  4379. }
  4380. static int mvpp2_probe(struct udevice *dev)
  4381. {
  4382. struct mvpp2_port *port = dev_get_priv(dev);
  4383. struct mvpp2 *priv = dev_get_priv(dev->parent);
  4384. int err;
  4385. /* Only call the probe function for the parent once */
  4386. if (!priv->probe_done)
  4387. err = mvpp2_base_probe(dev->parent);
  4388. port->priv = priv;
  4389. err = phy_info_parse(dev, port);
  4390. if (err)
  4391. return err;
  4392. /*
  4393. * We need the port specific io base addresses at this stage, since
  4394. * gop_port_init() accesses these registers
  4395. */
  4396. if (priv->hw_version == MVPP21) {
  4397. int priv_common_regs_num = 2;
  4398. port->base = (void __iomem *)devfdt_get_addr_index(
  4399. dev->parent, priv_common_regs_num + port->id);
  4400. if (IS_ERR(port->base))
  4401. return PTR_ERR(port->base);
  4402. } else {
  4403. port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  4404. "gop-port-id", -1);
  4405. if (port->id == -1) {
  4406. dev_err(&pdev->dev, "missing gop-port-id value\n");
  4407. return -EINVAL;
  4408. }
  4409. port->base = priv->iface_base + MVPP22_PORT_BASE +
  4410. port->gop_id * MVPP22_PORT_OFFSET;
  4411. /* Set phy address of the port */
  4412. if (port->phyaddr < PHY_MAX_ADDR)
  4413. mvpp22_smi_phy_addr_cfg(port);
  4414. /* GoP Init */
  4415. gop_port_init(port);
  4416. }
  4417. if (!priv->probe_done) {
  4418. /* Initialize network controller */
  4419. err = mvpp2_init(dev, priv);
  4420. if (err < 0) {
  4421. dev_err(&pdev->dev, "failed to initialize controller\n");
  4422. return err;
  4423. }
  4424. priv->num_ports = 0;
  4425. priv->probe_done = 1;
  4426. }
  4427. err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
  4428. if (err)
  4429. return err;
  4430. if (priv->hw_version == MVPP22) {
  4431. priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
  4432. port->phy_interface);
  4433. /* Netcomplex configurations for all ports */
  4434. gop_netc_init(priv, MV_NETC_FIRST_PHASE);
  4435. gop_netc_init(priv, MV_NETC_SECOND_PHASE);
  4436. }
  4437. return 0;
  4438. }
  4439. /*
  4440. * Empty BM pool and stop its activity before the OS is started
  4441. */
  4442. static int mvpp2_remove(struct udevice *dev)
  4443. {
  4444. struct mvpp2_port *port = dev_get_priv(dev);
  4445. struct mvpp2 *priv = port->priv;
  4446. int i;
  4447. priv->num_ports--;
  4448. if (priv->num_ports)
  4449. return 0;
  4450. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
  4451. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  4452. return 0;
  4453. }
  4454. static const struct eth_ops mvpp2_ops = {
  4455. .start = mvpp2_start,
  4456. .send = mvpp2_send,
  4457. .recv = mvpp2_recv,
  4458. .stop = mvpp2_stop,
  4459. .write_hwaddr = mvpp2_write_hwaddr
  4460. };
  4461. static struct driver mvpp2_driver = {
  4462. .name = "mvpp2",
  4463. .id = UCLASS_ETH,
  4464. .probe = mvpp2_probe,
  4465. .remove = mvpp2_remove,
  4466. .ops = &mvpp2_ops,
  4467. .priv_auto_alloc_size = sizeof(struct mvpp2_port),
  4468. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  4469. .flags = DM_FLAG_ACTIVE_DMA,
  4470. };
  4471. /*
  4472. * Use a MISC device to bind the n instances (child nodes) of the
  4473. * network base controller in UCLASS_ETH.
  4474. */
  4475. static int mvpp2_base_bind(struct udevice *parent)
  4476. {
  4477. const void *blob = gd->fdt_blob;
  4478. int node = dev_of_offset(parent);
  4479. struct uclass_driver *drv;
  4480. struct udevice *dev;
  4481. struct eth_pdata *plat;
  4482. char *name;
  4483. int subnode;
  4484. u32 id;
  4485. int base_id_add;
  4486. /* Lookup eth driver */
  4487. drv = lists_uclass_lookup(UCLASS_ETH);
  4488. if (!drv) {
  4489. puts("Cannot find eth driver\n");
  4490. return -ENOENT;
  4491. }
  4492. base_id_add = base_id;
  4493. fdt_for_each_subnode(subnode, blob, node) {
  4494. /* Increment base_id for all subnodes, also the disabled ones */
  4495. base_id++;
  4496. /* Skip disabled ports */
  4497. if (!fdtdec_get_is_enabled(blob, subnode))
  4498. continue;
  4499. plat = calloc(1, sizeof(*plat));
  4500. if (!plat)
  4501. return -ENOMEM;
  4502. id = fdtdec_get_int(blob, subnode, "port-id", -1);
  4503. id += base_id_add;
  4504. name = calloc(1, 16);
  4505. if (!name) {
  4506. free(plat);
  4507. return -ENOMEM;
  4508. }
  4509. sprintf(name, "mvpp2-%d", id);
  4510. /* Create child device UCLASS_ETH and bind it */
  4511. device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
  4512. dev_set_of_offset(dev, subnode);
  4513. }
  4514. return 0;
  4515. }
  4516. static const struct udevice_id mvpp2_ids[] = {
  4517. {
  4518. .compatible = "marvell,armada-375-pp2",
  4519. .data = MVPP21,
  4520. },
  4521. {
  4522. .compatible = "marvell,armada-7k-pp22",
  4523. .data = MVPP22,
  4524. },
  4525. { }
  4526. };
  4527. U_BOOT_DRIVER(mvpp2_base) = {
  4528. .name = "mvpp2_base",
  4529. .id = UCLASS_MISC,
  4530. .of_match = mvpp2_ids,
  4531. .bind = mvpp2_base_bind,
  4532. .priv_auto_alloc_size = sizeof(struct mvpp2),
  4533. };