mvneta.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  4. *
  5. * U-Boot version:
  6. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  7. *
  8. * Based on the Linux version which is:
  9. * Copyright (C) 2012 Marvell
  10. *
  11. * Rami Rosen <rosenr@marvell.com>
  12. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13. */
  14. #include <common.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. #include <config.h>
  21. #include <malloc.h>
  22. #include <asm/cache.h>
  23. #include <asm/io.h>
  24. #include <dm/device_compat.h>
  25. #include <dm/devres.h>
  26. #include <linux/bitops.h>
  27. #include <linux/bug.h>
  28. #include <linux/delay.h>
  29. #include <linux/errno.h>
  30. #include <phy.h>
  31. #include <miiphy.h>
  32. #include <watchdog.h>
  33. #include <asm/arch/cpu.h>
  34. #include <asm/arch/soc.h>
  35. #include <linux/compat.h>
  36. #include <linux/mbus.h>
  37. #include <asm-generic/gpio.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #if !defined(CONFIG_PHYLIB)
  40. # error Marvell mvneta requires PHYLIB
  41. #endif
  42. #define CONFIG_NR_CPUS 1
  43. #define ETH_HLEN 14 /* Total octets in header */
  44. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  45. #define WRAP (2 + ETH_HLEN + 4 + 32)
  46. #define MTU 1500
  47. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  48. #define MVNETA_SMI_TIMEOUT 10000
  49. /* Registers */
  50. #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
  51. #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
  52. #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
  53. #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
  54. #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
  55. #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
  56. #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
  57. #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
  58. #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
  59. #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
  60. #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
  61. #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
  62. #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
  63. #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
  64. #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
  65. #define MVNETA_PORT_RX_RESET 0x1cc0
  66. #define MVNETA_PORT_RX_DMA_RESET BIT(0)
  67. #define MVNETA_PHY_ADDR 0x2000
  68. #define MVNETA_PHY_ADDR_MASK 0x1f
  69. #define MVNETA_SMI 0x2004
  70. #define MVNETA_PHY_REG_MASK 0x1f
  71. /* SMI register fields */
  72. #define MVNETA_SMI_DATA_OFFS 0 /* Data */
  73. #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
  74. #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  75. #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  76. #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  77. #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
  78. #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
  79. #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
  80. #define MVNETA_MBUS_RETRY 0x2010
  81. #define MVNETA_UNIT_INTR_CAUSE 0x2080
  82. #define MVNETA_UNIT_CONTROL 0x20B0
  83. #define MVNETA_PHY_POLLING_ENABLE BIT(1)
  84. #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
  85. #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
  86. #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
  87. #define MVNETA_WIN_SIZE_MASK (0xffff0000)
  88. #define MVNETA_BASE_ADDR_ENABLE 0x2290
  89. #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
  90. #define MVNETA_PORT_ACCESS_PROTECT 0x2294
  91. #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
  92. #define MVNETA_PORT_CONFIG 0x2400
  93. #define MVNETA_UNI_PROMISC_MODE BIT(0)
  94. #define MVNETA_DEF_RXQ(q) ((q) << 1)
  95. #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
  96. #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
  97. #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
  98. #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
  99. #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
  100. #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
  101. #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
  102. MVNETA_DEF_RXQ_ARP(q) | \
  103. MVNETA_DEF_RXQ_TCP(q) | \
  104. MVNETA_DEF_RXQ_UDP(q) | \
  105. MVNETA_DEF_RXQ_BPDU(q) | \
  106. MVNETA_TX_UNSET_ERR_SUM | \
  107. MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
  108. #define MVNETA_PORT_CONFIG_EXTEND 0x2404
  109. #define MVNETA_MAC_ADDR_LOW 0x2414
  110. #define MVNETA_MAC_ADDR_HIGH 0x2418
  111. #define MVNETA_SDMA_CONFIG 0x241c
  112. #define MVNETA_SDMA_BRST_SIZE_16 4
  113. #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
  114. #define MVNETA_RX_NO_DATA_SWAP BIT(4)
  115. #define MVNETA_TX_NO_DATA_SWAP BIT(5)
  116. #define MVNETA_DESC_SWAP BIT(6)
  117. #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
  118. #define MVNETA_PORT_STATUS 0x2444
  119. #define MVNETA_TX_IN_PRGRS BIT(1)
  120. #define MVNETA_TX_FIFO_EMPTY BIT(8)
  121. #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
  122. #define MVNETA_SERDES_CFG 0x24A0
  123. #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
  124. #define MVNETA_QSGMII_SERDES_PROTO 0x0667
  125. #define MVNETA_TYPE_PRIO 0x24bc
  126. #define MVNETA_FORCE_UNI BIT(21)
  127. #define MVNETA_TXQ_CMD_1 0x24e4
  128. #define MVNETA_TXQ_CMD 0x2448
  129. #define MVNETA_TXQ_DISABLE_SHIFT 8
  130. #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
  131. #define MVNETA_ACC_MODE 0x2500
  132. #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
  133. #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
  134. #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
  135. #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
  136. /* Exception Interrupt Port/Queue Cause register */
  137. #define MVNETA_INTR_NEW_CAUSE 0x25a0
  138. #define MVNETA_INTR_NEW_MASK 0x25a4
  139. /* bits 0..7 = TXQ SENT, one bit per queue.
  140. * bits 8..15 = RXQ OCCUP, one bit per queue.
  141. * bits 16..23 = RXQ FREE, one bit per queue.
  142. * bit 29 = OLD_REG_SUM, see old reg ?
  143. * bit 30 = TX_ERR_SUM, one bit for 4 ports
  144. * bit 31 = MISC_SUM, one bit for 4 ports
  145. */
  146. #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
  147. #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
  148. #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
  149. #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
  150. #define MVNETA_INTR_OLD_CAUSE 0x25a8
  151. #define MVNETA_INTR_OLD_MASK 0x25ac
  152. /* Data Path Port/Queue Cause Register */
  153. #define MVNETA_INTR_MISC_CAUSE 0x25b0
  154. #define MVNETA_INTR_MISC_MASK 0x25b4
  155. #define MVNETA_INTR_ENABLE 0x25b8
  156. #define MVNETA_RXQ_CMD 0x2680
  157. #define MVNETA_RXQ_DISABLE_SHIFT 8
  158. #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
  159. #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
  160. #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
  161. #define MVNETA_GMAC_CTRL_0 0x2c00
  162. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  163. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  164. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  165. #define MVNETA_GMAC_CTRL_2 0x2c08
  166. #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
  167. #define MVNETA_GMAC2_PORT_RGMII BIT(4)
  168. #define MVNETA_GMAC2_PORT_RESET BIT(6)
  169. #define MVNETA_GMAC_STATUS 0x2c10
  170. #define MVNETA_GMAC_LINK_UP BIT(0)
  171. #define MVNETA_GMAC_SPEED_1000 BIT(1)
  172. #define MVNETA_GMAC_SPEED_100 BIT(2)
  173. #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
  174. #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
  175. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  176. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  177. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  178. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  179. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  180. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  181. #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
  182. #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
  183. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  184. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  185. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  186. #define MVNETA_GMAC_SET_FC_EN BIT(8)
  187. #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
  188. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  189. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  190. #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
  191. #define MVNETA_MIB_COUNTERS_BASE 0x3080
  192. #define MVNETA_MIB_LATE_COLLISION 0x7c
  193. #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
  194. #define MVNETA_DA_FILT_OTH_MCAST 0x3500
  195. #define MVNETA_DA_FILT_UCAST_BASE 0x3600
  196. #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
  197. #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
  198. #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
  199. #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
  200. #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
  201. #define MVNETA_TXQ_DEC_SENT_SHIFT 16
  202. #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
  203. #define MVNETA_TXQ_SENT_DESC_SHIFT 16
  204. #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
  205. #define MVNETA_PORT_TX_RESET 0x3cf0
  206. #define MVNETA_PORT_TX_DMA_RESET BIT(0)
  207. #define MVNETA_TX_MTU 0x3e0c
  208. #define MVNETA_TX_TOKEN_SIZE 0x3e14
  209. #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
  210. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  211. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  212. /* Descriptor ring Macros */
  213. #define MVNETA_QUEUE_NEXT_DESC(q, index) \
  214. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  215. /* Various constants */
  216. /* Coalescing */
  217. #define MVNETA_TXDONE_COAL_PKTS 16
  218. #define MVNETA_RX_COAL_PKTS 32
  219. #define MVNETA_RX_COAL_USEC 100
  220. /* The two bytes Marvell header. Either contains a special value used
  221. * by Marvell switches when a specific hardware mode is enabled (not
  222. * supported by this driver) or is filled automatically by zeroes on
  223. * the RX side. Those two bytes being at the front of the Ethernet
  224. * header, they allow to have the IP header aligned on a 4 bytes
  225. * boundary automatically: the hardware skips those two bytes on its
  226. * own.
  227. */
  228. #define MVNETA_MH_SIZE 2
  229. #define MVNETA_VLAN_TAG_LEN 4
  230. #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
  231. #define MVNETA_TX_CSUM_MAX_SIZE 9800
  232. #define MVNETA_ACC_MODE_EXT 1
  233. /* Timeout constants */
  234. #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
  235. #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
  236. #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
  237. #define MVNETA_TX_MTU_MAX 0x3ffff
  238. /* Max number of Rx descriptors */
  239. #define MVNETA_MAX_RXD 16
  240. /* Max number of Tx descriptors */
  241. #define MVNETA_MAX_TXD 16
  242. /* descriptor aligned size */
  243. #define MVNETA_DESC_ALIGNED_SIZE 32
  244. struct mvneta_port {
  245. void __iomem *base;
  246. struct mvneta_rx_queue *rxqs;
  247. struct mvneta_tx_queue *txqs;
  248. u8 mcast_count[256];
  249. u16 tx_ring_size;
  250. u16 rx_ring_size;
  251. phy_interface_t phy_interface;
  252. unsigned int link;
  253. unsigned int duplex;
  254. unsigned int speed;
  255. int init;
  256. int phyaddr;
  257. struct phy_device *phydev;
  258. #if CONFIG_IS_ENABLED(DM_GPIO)
  259. struct gpio_desc phy_reset_gpio;
  260. #endif
  261. struct mii_dev *bus;
  262. };
  263. /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
  264. * layout of the transmit and reception DMA descriptors, and their
  265. * layout is therefore defined by the hardware design
  266. */
  267. #define MVNETA_TX_L3_OFF_SHIFT 0
  268. #define MVNETA_TX_IP_HLEN_SHIFT 8
  269. #define MVNETA_TX_L4_UDP BIT(16)
  270. #define MVNETA_TX_L3_IP6 BIT(17)
  271. #define MVNETA_TXD_IP_CSUM BIT(18)
  272. #define MVNETA_TXD_Z_PAD BIT(19)
  273. #define MVNETA_TXD_L_DESC BIT(20)
  274. #define MVNETA_TXD_F_DESC BIT(21)
  275. #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
  276. MVNETA_TXD_L_DESC | \
  277. MVNETA_TXD_F_DESC)
  278. #define MVNETA_TX_L4_CSUM_FULL BIT(30)
  279. #define MVNETA_TX_L4_CSUM_NOT BIT(31)
  280. #define MVNETA_RXD_ERR_CRC 0x0
  281. #define MVNETA_RXD_ERR_SUMMARY BIT(16)
  282. #define MVNETA_RXD_ERR_OVERRUN BIT(17)
  283. #define MVNETA_RXD_ERR_LEN BIT(18)
  284. #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
  285. #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
  286. #define MVNETA_RXD_L3_IP4 BIT(25)
  287. #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
  288. #define MVNETA_RXD_L4_CSUM_OK BIT(30)
  289. struct mvneta_tx_desc {
  290. u32 command; /* Options used by HW for packet transmitting.*/
  291. u16 reserverd1; /* csum_l4 (for future use) */
  292. u16 data_size; /* Data size of transmitted packet in bytes */
  293. u32 buf_phys_addr; /* Physical addr of transmitted buffer */
  294. u32 reserved2; /* hw_cmd - (for future use, PMT) */
  295. u32 reserved3[4]; /* Reserved - (for future use) */
  296. };
  297. struct mvneta_rx_desc {
  298. u32 status; /* Info about received packet */
  299. u16 reserved1; /* pnc_info - (for future use, PnC) */
  300. u16 data_size; /* Size of received packet in bytes */
  301. u32 buf_phys_addr; /* Physical address of the buffer */
  302. u32 reserved2; /* pnc_flow_id (for future use, PnC) */
  303. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  304. u16 reserved3; /* prefetch_cmd, for future use */
  305. u16 reserved4; /* csum_l4 - (for future use, PnC) */
  306. u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
  307. u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
  308. };
  309. struct mvneta_tx_queue {
  310. /* Number of this TX queue, in the range 0-7 */
  311. u8 id;
  312. /* Number of TX DMA descriptors in the descriptor ring */
  313. int size;
  314. /* Index of last TX DMA descriptor that was inserted */
  315. int txq_put_index;
  316. /* Index of the TX DMA descriptor to be cleaned up */
  317. int txq_get_index;
  318. /* Virtual address of the TX DMA descriptors array */
  319. struct mvneta_tx_desc *descs;
  320. /* DMA address of the TX DMA descriptors array */
  321. dma_addr_t descs_phys;
  322. /* Index of the last TX DMA descriptor */
  323. int last_desc;
  324. /* Index of the next TX DMA descriptor to process */
  325. int next_desc_to_proc;
  326. };
  327. struct mvneta_rx_queue {
  328. /* rx queue number, in the range 0-7 */
  329. u8 id;
  330. /* num of rx descriptors in the rx descriptor ring */
  331. int size;
  332. /* Virtual address of the RX DMA descriptors array */
  333. struct mvneta_rx_desc *descs;
  334. /* DMA address of the RX DMA descriptors array */
  335. dma_addr_t descs_phys;
  336. /* Index of the last RX DMA descriptor */
  337. int last_desc;
  338. /* Index of the next RX DMA descriptor to process */
  339. int next_desc_to_proc;
  340. };
  341. /* U-Boot doesn't use the queues, so set the number to 1 */
  342. static int rxq_number = 1;
  343. static int txq_number = 1;
  344. static int rxq_def;
  345. struct buffer_location {
  346. struct mvneta_tx_desc *tx_descs;
  347. struct mvneta_rx_desc *rx_descs;
  348. u32 rx_buffers;
  349. };
  350. /*
  351. * All 4 interfaces use the same global buffer, since only one interface
  352. * can be enabled at once
  353. */
  354. static struct buffer_location buffer_loc;
  355. /*
  356. * Page table entries are set to 1MB, or multiples of 1MB
  357. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  358. */
  359. #define BD_SPACE (1 << 20)
  360. /*
  361. * Dummy implementation that can be overwritten by a board
  362. * specific function
  363. */
  364. __weak int board_network_enable(struct mii_dev *bus)
  365. {
  366. return 0;
  367. }
  368. /* Utility/helper methods */
  369. /* Write helper method */
  370. static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
  371. {
  372. writel(data, pp->base + offset);
  373. }
  374. /* Read helper method */
  375. static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
  376. {
  377. return readl(pp->base + offset);
  378. }
  379. /* Clear all MIB counters */
  380. static void mvneta_mib_counters_clear(struct mvneta_port *pp)
  381. {
  382. int i;
  383. /* Perform dummy reads from MIB counters */
  384. for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
  385. mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
  386. }
  387. /* Rx descriptors helper methods */
  388. /* Checks whether the RX descriptor having this status is both the first
  389. * and the last descriptor for the RX packet. Each RX packet is currently
  390. * received through a single RX descriptor, so not having each RX
  391. * descriptor with its first and last bits set is an error
  392. */
  393. static int mvneta_rxq_desc_is_first_last(u32 status)
  394. {
  395. return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
  396. MVNETA_RXD_FIRST_LAST_DESC;
  397. }
  398. /* Add number of descriptors ready to receive new packets */
  399. static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
  400. struct mvneta_rx_queue *rxq,
  401. int ndescs)
  402. {
  403. /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
  404. * be added at once
  405. */
  406. while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
  407. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  408. (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
  409. MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  410. ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
  411. }
  412. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  413. (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  414. }
  415. /* Get number of RX descriptors occupied by received packets */
  416. static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
  417. struct mvneta_rx_queue *rxq)
  418. {
  419. u32 val;
  420. val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
  421. return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
  422. }
  423. /* Update num of rx desc called upon return from rx path or
  424. * from mvneta_rxq_drop_pkts().
  425. */
  426. static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
  427. struct mvneta_rx_queue *rxq,
  428. int rx_done, int rx_filled)
  429. {
  430. u32 val;
  431. if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
  432. val = rx_done |
  433. (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
  434. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  435. return;
  436. }
  437. /* Only 255 descriptors can be added at once */
  438. while ((rx_done > 0) || (rx_filled > 0)) {
  439. if (rx_done <= 0xff) {
  440. val = rx_done;
  441. rx_done = 0;
  442. } else {
  443. val = 0xff;
  444. rx_done -= 0xff;
  445. }
  446. if (rx_filled <= 0xff) {
  447. val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  448. rx_filled = 0;
  449. } else {
  450. val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  451. rx_filled -= 0xff;
  452. }
  453. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  454. }
  455. }
  456. /* Get pointer to next RX descriptor to be processed by SW */
  457. static struct mvneta_rx_desc *
  458. mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
  459. {
  460. int rx_desc = rxq->next_desc_to_proc;
  461. rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
  462. return rxq->descs + rx_desc;
  463. }
  464. /* Tx descriptors helper methods */
  465. /* Update HW with number of TX descriptors to be sent */
  466. static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
  467. struct mvneta_tx_queue *txq,
  468. int pend_desc)
  469. {
  470. u32 val;
  471. /* Only 255 descriptors can be added at once ; Assume caller
  472. * process TX descriptors in quanta less than 256
  473. */
  474. val = pend_desc;
  475. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  476. }
  477. /* Get pointer to next TX descriptor to be processed (send) by HW */
  478. static struct mvneta_tx_desc *
  479. mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
  480. {
  481. int tx_desc = txq->next_desc_to_proc;
  482. txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
  483. return txq->descs + tx_desc;
  484. }
  485. /* Set rxq buf size */
  486. static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
  487. struct mvneta_rx_queue *rxq,
  488. int buf_size)
  489. {
  490. u32 val;
  491. val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
  492. val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
  493. val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
  494. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
  495. }
  496. static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
  497. {
  498. /* phy_addr is set to invalid value for fixed link */
  499. return pp->phyaddr > PHY_MAX_ADDR;
  500. }
  501. /* Start the Ethernet port RX and TX activity */
  502. static void mvneta_port_up(struct mvneta_port *pp)
  503. {
  504. int queue;
  505. u32 q_map;
  506. /* Enable all initialized TXs. */
  507. mvneta_mib_counters_clear(pp);
  508. q_map = 0;
  509. for (queue = 0; queue < txq_number; queue++) {
  510. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  511. if (txq->descs != NULL)
  512. q_map |= (1 << queue);
  513. }
  514. mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
  515. /* Enable all initialized RXQs. */
  516. q_map = 0;
  517. for (queue = 0; queue < rxq_number; queue++) {
  518. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  519. if (rxq->descs != NULL)
  520. q_map |= (1 << queue);
  521. }
  522. mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
  523. }
  524. /* Stop the Ethernet port activity */
  525. static void mvneta_port_down(struct mvneta_port *pp)
  526. {
  527. u32 val;
  528. int count;
  529. /* Stop Rx port activity. Check port Rx activity. */
  530. val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
  531. /* Issue stop command for active channels only */
  532. if (val != 0)
  533. mvreg_write(pp, MVNETA_RXQ_CMD,
  534. val << MVNETA_RXQ_DISABLE_SHIFT);
  535. /* Wait for all Rx activity to terminate. */
  536. count = 0;
  537. do {
  538. if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
  539. netdev_warn(pp->dev,
  540. "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
  541. val);
  542. break;
  543. }
  544. mdelay(1);
  545. val = mvreg_read(pp, MVNETA_RXQ_CMD);
  546. } while (val & 0xff);
  547. /* Stop Tx port activity. Check port Tx activity. Issue stop
  548. * command for active channels only
  549. */
  550. val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
  551. if (val != 0)
  552. mvreg_write(pp, MVNETA_TXQ_CMD,
  553. (val << MVNETA_TXQ_DISABLE_SHIFT));
  554. /* Wait for all Tx activity to terminate. */
  555. count = 0;
  556. do {
  557. if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
  558. netdev_warn(pp->dev,
  559. "TIMEOUT for TX stopped status=0x%08x\n",
  560. val);
  561. break;
  562. }
  563. mdelay(1);
  564. /* Check TX Command reg that all Txqs are stopped */
  565. val = mvreg_read(pp, MVNETA_TXQ_CMD);
  566. } while (val & 0xff);
  567. /* Double check to verify that TX FIFO is empty */
  568. count = 0;
  569. do {
  570. if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
  571. netdev_warn(pp->dev,
  572. "TX FIFO empty timeout status=0x08%x\n",
  573. val);
  574. break;
  575. }
  576. mdelay(1);
  577. val = mvreg_read(pp, MVNETA_PORT_STATUS);
  578. } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
  579. (val & MVNETA_TX_IN_PRGRS));
  580. udelay(200);
  581. }
  582. /* Enable the port by setting the port enable bit of the MAC control register */
  583. static void mvneta_port_enable(struct mvneta_port *pp)
  584. {
  585. u32 val;
  586. /* Enable port */
  587. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  588. val |= MVNETA_GMAC0_PORT_ENABLE;
  589. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  590. }
  591. /* Disable the port and wait for about 200 usec before retuning */
  592. static void mvneta_port_disable(struct mvneta_port *pp)
  593. {
  594. u32 val;
  595. /* Reset the Enable bit in the Serial Control Register */
  596. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  597. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  598. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  599. udelay(200);
  600. }
  601. /* Multicast tables methods */
  602. /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
  603. static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
  604. {
  605. int offset;
  606. u32 val;
  607. if (queue == -1) {
  608. val = 0;
  609. } else {
  610. val = 0x1 | (queue << 1);
  611. val |= (val << 24) | (val << 16) | (val << 8);
  612. }
  613. for (offset = 0; offset <= 0xc; offset += 4)
  614. mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
  615. }
  616. /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
  617. static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
  618. {
  619. int offset;
  620. u32 val;
  621. if (queue == -1) {
  622. val = 0;
  623. } else {
  624. val = 0x1 | (queue << 1);
  625. val |= (val << 24) | (val << 16) | (val << 8);
  626. }
  627. for (offset = 0; offset <= 0xfc; offset += 4)
  628. mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
  629. }
  630. /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
  631. static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
  632. {
  633. int offset;
  634. u32 val;
  635. if (queue == -1) {
  636. memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
  637. val = 0;
  638. } else {
  639. memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
  640. val = 0x1 | (queue << 1);
  641. val |= (val << 24) | (val << 16) | (val << 8);
  642. }
  643. for (offset = 0; offset <= 0xfc; offset += 4)
  644. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  645. }
  646. /* This method sets defaults to the NETA port:
  647. * Clears interrupt Cause and Mask registers.
  648. * Clears all MAC tables.
  649. * Sets defaults to all registers.
  650. * Resets RX and TX descriptor rings.
  651. * Resets PHY.
  652. * This method can be called after mvneta_port_down() to return the port
  653. * settings to defaults.
  654. */
  655. static void mvneta_defaults_set(struct mvneta_port *pp)
  656. {
  657. int cpu;
  658. int queue;
  659. u32 val;
  660. /* Clear all Cause registers */
  661. mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
  662. mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
  663. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  664. /* Mask all interrupts */
  665. mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
  666. mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
  667. mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
  668. mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
  669. /* Enable MBUS Retry bit16 */
  670. mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
  671. /* Set CPU queue access map - all CPUs have access to all RX
  672. * queues and to all TX queues
  673. */
  674. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
  675. mvreg_write(pp, MVNETA_CPU_MAP(cpu),
  676. (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
  677. MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
  678. /* Reset RX and TX DMAs */
  679. mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
  680. mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
  681. /* Disable Legacy WRR, Disable EJP, Release from reset */
  682. mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
  683. for (queue = 0; queue < txq_number; queue++) {
  684. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
  685. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
  686. }
  687. mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
  688. mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
  689. /* Set Port Acceleration Mode */
  690. val = MVNETA_ACC_MODE_EXT;
  691. mvreg_write(pp, MVNETA_ACC_MODE, val);
  692. /* Update val of portCfg register accordingly with all RxQueue types */
  693. val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
  694. mvreg_write(pp, MVNETA_PORT_CONFIG, val);
  695. val = 0;
  696. mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
  697. mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
  698. /* Build PORT_SDMA_CONFIG_REG */
  699. val = 0;
  700. /* Default burst size */
  701. val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  702. val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  703. val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
  704. /* Assign port SDMA configuration */
  705. mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
  706. /* Enable PHY polling in hardware if not in fixed-link mode */
  707. if (!mvneta_port_is_fixed_link(pp)) {
  708. val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
  709. val |= MVNETA_PHY_POLLING_ENABLE;
  710. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  711. }
  712. mvneta_set_ucast_table(pp, -1);
  713. mvneta_set_special_mcast_table(pp, -1);
  714. mvneta_set_other_mcast_table(pp, -1);
  715. }
  716. /* Set unicast address */
  717. static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
  718. int queue)
  719. {
  720. unsigned int unicast_reg;
  721. unsigned int tbl_offset;
  722. unsigned int reg_offset;
  723. /* Locate the Unicast table entry */
  724. last_nibble = (0xf & last_nibble);
  725. /* offset from unicast tbl base */
  726. tbl_offset = (last_nibble / 4) * 4;
  727. /* offset within the above reg */
  728. reg_offset = last_nibble % 4;
  729. unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
  730. if (queue == -1) {
  731. /* Clear accepts frame bit at specified unicast DA tbl entry */
  732. unicast_reg &= ~(0xff << (8 * reg_offset));
  733. } else {
  734. unicast_reg &= ~(0xff << (8 * reg_offset));
  735. unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
  736. }
  737. mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
  738. }
  739. /* Set mac address */
  740. static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
  741. int queue)
  742. {
  743. unsigned int mac_h;
  744. unsigned int mac_l;
  745. if (queue != -1) {
  746. mac_l = (addr[4] << 8) | (addr[5]);
  747. mac_h = (addr[0] << 24) | (addr[1] << 16) |
  748. (addr[2] << 8) | (addr[3] << 0);
  749. mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
  750. mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
  751. }
  752. /* Accept frames of this address */
  753. mvneta_set_ucast_addr(pp, addr[5], queue);
  754. }
  755. static int mvneta_write_hwaddr(struct udevice *dev)
  756. {
  757. mvneta_mac_addr_set(dev_get_priv(dev),
  758. ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
  759. rxq_def);
  760. return 0;
  761. }
  762. /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
  763. static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
  764. u32 phys_addr, u32 cookie)
  765. {
  766. rx_desc->buf_cookie = cookie;
  767. rx_desc->buf_phys_addr = phys_addr;
  768. }
  769. /* Decrement sent descriptors counter */
  770. static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
  771. struct mvneta_tx_queue *txq,
  772. int sent_desc)
  773. {
  774. u32 val;
  775. /* Only 255 TX descriptors can be updated at once */
  776. while (sent_desc > 0xff) {
  777. val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
  778. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  779. sent_desc = sent_desc - 0xff;
  780. }
  781. val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
  782. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  783. }
  784. /* Get number of TX descriptors already sent by HW */
  785. static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
  786. struct mvneta_tx_queue *txq)
  787. {
  788. u32 val;
  789. int sent_desc;
  790. val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
  791. sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
  792. MVNETA_TXQ_SENT_DESC_SHIFT;
  793. return sent_desc;
  794. }
  795. /* Display more error info */
  796. static void mvneta_rx_error(struct mvneta_port *pp,
  797. struct mvneta_rx_desc *rx_desc)
  798. {
  799. u32 status = rx_desc->status;
  800. if (!mvneta_rxq_desc_is_first_last(status)) {
  801. netdev_err(pp->dev,
  802. "bad rx status %08x (buffer oversize), size=%d\n",
  803. status, rx_desc->data_size);
  804. return;
  805. }
  806. switch (status & MVNETA_RXD_ERR_CODE_MASK) {
  807. case MVNETA_RXD_ERR_CRC:
  808. netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
  809. status, rx_desc->data_size);
  810. break;
  811. case MVNETA_RXD_ERR_OVERRUN:
  812. netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
  813. status, rx_desc->data_size);
  814. break;
  815. case MVNETA_RXD_ERR_LEN:
  816. netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
  817. status, rx_desc->data_size);
  818. break;
  819. case MVNETA_RXD_ERR_RESOURCE:
  820. netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
  821. status, rx_desc->data_size);
  822. break;
  823. }
  824. }
  825. static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
  826. int rxq)
  827. {
  828. return &pp->rxqs[rxq];
  829. }
  830. /* Drop packets received by the RXQ and free buffers */
  831. static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
  832. struct mvneta_rx_queue *rxq)
  833. {
  834. int rx_done;
  835. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  836. if (rx_done)
  837. mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
  838. }
  839. /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
  840. static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
  841. int num)
  842. {
  843. int i;
  844. for (i = 0; i < num; i++) {
  845. u32 addr;
  846. /* U-Boot special: Fill in the rx buffer addresses */
  847. addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
  848. mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
  849. }
  850. /* Add this number of RX descriptors as non occupied (ready to
  851. * get packets)
  852. */
  853. mvneta_rxq_non_occup_desc_add(pp, rxq, i);
  854. return 0;
  855. }
  856. /* Rx/Tx queue initialization/cleanup methods */
  857. /* Create a specified RX queue */
  858. static int mvneta_rxq_init(struct mvneta_port *pp,
  859. struct mvneta_rx_queue *rxq)
  860. {
  861. rxq->size = pp->rx_ring_size;
  862. /* Allocate memory for RX descriptors */
  863. rxq->descs_phys = (dma_addr_t)rxq->descs;
  864. if (rxq->descs == NULL)
  865. return -ENOMEM;
  866. WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
  867. rxq->last_desc = rxq->size - 1;
  868. /* Set Rx descriptors queue starting address */
  869. mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
  870. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
  871. /* Fill RXQ with buffers from RX pool */
  872. mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
  873. mvneta_rxq_fill(pp, rxq, rxq->size);
  874. return 0;
  875. }
  876. /* Cleanup Rx queue */
  877. static void mvneta_rxq_deinit(struct mvneta_port *pp,
  878. struct mvneta_rx_queue *rxq)
  879. {
  880. mvneta_rxq_drop_pkts(pp, rxq);
  881. rxq->descs = NULL;
  882. rxq->last_desc = 0;
  883. rxq->next_desc_to_proc = 0;
  884. rxq->descs_phys = 0;
  885. }
  886. /* Create and initialize a tx queue */
  887. static int mvneta_txq_init(struct mvneta_port *pp,
  888. struct mvneta_tx_queue *txq)
  889. {
  890. txq->size = pp->tx_ring_size;
  891. /* Allocate memory for TX descriptors */
  892. txq->descs_phys = (dma_addr_t)txq->descs;
  893. if (txq->descs == NULL)
  894. return -ENOMEM;
  895. WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
  896. txq->last_desc = txq->size - 1;
  897. /* Set maximum bandwidth for enabled TXQs */
  898. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
  899. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
  900. /* Set Tx descriptors queue starting address */
  901. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
  902. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
  903. return 0;
  904. }
  905. /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
  906. static void mvneta_txq_deinit(struct mvneta_port *pp,
  907. struct mvneta_tx_queue *txq)
  908. {
  909. txq->descs = NULL;
  910. txq->last_desc = 0;
  911. txq->next_desc_to_proc = 0;
  912. txq->descs_phys = 0;
  913. /* Set minimum bandwidth for disabled TXQs */
  914. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
  915. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
  916. /* Set Tx descriptors queue starting address and size */
  917. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
  918. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
  919. }
  920. /* Cleanup all Tx queues */
  921. static void mvneta_cleanup_txqs(struct mvneta_port *pp)
  922. {
  923. int queue;
  924. for (queue = 0; queue < txq_number; queue++)
  925. mvneta_txq_deinit(pp, &pp->txqs[queue]);
  926. }
  927. /* Cleanup all Rx queues */
  928. static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
  929. {
  930. int queue;
  931. for (queue = 0; queue < rxq_number; queue++)
  932. mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
  933. }
  934. /* Init all Rx queues */
  935. static int mvneta_setup_rxqs(struct mvneta_port *pp)
  936. {
  937. int queue;
  938. for (queue = 0; queue < rxq_number; queue++) {
  939. int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
  940. if (err) {
  941. netdev_err(pp->dev, "%s: can't create rxq=%d\n",
  942. __func__, queue);
  943. mvneta_cleanup_rxqs(pp);
  944. return err;
  945. }
  946. }
  947. return 0;
  948. }
  949. /* Init all tx queues */
  950. static int mvneta_setup_txqs(struct mvneta_port *pp)
  951. {
  952. int queue;
  953. for (queue = 0; queue < txq_number; queue++) {
  954. int err = mvneta_txq_init(pp, &pp->txqs[queue]);
  955. if (err) {
  956. netdev_err(pp->dev, "%s: can't create txq=%d\n",
  957. __func__, queue);
  958. mvneta_cleanup_txqs(pp);
  959. return err;
  960. }
  961. }
  962. return 0;
  963. }
  964. static void mvneta_start_dev(struct mvneta_port *pp)
  965. {
  966. /* start the Rx/Tx activity */
  967. mvneta_port_enable(pp);
  968. }
  969. static void mvneta_adjust_link(struct udevice *dev)
  970. {
  971. struct mvneta_port *pp = dev_get_priv(dev);
  972. struct phy_device *phydev = pp->phydev;
  973. int status_change = 0;
  974. if (mvneta_port_is_fixed_link(pp)) {
  975. debug("Using fixed link, skip link adjust\n");
  976. return;
  977. }
  978. if (phydev->link) {
  979. if ((pp->speed != phydev->speed) ||
  980. (pp->duplex != phydev->duplex)) {
  981. u32 val;
  982. val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  983. val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  984. MVNETA_GMAC_CONFIG_GMII_SPEED |
  985. MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  986. MVNETA_GMAC_AN_SPEED_EN |
  987. MVNETA_GMAC_AN_DUPLEX_EN);
  988. if (phydev->duplex)
  989. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  990. if (phydev->speed == SPEED_1000)
  991. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  992. else
  993. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  994. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  995. pp->duplex = phydev->duplex;
  996. pp->speed = phydev->speed;
  997. }
  998. }
  999. if (phydev->link != pp->link) {
  1000. if (!phydev->link) {
  1001. pp->duplex = -1;
  1002. pp->speed = 0;
  1003. }
  1004. pp->link = phydev->link;
  1005. status_change = 1;
  1006. }
  1007. if (status_change) {
  1008. if (phydev->link) {
  1009. u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  1010. val |= (MVNETA_GMAC_FORCE_LINK_PASS |
  1011. MVNETA_GMAC_FORCE_LINK_DOWN);
  1012. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1013. mvneta_port_up(pp);
  1014. } else {
  1015. mvneta_port_down(pp);
  1016. }
  1017. }
  1018. }
  1019. static int mvneta_open(struct udevice *dev)
  1020. {
  1021. struct mvneta_port *pp = dev_get_priv(dev);
  1022. int ret;
  1023. ret = mvneta_setup_rxqs(pp);
  1024. if (ret)
  1025. return ret;
  1026. ret = mvneta_setup_txqs(pp);
  1027. if (ret)
  1028. return ret;
  1029. mvneta_adjust_link(dev);
  1030. mvneta_start_dev(pp);
  1031. return 0;
  1032. }
  1033. /* Initialize hw */
  1034. static int mvneta_init2(struct mvneta_port *pp)
  1035. {
  1036. int queue;
  1037. /* Disable port */
  1038. mvneta_port_disable(pp);
  1039. /* Set port default values */
  1040. mvneta_defaults_set(pp);
  1041. pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
  1042. GFP_KERNEL);
  1043. if (!pp->txqs)
  1044. return -ENOMEM;
  1045. /* U-Boot special: use preallocated area */
  1046. pp->txqs[0].descs = buffer_loc.tx_descs;
  1047. /* Initialize TX descriptor rings */
  1048. for (queue = 0; queue < txq_number; queue++) {
  1049. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  1050. txq->id = queue;
  1051. txq->size = pp->tx_ring_size;
  1052. }
  1053. pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
  1054. GFP_KERNEL);
  1055. if (!pp->rxqs) {
  1056. kfree(pp->txqs);
  1057. return -ENOMEM;
  1058. }
  1059. /* U-Boot special: use preallocated area */
  1060. pp->rxqs[0].descs = buffer_loc.rx_descs;
  1061. /* Create Rx descriptor rings */
  1062. for (queue = 0; queue < rxq_number; queue++) {
  1063. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  1064. rxq->id = queue;
  1065. rxq->size = pp->rx_ring_size;
  1066. }
  1067. return 0;
  1068. }
  1069. /* platform glue : initialize decoding windows */
  1070. /*
  1071. * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
  1072. * First layer is: GbE Address window that resides inside the GBE unit,
  1073. * Second layer is: Fabric address window which is located in the NIC400
  1074. * (South Fabric).
  1075. * To simplify the address decode configuration for Armada3700, we bypass the
  1076. * first layer of GBE decode window by setting the first window to 4GB.
  1077. */
  1078. static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
  1079. {
  1080. /*
  1081. * Set window size to 4GB, to bypass GBE address decode, leave the
  1082. * work to MBUS decode window
  1083. */
  1084. mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
  1085. /* Enable GBE address decode window 0 by set bit 0 to 0 */
  1086. clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
  1087. MVNETA_BASE_ADDR_ENABLE_BIT);
  1088. /* Set GBE address decode window 0 to full Access (read or write) */
  1089. setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
  1090. MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
  1091. }
  1092. static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
  1093. {
  1094. const struct mbus_dram_target_info *dram;
  1095. u32 win_enable;
  1096. u32 win_protect;
  1097. int i;
  1098. dram = mvebu_mbus_dram_info();
  1099. for (i = 0; i < 6; i++) {
  1100. mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
  1101. mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
  1102. if (i < 4)
  1103. mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
  1104. }
  1105. win_enable = 0x3f;
  1106. win_protect = 0;
  1107. for (i = 0; i < dram->num_cs; i++) {
  1108. const struct mbus_dram_window *cs = dram->cs + i;
  1109. mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
  1110. (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
  1111. mvreg_write(pp, MVNETA_WIN_SIZE(i),
  1112. (cs->size - 1) & 0xffff0000);
  1113. win_enable &= ~(1 << i);
  1114. win_protect |= 3 << (2 * i);
  1115. }
  1116. mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
  1117. }
  1118. /* Power up the port */
  1119. static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
  1120. {
  1121. u32 ctrl;
  1122. /* MAC Cause register should be cleared */
  1123. mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
  1124. ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  1125. /* Even though it might look weird, when we're configured in
  1126. * SGMII or QSGMII mode, the RGMII bit needs to be set.
  1127. */
  1128. switch (phy_mode) {
  1129. case PHY_INTERFACE_MODE_QSGMII:
  1130. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
  1131. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1132. break;
  1133. case PHY_INTERFACE_MODE_SGMII:
  1134. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
  1135. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1136. break;
  1137. case PHY_INTERFACE_MODE_RGMII:
  1138. case PHY_INTERFACE_MODE_RGMII_ID:
  1139. ctrl |= MVNETA_GMAC2_PORT_RGMII;
  1140. break;
  1141. default:
  1142. return -EINVAL;
  1143. }
  1144. /* Cancel Port Reset */
  1145. ctrl &= ~MVNETA_GMAC2_PORT_RESET;
  1146. mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
  1147. while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
  1148. MVNETA_GMAC2_PORT_RESET) != 0)
  1149. continue;
  1150. return 0;
  1151. }
  1152. /* Device initialization routine */
  1153. static int mvneta_init(struct udevice *dev)
  1154. {
  1155. struct eth_pdata *pdata = dev_get_platdata(dev);
  1156. struct mvneta_port *pp = dev_get_priv(dev);
  1157. int err;
  1158. pp->tx_ring_size = MVNETA_MAX_TXD;
  1159. pp->rx_ring_size = MVNETA_MAX_RXD;
  1160. err = mvneta_init2(pp);
  1161. if (err < 0) {
  1162. dev_err(&pdev->dev, "can't init eth hal\n");
  1163. return err;
  1164. }
  1165. mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
  1166. err = mvneta_port_power_up(pp, pp->phy_interface);
  1167. if (err < 0) {
  1168. dev_err(&pdev->dev, "can't power up port\n");
  1169. return err;
  1170. }
  1171. /* Call open() now as it needs to be done before runing send() */
  1172. mvneta_open(dev);
  1173. return 0;
  1174. }
  1175. /* U-Boot only functions follow here */
  1176. /* SMI / MDIO functions */
  1177. static int smi_wait_ready(struct mvneta_port *pp)
  1178. {
  1179. u32 timeout = MVNETA_SMI_TIMEOUT;
  1180. u32 smi_reg;
  1181. /* wait till the SMI is not busy */
  1182. do {
  1183. /* read smi register */
  1184. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1185. if (timeout-- == 0) {
  1186. printf("Error: SMI busy timeout\n");
  1187. return -EFAULT;
  1188. }
  1189. } while (smi_reg & MVNETA_SMI_BUSY);
  1190. return 0;
  1191. }
  1192. /*
  1193. * mvneta_mdio_read - miiphy_read callback function.
  1194. *
  1195. * Returns 16bit phy register value, or 0xffff on error
  1196. */
  1197. static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  1198. {
  1199. struct mvneta_port *pp = bus->priv;
  1200. u32 smi_reg;
  1201. u32 timeout;
  1202. /* check parameters */
  1203. if (addr > MVNETA_PHY_ADDR_MASK) {
  1204. printf("Error: Invalid PHY address %d\n", addr);
  1205. return -EFAULT;
  1206. }
  1207. if (reg > MVNETA_PHY_REG_MASK) {
  1208. printf("Err: Invalid register offset %d\n", reg);
  1209. return -EFAULT;
  1210. }
  1211. /* wait till the SMI is not busy */
  1212. if (smi_wait_ready(pp) < 0)
  1213. return -EFAULT;
  1214. /* fill the phy address and regiser offset and read opcode */
  1215. smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1216. | (reg << MVNETA_SMI_REG_ADDR_OFFS)
  1217. | MVNETA_SMI_OPCODE_READ;
  1218. /* write the smi register */
  1219. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1220. /* wait till read value is ready */
  1221. timeout = MVNETA_SMI_TIMEOUT;
  1222. do {
  1223. /* read smi register */
  1224. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1225. if (timeout-- == 0) {
  1226. printf("Err: SMI read ready timeout\n");
  1227. return -EFAULT;
  1228. }
  1229. } while (!(smi_reg & MVNETA_SMI_READ_VALID));
  1230. /* Wait for the data to update in the SMI register */
  1231. for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
  1232. ;
  1233. return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
  1234. }
  1235. /*
  1236. * mvneta_mdio_write - miiphy_write callback function.
  1237. *
  1238. * Returns 0 if write succeed, -EINVAL on bad parameters
  1239. * -ETIME on timeout
  1240. */
  1241. static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  1242. u16 value)
  1243. {
  1244. struct mvneta_port *pp = bus->priv;
  1245. u32 smi_reg;
  1246. /* check parameters */
  1247. if (addr > MVNETA_PHY_ADDR_MASK) {
  1248. printf("Error: Invalid PHY address %d\n", addr);
  1249. return -EFAULT;
  1250. }
  1251. if (reg > MVNETA_PHY_REG_MASK) {
  1252. printf("Err: Invalid register offset %d\n", reg);
  1253. return -EFAULT;
  1254. }
  1255. /* wait till the SMI is not busy */
  1256. if (smi_wait_ready(pp) < 0)
  1257. return -EFAULT;
  1258. /* fill the phy addr and reg offset and write opcode and data */
  1259. smi_reg = value << MVNETA_SMI_DATA_OFFS;
  1260. smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1261. | (reg << MVNETA_SMI_REG_ADDR_OFFS);
  1262. smi_reg &= ~MVNETA_SMI_OPCODE_READ;
  1263. /* write the smi register */
  1264. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1265. return 0;
  1266. }
  1267. static int mvneta_start(struct udevice *dev)
  1268. {
  1269. struct mvneta_port *pp = dev_get_priv(dev);
  1270. struct phy_device *phydev;
  1271. mvneta_port_power_up(pp, pp->phy_interface);
  1272. if (!pp->init || pp->link == 0) {
  1273. if (mvneta_port_is_fixed_link(pp)) {
  1274. u32 val;
  1275. pp->init = 1;
  1276. pp->link = 1;
  1277. mvneta_init(dev);
  1278. val = MVNETA_GMAC_FORCE_LINK_UP |
  1279. MVNETA_GMAC_IB_BYPASS_AN_EN |
  1280. MVNETA_GMAC_SET_FC_EN |
  1281. MVNETA_GMAC_ADVERT_FC_EN |
  1282. MVNETA_GMAC_SAMPLE_TX_CFG_EN;
  1283. if (pp->duplex)
  1284. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  1285. if (pp->speed == SPEED_1000)
  1286. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  1287. else if (pp->speed == SPEED_100)
  1288. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  1289. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1290. } else {
  1291. /* Set phy address of the port */
  1292. mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
  1293. phydev = phy_connect(pp->bus, pp->phyaddr, dev,
  1294. pp->phy_interface);
  1295. if (!phydev) {
  1296. printf("phy_connect failed\n");
  1297. return -ENODEV;
  1298. }
  1299. pp->phydev = phydev;
  1300. phy_config(phydev);
  1301. phy_startup(phydev);
  1302. if (!phydev->link) {
  1303. printf("%s: No link.\n", phydev->dev->name);
  1304. return -1;
  1305. }
  1306. /* Full init on first call */
  1307. mvneta_init(dev);
  1308. pp->init = 1;
  1309. return 0;
  1310. }
  1311. }
  1312. /* Upon all following calls, this is enough */
  1313. mvneta_port_up(pp);
  1314. mvneta_port_enable(pp);
  1315. return 0;
  1316. }
  1317. static int mvneta_send(struct udevice *dev, void *packet, int length)
  1318. {
  1319. struct mvneta_port *pp = dev_get_priv(dev);
  1320. struct mvneta_tx_queue *txq = &pp->txqs[0];
  1321. struct mvneta_tx_desc *tx_desc;
  1322. int sent_desc;
  1323. u32 timeout = 0;
  1324. /* Get a descriptor for the first part of the packet */
  1325. tx_desc = mvneta_txq_next_desc_get(txq);
  1326. tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
  1327. tx_desc->data_size = length;
  1328. flush_dcache_range((ulong)packet,
  1329. (ulong)packet + ALIGN(length, PKTALIGN));
  1330. /* First and Last descriptor */
  1331. tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
  1332. mvneta_txq_pend_desc_add(pp, txq, 1);
  1333. /* Wait for packet to be sent (queue might help with speed here) */
  1334. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1335. while (!sent_desc) {
  1336. if (timeout++ > 10000) {
  1337. printf("timeout: packet not sent\n");
  1338. return -1;
  1339. }
  1340. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1341. }
  1342. /* txDone has increased - hw sent packet */
  1343. mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
  1344. return 0;
  1345. }
  1346. static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
  1347. {
  1348. struct mvneta_port *pp = dev_get_priv(dev);
  1349. int rx_done;
  1350. struct mvneta_rx_queue *rxq;
  1351. int rx_bytes = 0;
  1352. /* get rx queue */
  1353. rxq = mvneta_rxq_handle_get(pp, rxq_def);
  1354. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  1355. if (rx_done) {
  1356. struct mvneta_rx_desc *rx_desc;
  1357. unsigned char *data;
  1358. u32 rx_status;
  1359. /*
  1360. * No cache invalidation needed here, since the desc's are
  1361. * located in a uncached memory region
  1362. */
  1363. rx_desc = mvneta_rxq_next_desc_get(rxq);
  1364. rx_status = rx_desc->status;
  1365. if (!mvneta_rxq_desc_is_first_last(rx_status) ||
  1366. (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
  1367. mvneta_rx_error(pp, rx_desc);
  1368. /* leave the descriptor untouched */
  1369. return -EIO;
  1370. }
  1371. /* 2 bytes for marvell header. 4 bytes for crc */
  1372. rx_bytes = rx_desc->data_size - 6;
  1373. /* give packet to stack - skip on first 2 bytes */
  1374. data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
  1375. /*
  1376. * No cache invalidation needed here, since the rx_buffer's are
  1377. * located in a uncached memory region
  1378. */
  1379. *packetp = data;
  1380. /*
  1381. * Only mark one descriptor as free
  1382. * since only one was processed
  1383. */
  1384. mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
  1385. }
  1386. return rx_bytes;
  1387. }
  1388. static int mvneta_probe(struct udevice *dev)
  1389. {
  1390. struct eth_pdata *pdata = dev_get_platdata(dev);
  1391. struct mvneta_port *pp = dev_get_priv(dev);
  1392. void *blob = (void *)gd->fdt_blob;
  1393. int node = dev_of_offset(dev);
  1394. struct mii_dev *bus;
  1395. unsigned long addr;
  1396. void *bd_space;
  1397. int ret;
  1398. int fl_node;
  1399. /*
  1400. * Allocate buffer area for descs and rx_buffers. This is only
  1401. * done once for all interfaces. As only one interface can
  1402. * be active. Make this area DMA safe by disabling the D-cache
  1403. */
  1404. if (!buffer_loc.tx_descs) {
  1405. u32 size;
  1406. /* Align buffer area for descs and rx_buffers to 1MiB */
  1407. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  1408. flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
  1409. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
  1410. DCACHE_OFF);
  1411. buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
  1412. size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
  1413. ARCH_DMA_MINALIGN);
  1414. memset(buffer_loc.tx_descs, 0, size);
  1415. buffer_loc.rx_descs = (struct mvneta_rx_desc *)
  1416. ((phys_addr_t)bd_space + size);
  1417. size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
  1418. ARCH_DMA_MINALIGN);
  1419. buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
  1420. }
  1421. pp->base = (void __iomem *)pdata->iobase;
  1422. /* Configure MBUS address windows */
  1423. if (device_is_compatible(dev, "marvell,armada-3700-neta"))
  1424. mvneta_bypass_mbus_windows(pp);
  1425. else
  1426. mvneta_conf_mbus_windows(pp);
  1427. /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
  1428. pp->phy_interface = pdata->phy_interface;
  1429. /* fetch 'fixed-link' property from 'neta' node */
  1430. fl_node = fdt_subnode_offset(blob, node, "fixed-link");
  1431. if (fl_node != -FDT_ERR_NOTFOUND) {
  1432. /* set phy_addr to invalid value for fixed link */
  1433. pp->phyaddr = PHY_MAX_ADDR + 1;
  1434. pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  1435. pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  1436. } else {
  1437. /* Now read phyaddr from DT */
  1438. addr = fdtdec_get_int(blob, node, "phy", 0);
  1439. addr = fdt_node_offset_by_phandle(blob, addr);
  1440. pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  1441. }
  1442. bus = mdio_alloc();
  1443. if (!bus) {
  1444. printf("Failed to allocate MDIO bus\n");
  1445. return -ENOMEM;
  1446. }
  1447. bus->read = mvneta_mdio_read;
  1448. bus->write = mvneta_mdio_write;
  1449. snprintf(bus->name, sizeof(bus->name), dev->name);
  1450. bus->priv = (void *)pp;
  1451. pp->bus = bus;
  1452. ret = mdio_register(bus);
  1453. if (ret)
  1454. return ret;
  1455. #if CONFIG_IS_ENABLED(DM_GPIO)
  1456. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1457. &pp->phy_reset_gpio, GPIOD_IS_OUT);
  1458. if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
  1459. dm_gpio_set_value(&pp->phy_reset_gpio, 1);
  1460. mdelay(10);
  1461. dm_gpio_set_value(&pp->phy_reset_gpio, 0);
  1462. }
  1463. #endif
  1464. return board_network_enable(bus);
  1465. }
  1466. static void mvneta_stop(struct udevice *dev)
  1467. {
  1468. struct mvneta_port *pp = dev_get_priv(dev);
  1469. mvneta_port_down(pp);
  1470. mvneta_port_disable(pp);
  1471. }
  1472. static const struct eth_ops mvneta_ops = {
  1473. .start = mvneta_start,
  1474. .send = mvneta_send,
  1475. .recv = mvneta_recv,
  1476. .stop = mvneta_stop,
  1477. .write_hwaddr = mvneta_write_hwaddr,
  1478. };
  1479. static int mvneta_ofdata_to_platdata(struct udevice *dev)
  1480. {
  1481. struct eth_pdata *pdata = dev_get_platdata(dev);
  1482. const char *phy_mode;
  1483. pdata->iobase = dev_read_addr(dev);
  1484. /* Get phy-mode / phy_interface from DT */
  1485. pdata->phy_interface = -1;
  1486. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1487. NULL);
  1488. if (phy_mode)
  1489. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1490. if (pdata->phy_interface == -1) {
  1491. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1492. return -EINVAL;
  1493. }
  1494. return 0;
  1495. }
  1496. static const struct udevice_id mvneta_ids[] = {
  1497. { .compatible = "marvell,armada-370-neta" },
  1498. { .compatible = "marvell,armada-xp-neta" },
  1499. { .compatible = "marvell,armada-3700-neta" },
  1500. { }
  1501. };
  1502. U_BOOT_DRIVER(mvneta) = {
  1503. .name = "mvneta",
  1504. .id = UCLASS_ETH,
  1505. .of_match = mvneta_ids,
  1506. .ofdata_to_platdata = mvneta_ofdata_to_platdata,
  1507. .probe = mvneta_probe,
  1508. .ops = &mvneta_ops,
  1509. .priv_auto_alloc_size = sizeof(struct mvneta_port),
  1510. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1511. };