clk-rcar-gen2.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas RCar Gen2 CPG MSSR driver
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on the following driver from Linux kernel:
  8. * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
  9. *
  10. * Copyright (C) 2016 Glider bvba
  11. */
  12. #include <common.h>
  13. #include <clk-uclass.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <log.h>
  17. #include <asm/io.h>
  18. #include <dt-bindings/clock/renesas-cpg-mssr.h>
  19. #include "renesas-cpg-mssr.h"
  20. #include "rcar-gen2-cpg.h"
  21. #define CPG_RST_MODEMR 0x0060
  22. #define CPG_PLL0CR 0x00d8
  23. #define CPG_SDCKCR 0x0074
  24. struct clk_div_table {
  25. u8 val;
  26. u8 div;
  27. };
  28. /* SDHI divisors */
  29. static const struct clk_div_table cpg_sdh_div_table[] = {
  30. { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
  31. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  32. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
  33. };
  34. static const struct clk_div_table cpg_sd01_div_table[] = {
  35. { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
  36. { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
  37. { 0, 0 },
  38. };
  39. static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
  40. {
  41. for (;;) {
  42. if (!(*table).div)
  43. return 0xff;
  44. if ((*table).val == val)
  45. return (*table).div;
  46. table++;
  47. }
  48. }
  49. static int gen2_clk_enable(struct clk *clk)
  50. {
  51. struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  52. return renesas_clk_endisable(clk, priv->base, true);
  53. }
  54. static int gen2_clk_disable(struct clk *clk)
  55. {
  56. struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  57. return renesas_clk_endisable(clk, priv->base, false);
  58. }
  59. static ulong gen2_clk_get_rate(struct clk *clk)
  60. {
  61. struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  62. struct cpg_mssr_info *info = priv->info;
  63. struct clk parent;
  64. const struct cpg_core_clk *core;
  65. const struct rcar_gen2_cpg_pll_config *pll_config =
  66. priv->cpg_pll_config;
  67. u32 value, mult, div, rate = 0;
  68. int ret;
  69. debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
  70. ret = renesas_clk_get_parent(clk, info, &parent);
  71. if (ret) {
  72. printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  73. return ret;
  74. }
  75. if (renesas_clk_is_mod(clk)) {
  76. rate = gen2_clk_get_rate(&parent);
  77. debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
  78. __func__, __LINE__, parent.id, rate);
  79. return rate;
  80. }
  81. ret = renesas_clk_get_core(clk, info, &core);
  82. if (ret)
  83. return ret;
  84. switch (core->type) {
  85. case CLK_TYPE_IN:
  86. if (core->id == info->clk_extal_id) {
  87. rate = clk_get_rate(&priv->clk_extal);
  88. debug("%s[%i] EXTAL clk: rate=%u\n",
  89. __func__, __LINE__, rate);
  90. return rate;
  91. }
  92. if (core->id == info->clk_extal_usb_id) {
  93. rate = clk_get_rate(&priv->clk_extal_usb);
  94. debug("%s[%i] EXTALR clk: rate=%u\n",
  95. __func__, __LINE__, rate);
  96. return rate;
  97. }
  98. return -EINVAL;
  99. case CLK_TYPE_FF:
  100. rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
  101. debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
  102. __func__, __LINE__,
  103. core->parent, core->mult, core->div, rate);
  104. return rate;
  105. case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
  106. value = (readl(priv->base + core->offset) & 0x3f) + 1;
  107. rate = gen2_clk_get_rate(&parent) / value;
  108. debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
  109. __func__, __LINE__,
  110. core->parent, value, rate);
  111. return rate;
  112. case CLK_TYPE_GEN2_MAIN:
  113. rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
  114. debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
  115. __func__, __LINE__,
  116. core->parent, pll_config->extal_div, rate);
  117. return rate;
  118. case CLK_TYPE_GEN2_PLL0:
  119. /*
  120. * PLL0 is a configurable multiplier clock except on R-Car
  121. * V2H/E2. Register the PLL0 clock as a fixed factor clock for
  122. * now as there's no generic multiplier clock implementation and
  123. * we currently have no need to change the multiplier value.
  124. */
  125. mult = pll_config->pll0_mult;
  126. if (!mult) {
  127. value = readl(priv->base + CPG_PLL0CR);
  128. mult = (((value >> 24) & 0x7f) + 1) * 2;
  129. }
  130. rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
  131. debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
  132. __func__, __LINE__, core->parent, mult, rate);
  133. return rate;
  134. case CLK_TYPE_GEN2_PLL1:
  135. rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
  136. debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
  137. __func__, __LINE__,
  138. core->parent, pll_config->pll1_mult, rate);
  139. return rate;
  140. case CLK_TYPE_GEN2_PLL3:
  141. rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
  142. debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
  143. __func__, __LINE__,
  144. core->parent, pll_config->pll3_mult, rate);
  145. return rate;
  146. case CLK_TYPE_GEN2_SDH:
  147. value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
  148. div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
  149. rate = gen2_clk_get_rate(&parent) / div;
  150. debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
  151. __func__, __LINE__,
  152. core->parent, div, rate);
  153. return rate;
  154. case CLK_TYPE_GEN2_SD0:
  155. value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
  156. div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
  157. rate = gen2_clk_get_rate(&parent) / div;
  158. debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
  159. __func__, __LINE__,
  160. core->parent, div, rate);
  161. return rate;
  162. case CLK_TYPE_GEN2_SD1:
  163. value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
  164. div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
  165. rate = gen2_clk_get_rate(&parent) / div;
  166. debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
  167. __func__, __LINE__,
  168. core->parent, div, rate);
  169. return rate;
  170. }
  171. printf("%s[%i] unknown fail\n", __func__, __LINE__);
  172. return -ENOENT;
  173. }
  174. static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
  175. {
  176. struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
  177. struct cpg_mssr_info *info = priv->info;
  178. const struct cpg_core_clk *core;
  179. struct clk parent, pparent;
  180. u32 val;
  181. int ret;
  182. ret = renesas_clk_get_parent(clk, info, &parent);
  183. if (ret) {
  184. debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  185. return ret;
  186. }
  187. if (renesas_clk_is_mod(&parent))
  188. return 0;
  189. ret = renesas_clk_get_core(&parent, info, &core);
  190. if (ret)
  191. return ret;
  192. if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
  193. return 0;
  194. ret = renesas_clk_get_parent(&parent, info, &pparent);
  195. if (ret) {
  196. debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  197. return ret;
  198. }
  199. val = (gen2_clk_get_rate(&pparent) / rate) - 1;
  200. debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
  201. writel(val, priv->base + core->offset);
  202. return 0;
  203. }
  204. static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
  205. {
  206. /* Force correct MMC-IF divider configuration if applicable */
  207. gen2_clk_setup_mmcif_div(clk, rate);
  208. return gen2_clk_get_rate(clk);
  209. }
  210. static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  211. {
  212. if (args->args_count != 2) {
  213. debug("Invaild args_count: %d\n", args->args_count);
  214. return -EINVAL;
  215. }
  216. clk->id = (args->args[0] << 16) | args->args[1];
  217. return 0;
  218. }
  219. const struct clk_ops gen2_clk_ops = {
  220. .enable = gen2_clk_enable,
  221. .disable = gen2_clk_disable,
  222. .get_rate = gen2_clk_get_rate,
  223. .set_rate = gen2_clk_set_rate,
  224. .of_xlate = gen2_clk_of_xlate,
  225. };
  226. int gen2_clk_probe(struct udevice *dev)
  227. {
  228. struct gen2_clk_priv *priv = dev_get_priv(dev);
  229. struct cpg_mssr_info *info =
  230. (struct cpg_mssr_info *)dev_get_driver_data(dev);
  231. fdt_addr_t rst_base;
  232. u32 cpg_mode;
  233. int ret;
  234. priv->base = (struct gen2_base *)devfdt_get_addr(dev);
  235. if (!priv->base)
  236. return -EINVAL;
  237. priv->info = info;
  238. ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
  239. if (ret < 0)
  240. return ret;
  241. rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg",
  242. 0, NULL, false);
  243. if (rst_base == FDT_ADDR_T_NONE)
  244. return -EINVAL;
  245. cpg_mode = readl(rst_base + CPG_RST_MODEMR);
  246. priv->cpg_pll_config =
  247. (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
  248. if (!priv->cpg_pll_config->extal_div)
  249. return -EINVAL;
  250. ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
  251. if (ret < 0)
  252. return ret;
  253. if (info->extal_usb_node) {
  254. ret = clk_get_by_name(dev, info->extal_usb_node,
  255. &priv->clk_extal_usb);
  256. if (ret < 0)
  257. return ret;
  258. }
  259. return 0;
  260. }
  261. int gen2_clk_remove(struct udevice *dev)
  262. {
  263. struct gen2_clk_priv *priv = dev_get_priv(dev);
  264. return renesas_clk_remove(priv->base, priv->info);
  265. }