clk-exynos7420.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Samsung Exynos7420 clock driver.
  4. * Copyright (C) 2016 Samsung Electronics
  5. * Thomas Abraham <thomas.ab@samsung.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <clk-uclass.h>
  11. #include <asm/io.h>
  12. #include <dt-bindings/clock/exynos7420-clk.h>
  13. #include "clk-pll.h"
  14. #define DIVIDER(reg, shift, mask) \
  15. (((readl(reg) >> shift) & mask) + 1)
  16. /* CMU TOPC block device structure */
  17. struct exynos7420_clk_cmu_topc {
  18. unsigned int rsvd1[68];
  19. unsigned int bus0_pll_con[2];
  20. unsigned int rsvd2[2];
  21. unsigned int bus1_pll_con[2];
  22. unsigned int rsvd3[54];
  23. unsigned int mux_sel[6];
  24. unsigned int rsvd4[250];
  25. unsigned int div[4];
  26. };
  27. /* CMU TOP0 block device structure */
  28. struct exynos7420_clk_cmu_top0 {
  29. unsigned int rsvd0[128];
  30. unsigned int mux_sel[7];
  31. unsigned int rsvd1[261];
  32. unsigned int div_peric[5];
  33. };
  34. /**
  35. * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
  36. *
  37. * @topc: base address of the memory mapped CMU TOPC controller.
  38. * @fin_freq: frequency of the Oscillator clock.
  39. * @sclk_bus0_pll_a: frequency of sclk_bus0_pll_a clock.
  40. * @sclk_bus1_pll_a: frequency of sclk_bus1_pll_a clock.
  41. */
  42. struct exynos7420_clk_topc_priv {
  43. struct exynos7420_clk_cmu_topc *topc;
  44. unsigned long fin_freq;
  45. unsigned long sclk_bus0_pll_a;
  46. unsigned long sclk_bus1_pll_a;
  47. };
  48. /**
  49. * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
  50. *
  51. * @top0: base address of the memory mapped CMU TOP0 controller.
  52. * @mout_top0_bus0_pll_half: frequency of mout_top0_bus0_pll_half clock
  53. * @sclk_uart2: frequency of sclk_uart2 clock.
  54. */
  55. struct exynos7420_clk_top0_priv {
  56. struct exynos7420_clk_cmu_top0 *top0;
  57. unsigned long mout_top0_bus0_pll_half;
  58. unsigned long sclk_uart2;
  59. };
  60. static ulong exynos7420_topc_get_rate(struct clk *clk)
  61. {
  62. struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
  63. switch (clk->id) {
  64. case DOUT_SCLK_BUS0_PLL:
  65. case SCLK_BUS0_PLL_A:
  66. case SCLK_BUS0_PLL_B:
  67. return priv->sclk_bus0_pll_a;
  68. case DOUT_SCLK_BUS1_PLL:
  69. case SCLK_BUS1_PLL_A:
  70. case SCLK_BUS1_PLL_B:
  71. return priv->sclk_bus1_pll_a;
  72. default:
  73. return 0;
  74. }
  75. }
  76. static struct clk_ops exynos7420_clk_topc_ops = {
  77. .get_rate = exynos7420_topc_get_rate,
  78. };
  79. static int exynos7420_clk_topc_probe(struct udevice *dev)
  80. {
  81. struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
  82. struct exynos7420_clk_cmu_topc *topc;
  83. struct clk in_clk;
  84. unsigned long rate;
  85. fdt_addr_t base;
  86. int ret;
  87. base = devfdt_get_addr(dev);
  88. if (base == FDT_ADDR_T_NONE)
  89. return -EINVAL;
  90. topc = (struct exynos7420_clk_cmu_topc *)base;
  91. priv->topc = topc;
  92. ret = clk_get_by_index(dev, 0, &in_clk);
  93. if (ret >= 0)
  94. priv->fin_freq = clk_get_rate(&in_clk);
  95. rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
  96. if (readl(&topc->mux_sel[1]) & (1 << 16))
  97. rate >>= 1;
  98. rate /= DIVIDER(&topc->div[3], 0, 0xf);
  99. priv->sclk_bus0_pll_a = rate;
  100. rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
  101. DIVIDER(&topc->div[3], 8, 0xf);
  102. priv->sclk_bus1_pll_a = rate;
  103. return 0;
  104. }
  105. static ulong exynos7420_top0_get_rate(struct clk *clk)
  106. {
  107. struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk->dev);
  108. struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
  109. switch (clk->id) {
  110. case CLK_SCLK_UART2:
  111. return priv->mout_top0_bus0_pll_half /
  112. DIVIDER(&top0->div_peric[3], 8, 0xf);
  113. default:
  114. return 0;
  115. }
  116. }
  117. static struct clk_ops exynos7420_clk_top0_ops = {
  118. .get_rate = exynos7420_top0_get_rate,
  119. };
  120. static int exynos7420_clk_top0_probe(struct udevice *dev)
  121. {
  122. struct exynos7420_clk_top0_priv *priv;
  123. struct exynos7420_clk_cmu_top0 *top0;
  124. struct clk in_clk;
  125. fdt_addr_t base;
  126. int ret;
  127. priv = dev_get_priv(dev);
  128. if (!priv)
  129. return -EINVAL;
  130. base = devfdt_get_addr(dev);
  131. if (base == FDT_ADDR_T_NONE)
  132. return -EINVAL;
  133. top0 = (struct exynos7420_clk_cmu_top0 *)base;
  134. priv->top0 = top0;
  135. ret = clk_get_by_index(dev, 1, &in_clk);
  136. if (ret >= 0) {
  137. priv->mout_top0_bus0_pll_half =
  138. clk_get_rate(&in_clk);
  139. if (readl(&top0->mux_sel[1]) & (1 << 16))
  140. priv->mout_top0_bus0_pll_half >>= 1;
  141. }
  142. return 0;
  143. }
  144. static ulong exynos7420_peric1_get_rate(struct clk *clk)
  145. {
  146. struct clk in_clk;
  147. unsigned int ret;
  148. unsigned long freq = 0;
  149. switch (clk->id) {
  150. case SCLK_UART2:
  151. ret = clk_get_by_index(clk->dev, 3, &in_clk);
  152. if (ret < 0)
  153. return ret;
  154. freq = clk_get_rate(&in_clk);
  155. break;
  156. }
  157. return freq;
  158. }
  159. static struct clk_ops exynos7420_clk_peric1_ops = {
  160. .get_rate = exynos7420_peric1_get_rate,
  161. };
  162. static const struct udevice_id exynos7420_clk_topc_compat[] = {
  163. { .compatible = "samsung,exynos7-clock-topc" },
  164. { }
  165. };
  166. U_BOOT_DRIVER(exynos7420_clk_topc) = {
  167. .name = "exynos7420-clock-topc",
  168. .id = UCLASS_CLK,
  169. .of_match = exynos7420_clk_topc_compat,
  170. .probe = exynos7420_clk_topc_probe,
  171. .priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
  172. .ops = &exynos7420_clk_topc_ops,
  173. };
  174. static const struct udevice_id exynos7420_clk_top0_compat[] = {
  175. { .compatible = "samsung,exynos7-clock-top0" },
  176. { }
  177. };
  178. U_BOOT_DRIVER(exynos7420_clk_top0) = {
  179. .name = "exynos7420-clock-top0",
  180. .id = UCLASS_CLK,
  181. .of_match = exynos7420_clk_top0_compat,
  182. .probe = exynos7420_clk_top0_probe,
  183. .priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
  184. .ops = &exynos7420_clk_top0_ops,
  185. };
  186. static const struct udevice_id exynos7420_clk_peric1_compat[] = {
  187. { .compatible = "samsung,exynos7-clock-peric1" },
  188. { }
  189. };
  190. U_BOOT_DRIVER(exynos7420_clk_peric1) = {
  191. .name = "exynos7420-clock-peric1",
  192. .id = UCLASS_CLK,
  193. .of_match = exynos7420_clk_peric1_compat,
  194. .ops = &exynos7420_clk_peric1_ops,
  195. };