arm_pl180_mmci.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ARM PrimeCell MultiMedia Card Interface - PL180
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Ulf Hansson <ulf.hansson@stericsson.com>
  8. * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
  9. * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
  10. */
  11. /* #define DEBUG */
  12. #include "common.h"
  13. #include <clk.h>
  14. #include <errno.h>
  15. #include <malloc.h>
  16. #include <mmc.h>
  17. #include <asm/io.h>
  18. #include <asm-generic/gpio.h>
  19. #include "arm_pl180_mmci.h"
  20. #ifdef CONFIG_DM_MMC
  21. #include <dm.h>
  22. #define MMC_CLOCK_MAX 48000000
  23. #define MMC_CLOCK_MIN 400000
  24. struct arm_pl180_mmc_plat {
  25. struct mmc_config cfg;
  26. struct mmc mmc;
  27. };
  28. #endif
  29. static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
  30. {
  31. u32 hoststatus, statusmask;
  32. struct pl180_mmc_host *host = dev->priv;
  33. statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
  34. if ((cmd->resp_type & MMC_RSP_PRESENT))
  35. statusmask |= SDI_STA_CMDREND;
  36. else
  37. statusmask |= SDI_STA_CMDSENT;
  38. do
  39. hoststatus = readl(&host->base->status) & statusmask;
  40. while (!hoststatus);
  41. writel(statusmask, &host->base->status_clear);
  42. if (hoststatus & SDI_STA_CTIMEOUT) {
  43. debug("CMD%d time out\n", cmd->cmdidx);
  44. return -ETIMEDOUT;
  45. } else if ((hoststatus & SDI_STA_CCRCFAIL) &&
  46. (cmd->resp_type & MMC_RSP_CRC)) {
  47. printf("CMD%d CRC error\n", cmd->cmdidx);
  48. return -EILSEQ;
  49. }
  50. if (cmd->resp_type & MMC_RSP_PRESENT) {
  51. cmd->response[0] = readl(&host->base->response0);
  52. cmd->response[1] = readl(&host->base->response1);
  53. cmd->response[2] = readl(&host->base->response2);
  54. cmd->response[3] = readl(&host->base->response3);
  55. debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
  56. "response[2]:0x%08X, response[3]:0x%08X\n",
  57. cmd->cmdidx, cmd->response[0], cmd->response[1],
  58. cmd->response[2], cmd->response[3]);
  59. }
  60. return 0;
  61. }
  62. /* send command to the mmc card and wait for results */
  63. static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
  64. {
  65. int result;
  66. u32 sdi_cmd = 0;
  67. struct pl180_mmc_host *host = dev->priv;
  68. sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
  69. if (cmd->resp_type) {
  70. sdi_cmd |= SDI_CMD_WAITRESP;
  71. if (cmd->resp_type & MMC_RSP_136)
  72. sdi_cmd |= SDI_CMD_LONGRESP;
  73. }
  74. writel((u32)cmd->cmdarg, &host->base->argument);
  75. udelay(COMMAND_REG_DELAY);
  76. writel(sdi_cmd, &host->base->command);
  77. result = wait_for_command_end(dev, cmd);
  78. /* After CMD2 set RCA to a none zero value. */
  79. if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
  80. dev->rca = 10;
  81. /* After CMD3 open drain is switched off and push pull is used. */
  82. if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
  83. u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
  84. writel(sdi_pwr, &host->base->power);
  85. }
  86. return result;
  87. }
  88. static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
  89. {
  90. u32 *tempbuff = dest;
  91. u64 xfercount = blkcount * blksize;
  92. struct pl180_mmc_host *host = dev->priv;
  93. u32 status, status_err;
  94. debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  95. status = readl(&host->base->status);
  96. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  97. SDI_STA_RXOVERR);
  98. while ((!status_err) && (xfercount >= sizeof(u32))) {
  99. if (status & SDI_STA_RXDAVL) {
  100. *(tempbuff) = readl(&host->base->fifo);
  101. tempbuff++;
  102. xfercount -= sizeof(u32);
  103. }
  104. status = readl(&host->base->status);
  105. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
  106. SDI_STA_RXOVERR);
  107. }
  108. status_err = status &
  109. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  110. SDI_STA_RXOVERR);
  111. while (!status_err) {
  112. status = readl(&host->base->status);
  113. status_err = status &
  114. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
  115. SDI_STA_RXOVERR);
  116. }
  117. if (status & SDI_STA_DTIMEOUT) {
  118. printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
  119. xfercount, status);
  120. return -ETIMEDOUT;
  121. } else if (status & SDI_STA_DCRCFAIL) {
  122. printf("Read data bytes CRC error: 0x%x\n", status);
  123. return -EILSEQ;
  124. } else if (status & SDI_STA_RXOVERR) {
  125. printf("Read data RX overflow error\n");
  126. return -EIO;
  127. }
  128. writel(SDI_ICR_MASK, &host->base->status_clear);
  129. if (xfercount) {
  130. printf("Read data error, xfercount: %llu\n", xfercount);
  131. return -ENOBUFS;
  132. }
  133. return 0;
  134. }
  135. static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
  136. {
  137. u32 *tempbuff = src;
  138. int i;
  139. u64 xfercount = blkcount * blksize;
  140. struct pl180_mmc_host *host = dev->priv;
  141. u32 status, status_err;
  142. debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
  143. status = readl(&host->base->status);
  144. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  145. while (!status_err && xfercount) {
  146. if (status & SDI_STA_TXFIFOBW) {
  147. if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
  148. for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
  149. writel(*(tempbuff + i),
  150. &host->base->fifo);
  151. tempbuff += SDI_FIFO_BURST_SIZE;
  152. xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
  153. } else {
  154. while (xfercount >= sizeof(u32)) {
  155. writel(*(tempbuff), &host->base->fifo);
  156. tempbuff++;
  157. xfercount -= sizeof(u32);
  158. }
  159. }
  160. }
  161. status = readl(&host->base->status);
  162. status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
  163. }
  164. status_err = status &
  165. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  166. while (!status_err) {
  167. status = readl(&host->base->status);
  168. status_err = status &
  169. (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
  170. }
  171. if (status & SDI_STA_DTIMEOUT) {
  172. printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
  173. xfercount, status);
  174. return -ETIMEDOUT;
  175. } else if (status & SDI_STA_DCRCFAIL) {
  176. printf("Write data CRC error\n");
  177. return -EILSEQ;
  178. }
  179. writel(SDI_ICR_MASK, &host->base->status_clear);
  180. if (xfercount) {
  181. printf("Write data error, xfercount:%llu", xfercount);
  182. return -ENOBUFS;
  183. }
  184. return 0;
  185. }
  186. static int do_data_transfer(struct mmc *dev,
  187. struct mmc_cmd *cmd,
  188. struct mmc_data *data)
  189. {
  190. int error = -ETIMEDOUT;
  191. struct pl180_mmc_host *host = dev->priv;
  192. u32 blksz = 0;
  193. u32 data_ctrl = 0;
  194. u32 data_len = (u32) (data->blocks * data->blocksize);
  195. if (!host->version2) {
  196. blksz = (ffs(data->blocksize) - 1);
  197. data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
  198. } else {
  199. blksz = data->blocksize;
  200. data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT);
  201. }
  202. data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE;
  203. writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
  204. writel(data_len, &host->base->datalength);
  205. udelay(DATA_REG_DELAY);
  206. if (data->flags & MMC_DATA_READ) {
  207. data_ctrl |= SDI_DCTRL_DTDIR_IN;
  208. writel(data_ctrl, &host->base->datactrl);
  209. error = do_command(dev, cmd);
  210. if (error)
  211. return error;
  212. error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
  213. (u32)data->blocksize);
  214. } else if (data->flags & MMC_DATA_WRITE) {
  215. error = do_command(dev, cmd);
  216. if (error)
  217. return error;
  218. writel(data_ctrl, &host->base->datactrl);
  219. error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
  220. (u32)data->blocksize);
  221. }
  222. return error;
  223. }
  224. static int host_request(struct mmc *dev,
  225. struct mmc_cmd *cmd,
  226. struct mmc_data *data)
  227. {
  228. int result;
  229. if (data)
  230. result = do_data_transfer(dev, cmd, data);
  231. else
  232. result = do_command(dev, cmd);
  233. return result;
  234. }
  235. static int host_set_ios(struct mmc *dev)
  236. {
  237. struct pl180_mmc_host *host = dev->priv;
  238. u32 sdi_clkcr;
  239. sdi_clkcr = readl(&host->base->clock);
  240. /* Ramp up the clock rate */
  241. if (dev->clock) {
  242. u32 clkdiv = 0;
  243. u32 tmp_clock;
  244. if (dev->clock >= dev->cfg->f_max) {
  245. clkdiv = 0;
  246. dev->clock = dev->cfg->f_max;
  247. } else {
  248. clkdiv = (host->clock_in / dev->clock) - 2;
  249. }
  250. tmp_clock = host->clock_in / (clkdiv + 2);
  251. while (tmp_clock > dev->clock) {
  252. clkdiv++;
  253. tmp_clock = host->clock_in / (clkdiv + 2);
  254. }
  255. if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
  256. clkdiv = SDI_CLKCR_CLKDIV_MASK;
  257. tmp_clock = host->clock_in / (clkdiv + 2);
  258. dev->clock = tmp_clock;
  259. sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
  260. sdi_clkcr |= clkdiv;
  261. }
  262. /* Set the bus width */
  263. if (dev->bus_width) {
  264. u32 buswidth = 0;
  265. switch (dev->bus_width) {
  266. case 1:
  267. buswidth |= SDI_CLKCR_WIDBUS_1;
  268. break;
  269. case 4:
  270. buswidth |= SDI_CLKCR_WIDBUS_4;
  271. break;
  272. case 8:
  273. buswidth |= SDI_CLKCR_WIDBUS_8;
  274. break;
  275. default:
  276. printf("Invalid bus width: %d\n", dev->bus_width);
  277. break;
  278. }
  279. sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
  280. sdi_clkcr |= buswidth;
  281. }
  282. writel(sdi_clkcr, &host->base->clock);
  283. udelay(CLK_CHANGE_DELAY);
  284. return 0;
  285. }
  286. #ifndef CONFIG_DM_MMC
  287. /* MMC uses open drain drivers in the enumeration phase */
  288. static int mmc_host_reset(struct mmc *dev)
  289. {
  290. struct pl180_mmc_host *host = dev->priv;
  291. writel(host->pwr_init, &host->base->power);
  292. return 0;
  293. }
  294. static const struct mmc_ops arm_pl180_mmci_ops = {
  295. .send_cmd = host_request,
  296. .set_ios = host_set_ios,
  297. .init = mmc_host_reset,
  298. };
  299. /*
  300. * mmc_host_init - initialize the mmc controller.
  301. * Set initial clock and power for mmc slot.
  302. * Initialize mmc struct and register with mmc framework.
  303. */
  304. int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
  305. {
  306. u32 sdi_u32;
  307. writel(host->pwr_init, &host->base->power);
  308. writel(host->clkdiv_init, &host->base->clock);
  309. udelay(CLK_CHANGE_DELAY);
  310. /* Disable mmc interrupts */
  311. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  312. writel(sdi_u32, &host->base->mask0);
  313. host->cfg.name = host->name;
  314. host->cfg.ops = &arm_pl180_mmci_ops;
  315. /* TODO remove the duplicates */
  316. host->cfg.host_caps = host->caps;
  317. host->cfg.voltages = host->voltages;
  318. host->cfg.f_min = host->clock_min;
  319. host->cfg.f_max = host->clock_max;
  320. if (host->b_max != 0)
  321. host->cfg.b_max = host->b_max;
  322. else
  323. host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  324. *mmc = mmc_create(&host->cfg, host);
  325. if (!*mmc)
  326. return -1;
  327. debug("registered mmc interface number is:%d\n",
  328. (*mmc)->block_dev.devnum);
  329. return 0;
  330. }
  331. #endif
  332. #ifdef CONFIG_DM_MMC
  333. static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
  334. {
  335. u32 sdi_u32;
  336. writel(host->pwr_init, &host->base->power);
  337. writel(host->clkdiv_init, &host->base->clock);
  338. udelay(CLK_CHANGE_DELAY);
  339. /* Disable mmc interrupts */
  340. sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
  341. writel(sdi_u32, &host->base->mask0);
  342. }
  343. static int arm_pl180_mmc_probe(struct udevice *dev)
  344. {
  345. struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev);
  346. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  347. struct mmc *mmc = &pdata->mmc;
  348. struct pl180_mmc_host *host = dev->priv;
  349. struct mmc_config *cfg = &pdata->cfg;
  350. struct clk clk;
  351. u32 bus_width;
  352. u32 periphid;
  353. int ret;
  354. ret = clk_get_by_index(dev, 0, &clk);
  355. if (ret < 0)
  356. return ret;
  357. ret = clk_enable(&clk);
  358. if (ret) {
  359. clk_free(&clk);
  360. dev_err(dev, "failed to enable clock\n");
  361. return ret;
  362. }
  363. host->pwr_init = INIT_PWR;
  364. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
  365. SDI_CLKCR_HWFC_EN;
  366. host->clock_in = clk_get_rate(&clk);
  367. periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
  368. switch (periphid) {
  369. case STM32_MMCI_ID: /* stm32 variant */
  370. host->version2 = false;
  371. break;
  372. default:
  373. host->version2 = true;
  374. }
  375. cfg->name = dev->name;
  376. cfg->voltages = VOLTAGE_WINDOW_SD;
  377. cfg->host_caps = 0;
  378. cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  379. cfg->f_max = dev_read_u32_default(dev, "max-frequency", MMC_CLOCK_MAX);
  380. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  381. gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
  382. bus_width = dev_read_u32_default(dev, "bus-width", 1);
  383. switch (bus_width) {
  384. case 8:
  385. cfg->host_caps |= MMC_MODE_8BIT;
  386. /* Hosts capable of 8-bit transfers can also do 4 bits */
  387. case 4:
  388. cfg->host_caps |= MMC_MODE_4BIT;
  389. break;
  390. case 1:
  391. break;
  392. default:
  393. dev_err(dev, "Invalid bus-width value %u\n", bus_width);
  394. }
  395. arm_pl180_mmc_init(host);
  396. mmc->priv = host;
  397. mmc->dev = dev;
  398. upriv->mmc = mmc;
  399. return 0;
  400. }
  401. int arm_pl180_mmc_bind(struct udevice *dev)
  402. {
  403. struct arm_pl180_mmc_plat *plat = dev_get_platdata(dev);
  404. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  405. }
  406. static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
  407. struct mmc_data *data)
  408. {
  409. struct mmc *mmc = mmc_get_mmc_dev(dev);
  410. return host_request(mmc, cmd, data);
  411. }
  412. static int dm_host_set_ios(struct udevice *dev)
  413. {
  414. struct mmc *mmc = mmc_get_mmc_dev(dev);
  415. return host_set_ios(mmc);
  416. }
  417. static int dm_mmc_getcd(struct udevice *dev)
  418. {
  419. struct pl180_mmc_host *host = dev->priv;
  420. int value = 1;
  421. if (dm_gpio_is_valid(&host->cd_gpio))
  422. value = dm_gpio_get_value(&host->cd_gpio);
  423. return value;
  424. }
  425. static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
  426. .send_cmd = dm_host_request,
  427. .set_ios = dm_host_set_ios,
  428. .get_cd = dm_mmc_getcd,
  429. };
  430. static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev)
  431. {
  432. struct pl180_mmc_host *host = dev->priv;
  433. fdt_addr_t addr;
  434. addr = dev_read_addr(dev);
  435. if (addr == FDT_ADDR_T_NONE)
  436. return -EINVAL;
  437. host->base = (void *)addr;
  438. return 0;
  439. }
  440. static const struct udevice_id arm_pl180_mmc_match[] = {
  441. { .compatible = "arm,pl180" },
  442. { .compatible = "arm,primecell" },
  443. { /* sentinel */ }
  444. };
  445. U_BOOT_DRIVER(arm_pl180_mmc) = {
  446. .name = "arm_pl180_mmc",
  447. .id = UCLASS_MMC,
  448. .of_match = arm_pl180_mmc_match,
  449. .ops = &arm_pl180_dm_mmc_ops,
  450. .probe = arm_pl180_mmc_probe,
  451. .ofdata_to_platdata = arm_pl180_mmc_ofdata_to_platdata,
  452. .bind = arm_pl180_mmc_bind,
  453. .priv_auto_alloc_size = sizeof(struct pl180_mmc_host),
  454. .platdata_auto_alloc_size = sizeof(struct arm_pl180_mmc_plat),
  455. };
  456. #endif