fsp_graphics.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <log.h>
  9. #include <vbe.h>
  10. #include <video.h>
  11. #include <asm/fsp/fsp_support.h>
  12. #include <asm/mtrr.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. struct pixel {
  15. u8 pos;
  16. u8 size;
  17. };
  18. static const struct fsp_framebuffer {
  19. struct pixel red;
  20. struct pixel green;
  21. struct pixel blue;
  22. struct pixel rsvd;
  23. } fsp_framebuffer_format_map[] = {
  24. [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
  25. [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
  26. };
  27. static int save_vesa_mode(struct vesa_mode_info *vesa)
  28. {
  29. const struct hob_graphics_info *ginfo;
  30. const struct fsp_framebuffer *fbinfo;
  31. ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
  32. /*
  33. * If there is no graphics info structure, bail out and keep
  34. * running on the serial console.
  35. *
  36. * Note: on some platforms (eg: Braswell), the FSP will not produce
  37. * the graphics info HOB unless you plug some cables to the display
  38. * interface (eg: HDMI) on the board.
  39. */
  40. if (!ginfo) {
  41. debug("FSP graphics hand-off block not found\n");
  42. return -ENXIO;
  43. }
  44. vesa->x_resolution = ginfo->width;
  45. vesa->y_resolution = ginfo->height;
  46. vesa->bits_per_pixel = 32;
  47. vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
  48. vesa->phys_base_ptr = ginfo->fb_base;
  49. if (ginfo->pixel_format >= pixel_bitmask) {
  50. debug("FSP set unknown framebuffer format: %d\n",
  51. ginfo->pixel_format);
  52. return -EINVAL;
  53. }
  54. fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
  55. vesa->red_mask_size = fbinfo->red.size;
  56. vesa->red_mask_pos = fbinfo->red.pos;
  57. vesa->green_mask_size = fbinfo->green.size;
  58. vesa->green_mask_pos = fbinfo->green.pos;
  59. vesa->blue_mask_size = fbinfo->blue.size;
  60. vesa->blue_mask_pos = fbinfo->blue.pos;
  61. vesa->reserved_mask_size = fbinfo->rsvd.size;
  62. vesa->reserved_mask_pos = fbinfo->rsvd.pos;
  63. return 0;
  64. }
  65. static int fsp_video_probe(struct udevice *dev)
  66. {
  67. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  68. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  69. struct vesa_mode_info *vesa = &mode_info.vesa;
  70. int ret;
  71. if (!ll_boot_init())
  72. return 0;
  73. printf("Video: ");
  74. /* Initialize vesa_mode_info structure */
  75. ret = save_vesa_mode(vesa);
  76. if (ret)
  77. goto err;
  78. /*
  79. * The framebuffer base address in the FSP graphics info HOB reflects
  80. * the value assigned by the FSP. After PCI enumeration the framebuffer
  81. * base address may be relocated. Let's get the updated one from device.
  82. *
  83. * For IGD, it seems to be always on BAR2.
  84. */
  85. vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
  86. gd->fb_base = vesa->phys_base_ptr;
  87. ret = vbe_setup_video_priv(vesa, uc_priv, plat);
  88. if (ret)
  89. goto err;
  90. mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
  91. mtrr_commit(true);
  92. printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
  93. vesa->bits_per_pixel, vesa->phys_base_ptr);
  94. return 0;
  95. err:
  96. printf("No video mode configured in FSP!\n");
  97. return ret;
  98. }
  99. static const struct udevice_id fsp_video_ids[] = {
  100. { .compatible = "fsp-fb" },
  101. { }
  102. };
  103. U_BOOT_DRIVER(fsp_video) = {
  104. .name = "fsp_video",
  105. .id = UCLASS_VIDEO,
  106. .of_match = fsp_video_ids,
  107. .probe = fsp_video_probe,
  108. };
  109. static struct pci_device_id fsp_video_supported[] = {
  110. { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
  111. { },
  112. };
  113. U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);