cpu.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/encoding.h>
  11. #include <dm/uclass-internal.h>
  12. #include <linux/bitops.h>
  13. /*
  14. * The variables here must be stored in the data section since they are used
  15. * before the bss section is available.
  16. */
  17. #ifdef CONFIG_OF_PRIOR_STAGE
  18. phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
  19. #endif
  20. #ifndef CONFIG_XIP
  21. u32 hart_lottery __attribute__((section(".data"))) = 0;
  22. /*
  23. * The main hart running U-Boot has acquired available_harts_lock until it has
  24. * finished initialization of global data.
  25. */
  26. u32 available_harts_lock = 1;
  27. #endif
  28. static inline bool supports_extension(char ext)
  29. {
  30. #ifdef CONFIG_CPU
  31. struct udevice *dev;
  32. char desc[32];
  33. uclass_find_first_device(UCLASS_CPU, &dev);
  34. if (!dev) {
  35. debug("unable to find the RISC-V cpu device\n");
  36. return false;
  37. }
  38. if (!cpu_get_desc(dev, desc, sizeof(desc))) {
  39. /* skip the first 4 characters (rv32|rv64) */
  40. if (strchr(desc + 4, ext))
  41. return true;
  42. }
  43. return false;
  44. #else /* !CONFIG_CPU */
  45. #if CONFIG_IS_ENABLED(RISCV_MMODE)
  46. return csr_read(CSR_MISA) & (1 << (ext - 'a'));
  47. #else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
  48. #warning "There is no way to determine the available extensions in S-mode."
  49. #warning "Please convert your board to use the RISC-V CPU driver."
  50. return false;
  51. #endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
  52. #endif /* CONFIG_CPU */
  53. }
  54. static int riscv_cpu_probe(void)
  55. {
  56. #ifdef CONFIG_CPU
  57. int ret;
  58. /* probe cpus so that RISC-V timer can be bound */
  59. ret = cpu_probe_all();
  60. if (ret)
  61. return log_msg_ret("RISC-V cpus probe failed\n", ret);
  62. #endif
  63. return 0;
  64. }
  65. int arch_cpu_init_dm(void)
  66. {
  67. int ret;
  68. ret = riscv_cpu_probe();
  69. if (ret)
  70. return ret;
  71. /* Enable FPU */
  72. if (supports_extension('d') || supports_extension('f')) {
  73. csr_set(MODE_PREFIX(status), MSTATUS_FS);
  74. csr_write(CSR_FCSR, 0);
  75. }
  76. if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
  77. /*
  78. * Enable perf counters for cycle, time,
  79. * and instret counters only
  80. */
  81. #ifdef CONFIG_RISCV_PRIV_1_9
  82. csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
  83. csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
  84. #else
  85. csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
  86. #endif
  87. /* Disable paging */
  88. if (supports_extension('s'))
  89. #ifdef CONFIG_RISCV_PRIV_1_9
  90. csr_read_clear(CSR_MSTATUS, SR_VM);
  91. #else
  92. csr_write(CSR_SATP, 0);
  93. #endif
  94. }
  95. #ifdef CONFIG_SMP
  96. ret = riscv_init_ipi();
  97. if (ret)
  98. return ret;
  99. #endif
  100. return 0;
  101. }
  102. int arch_early_init_r(void)
  103. {
  104. return riscv_cpu_probe();
  105. }