omap5.dtsi 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on "omap4.dtsi"
  6. */
  7. #include <dt-bindings/bus/ti-sysc.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. #include <dt-bindings/pinctrl/omap.h>
  11. #include <dt-bindings/clock/omap5.h>
  12. / {
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. compatible = "ti,omap5";
  16. interrupt-parent = <&wakeupgen>;
  17. chosen { };
  18. aliases {
  19. i2c0 = &i2c1;
  20. i2c1 = &i2c2;
  21. i2c2 = &i2c3;
  22. i2c3 = &i2c4;
  23. i2c4 = &i2c5;
  24. serial0 = &uart1;
  25. serial1 = &uart2;
  26. serial2 = &uart3;
  27. serial3 = &uart4;
  28. serial4 = &uart5;
  29. serial5 = &uart6;
  30. };
  31. cpus {
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. cpu0: cpu@0 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a15";
  37. reg = <0x0>;
  38. operating-points = <
  39. /* kHz uV */
  40. 1000000 1060000
  41. 1500000 1250000
  42. >;
  43. clocks = <&dpll_mpu_ck>;
  44. clock-names = "cpu";
  45. clock-latency = <300000>; /* From omap-cpufreq driver */
  46. /* cooling options */
  47. #cooling-cells = <2>; /* min followed by max */
  48. };
  49. cpu@1 {
  50. device_type = "cpu";
  51. compatible = "arm,cortex-a15";
  52. reg = <0x1>;
  53. operating-points = <
  54. /* kHz uV */
  55. 1000000 1060000
  56. 1500000 1250000
  57. >;
  58. clocks = <&dpll_mpu_ck>;
  59. clock-names = "cpu";
  60. clock-latency = <300000>; /* From omap-cpufreq driver */
  61. /* cooling options */
  62. #cooling-cells = <2>; /* min followed by max */
  63. };
  64. };
  65. thermal-zones {
  66. #include "omap4-cpu-thermal.dtsi"
  67. #include "omap5-gpu-thermal.dtsi"
  68. #include "omap5-core-thermal.dtsi"
  69. };
  70. timer {
  71. compatible = "arm,armv7-timer";
  72. /* PPI secure/nonsecure IRQ */
  73. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  74. <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  75. <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  76. <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  77. interrupt-parent = <&gic>;
  78. };
  79. pmu {
  80. compatible = "arm,cortex-a15-pmu";
  81. interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  82. <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  83. };
  84. gic: interrupt-controller@48211000 {
  85. compatible = "arm,cortex-a15-gic";
  86. interrupt-controller;
  87. #interrupt-cells = <3>;
  88. reg = <0 0x48211000 0 0x1000>,
  89. <0 0x48212000 0 0x2000>,
  90. <0 0x48214000 0 0x2000>,
  91. <0 0x48216000 0 0x2000>;
  92. interrupt-parent = <&gic>;
  93. };
  94. wakeupgen: interrupt-controller@48281000 {
  95. compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  96. interrupt-controller;
  97. #interrupt-cells = <3>;
  98. reg = <0 0x48281000 0 0x1000>;
  99. interrupt-parent = <&gic>;
  100. };
  101. /*
  102. * The soc node represents the soc top level view. It is used for IPs
  103. * that are not memory mapped in the MPU view or for the MPU itself.
  104. */
  105. soc {
  106. compatible = "ti,omap-infra";
  107. mpu {
  108. compatible = "ti,omap4-mpu";
  109. ti,hwmods = "mpu";
  110. sram = <&ocmcram>;
  111. };
  112. };
  113. /*
  114. * XXX: Use a flat representation of the OMAP3 interconnect.
  115. * The real OMAP interconnect network is quite complex.
  116. * Since it will not bring real advantage to represent that in DT for
  117. * the moment, just use a fake OCP bus entry to represent the whole bus
  118. * hierarchy.
  119. */
  120. ocp {
  121. compatible = "ti,omap5-l3-noc", "simple-bus";
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. ranges = <0 0 0 0xc0000000>;
  125. dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
  126. ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  127. reg = <0 0x44000000 0 0x2000>,
  128. <0 0x44800000 0 0x3000>,
  129. <0 0x45000000 0 0x4000>;
  130. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  131. <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  132. l4_wkup: interconnect@4ae00000 {
  133. };
  134. l4_cfg: interconnect@4a000000 {
  135. };
  136. l4_per: interconnect@48000000 {
  137. };
  138. l4_abe: interconnect@40100000 {
  139. };
  140. ocmcram: sram@40300000 {
  141. compatible = "mmio-sram";
  142. reg = <0x40300000 0x20000>; /* 128k */
  143. };
  144. gpmc: gpmc@50000000 {
  145. compatible = "ti,omap4430-gpmc";
  146. reg = <0x50000000 0x1000>;
  147. #address-cells = <2>;
  148. #size-cells = <1>;
  149. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  150. dmas = <&sdma 4>;
  151. dma-names = "rxtx";
  152. gpmc,num-cs = <8>;
  153. gpmc,num-waitpins = <4>;
  154. ti,hwmods = "gpmc";
  155. clocks = <&l3_iclk_div>;
  156. clock-names = "fck";
  157. interrupt-controller;
  158. #interrupt-cells = <2>;
  159. gpio-controller;
  160. #gpio-cells = <2>;
  161. };
  162. target-module@55082000 {
  163. compatible = "ti,sysc-omap2", "ti,sysc";
  164. reg = <0x55082000 0x4>,
  165. <0x55082010 0x4>,
  166. <0x55082014 0x4>;
  167. reg-names = "rev", "sysc", "syss";
  168. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  169. <SYSC_IDLE_NO>,
  170. <SYSC_IDLE_SMART>;
  171. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  172. SYSC_OMAP2_SOFTRESET |
  173. SYSC_OMAP2_AUTOIDLE)>;
  174. clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
  175. clock-names = "fck";
  176. resets = <&prm_core 2>;
  177. reset-names = "rstctrl";
  178. ranges = <0x0 0x55082000 0x100>;
  179. #size-cells = <1>;
  180. #address-cells = <1>;
  181. mmu_ipu: mmu@0 {
  182. compatible = "ti,omap4-iommu";
  183. reg = <0x0 0x100>;
  184. interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  185. #iommu-cells = <0>;
  186. ti,iommu-bus-err-back;
  187. };
  188. };
  189. dmm@4e000000 {
  190. compatible = "ti,omap5-dmm";
  191. reg = <0x4e000000 0x800>;
  192. interrupts = <0 113 0x4>;
  193. ti,hwmods = "dmm";
  194. };
  195. emif1: emif@4c000000 {
  196. compatible = "ti,emif-4d5";
  197. ti,hwmods = "emif1";
  198. ti,no-idle-on-init;
  199. phy-type = <2>; /* DDR PHY type: Intelli PHY */
  200. reg = <0x4c000000 0x400>;
  201. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  202. hw-caps-read-idle-ctrl;
  203. hw-caps-ll-interface;
  204. hw-caps-temp-alert;
  205. };
  206. emif2: emif@4d000000 {
  207. compatible = "ti,emif-4d5";
  208. ti,hwmods = "emif2";
  209. ti,no-idle-on-init;
  210. phy-type = <2>; /* DDR PHY type: Intelli PHY */
  211. reg = <0x4d000000 0x400>;
  212. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  213. hw-caps-read-idle-ctrl;
  214. hw-caps-ll-interface;
  215. hw-caps-temp-alert;
  216. };
  217. bandgap: bandgap@4a0021e0 {
  218. reg = <0x4a0021e0 0xc
  219. 0x4a00232c 0xc
  220. 0x4a002380 0x2c
  221. 0x4a0023C0 0x3c>;
  222. interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
  223. compatible = "ti,omap5430-bandgap";
  224. #thermal-sensor-cells = <1>;
  225. };
  226. /* OCP2SCP3 */
  227. sata: sata@4a141100 {
  228. compatible = "snps,dwc-ahci";
  229. reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
  230. interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  231. phys = <&sata_phy>;
  232. phy-names = "sata-phy";
  233. clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
  234. ti,hwmods = "sata";
  235. ports-implemented = <0x1>;
  236. };
  237. target-module@56000000 {
  238. compatible = "ti,sysc-omap4", "ti,sysc";
  239. reg = <0x5600fe00 0x4>,
  240. <0x5600fe10 0x4>;
  241. reg-names = "rev", "sysc";
  242. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  243. <SYSC_IDLE_NO>,
  244. <SYSC_IDLE_SMART>;
  245. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  246. <SYSC_IDLE_NO>,
  247. <SYSC_IDLE_SMART>;
  248. clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
  249. clock-names = "fck";
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. ranges = <0 0x56000000 0x2000000>;
  253. /*
  254. * Closed source PowerVR driver, no child device
  255. * binding or driver in mainline
  256. */
  257. };
  258. target-module@58000000 {
  259. compatible = "ti,sysc-omap2", "ti,sysc";
  260. reg = <0x58000000 4>,
  261. <0x58000014 4>;
  262. reg-names = "rev", "syss";
  263. ti,syss-mask = <1>;
  264. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
  265. <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
  266. <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
  267. <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
  268. clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
  269. #address-cells = <1>;
  270. #size-cells = <1>;
  271. ranges = <0 0x58000000 0x1000000>;
  272. dss: dss@0 {
  273. compatible = "ti,omap5-dss";
  274. reg = <0 0x80>;
  275. status = "disabled";
  276. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  277. clock-names = "fck";
  278. #address-cells = <1>;
  279. #size-cells = <1>;
  280. ranges = <0 0 0x1000000>;
  281. target-module@1000 {
  282. compatible = "ti,sysc-omap2", "ti,sysc";
  283. reg = <0x1000 0x4>,
  284. <0x1010 0x4>,
  285. <0x1014 0x4>;
  286. reg-names = "rev", "sysc", "syss";
  287. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  288. <SYSC_IDLE_NO>,
  289. <SYSC_IDLE_SMART>;
  290. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  291. <SYSC_IDLE_NO>,
  292. <SYSC_IDLE_SMART>;
  293. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  294. SYSC_OMAP2_ENAWAKEUP |
  295. SYSC_OMAP2_SOFTRESET |
  296. SYSC_OMAP2_AUTOIDLE)>;
  297. ti,syss-mask = <1>;
  298. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  299. clock-names = "fck";
  300. #address-cells = <1>;
  301. #size-cells = <1>;
  302. ranges = <0 0x1000 0x1000>;
  303. dispc@0 {
  304. compatible = "ti,omap5-dispc";
  305. reg = <0 0x1000>;
  306. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  307. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  308. clock-names = "fck";
  309. };
  310. };
  311. target-module@2000 {
  312. compatible = "ti,sysc-omap2", "ti,sysc";
  313. reg = <0x2000 0x4>,
  314. <0x2010 0x4>,
  315. <0x2014 0x4>;
  316. reg-names = "rev", "sysc", "syss";
  317. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  318. <SYSC_IDLE_NO>,
  319. <SYSC_IDLE_SMART>;
  320. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  321. SYSC_OMAP2_AUTOIDLE)>;
  322. ti,syss-mask = <1>;
  323. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  324. clock-names = "fck";
  325. #address-cells = <1>;
  326. #size-cells = <1>;
  327. ranges = <0 0x2000 0x1000>;
  328. rfbi: encoder@0 {
  329. compatible = "ti,omap5-rfbi";
  330. reg = <0 0x100>;
  331. status = "disabled";
  332. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
  333. clock-names = "fck", "ick";
  334. };
  335. };
  336. target-module@5000 {
  337. compatible = "ti,sysc-omap2", "ti,sysc";
  338. reg = <0x5000 0x4>,
  339. <0x5010 0x4>,
  340. <0x5014 0x4>;
  341. reg-names = "rev", "sysc", "syss";
  342. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  343. <SYSC_IDLE_NO>,
  344. <SYSC_IDLE_SMART>;
  345. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  346. SYSC_OMAP2_ENAWAKEUP |
  347. SYSC_OMAP2_SOFTRESET |
  348. SYSC_OMAP2_AUTOIDLE)>;
  349. ti,syss-mask = <1>;
  350. #address-cells = <1>;
  351. #size-cells = <1>;
  352. ranges = <0 0x5000 0x1000>;
  353. dsi1: encoder@0 {
  354. compatible = "ti,omap5-dsi";
  355. reg = <0 0x200>,
  356. <0x200 0x40>,
  357. <0x300 0x40>;
  358. reg-names = "proto", "phy", "pll";
  359. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  360. status = "disabled";
  361. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  362. clock-names = "fck";
  363. };
  364. };
  365. target-module@9000 {
  366. compatible = "ti,sysc-omap2", "ti,sysc";
  367. reg = <0x9000 0x4>,
  368. <0x9010 0x4>,
  369. <0x9014 0x4>;
  370. reg-names = "rev", "sysc", "syss";
  371. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  372. <SYSC_IDLE_NO>,
  373. <SYSC_IDLE_SMART>;
  374. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  375. SYSC_OMAP2_ENAWAKEUP |
  376. SYSC_OMAP2_SOFTRESET |
  377. SYSC_OMAP2_AUTOIDLE)>;
  378. ti,syss-mask = <1>;
  379. #address-cells = <1>;
  380. #size-cells = <1>;
  381. ranges = <0 0x9000 0x1000>;
  382. dsi2: encoder@0 {
  383. compatible = "ti,omap5-dsi";
  384. reg = <0 0x200>,
  385. <0x200 0x40>,
  386. <0x300 0x40>;
  387. reg-names = "proto", "phy", "pll";
  388. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  389. status = "disabled";
  390. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  391. clock-names = "fck";
  392. };
  393. };
  394. target-module@40000 {
  395. compatible = "ti,sysc-omap4", "ti,sysc";
  396. reg = <0x40000 0x4>,
  397. <0x40010 0x4>;
  398. reg-names = "rev", "sysc";
  399. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  400. <SYSC_IDLE_NO>,
  401. <SYSC_IDLE_SMART>,
  402. <SYSC_IDLE_SMART_WKUP>;
  403. ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
  404. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
  405. <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
  406. clock-names = "fck", "dss_clk";
  407. #address-cells = <1>;
  408. #size-cells = <1>;
  409. ranges = <0 0x40000 0x40000>;
  410. hdmi: encoder@0 {
  411. compatible = "ti,omap5-hdmi";
  412. reg = <0 0x200>,
  413. <0x200 0x80>,
  414. <0x300 0x80>,
  415. <0x20000 0x19000>;
  416. reg-names = "wp", "pll", "phy", "core";
  417. interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  418. status = "disabled";
  419. clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
  420. <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
  421. clock-names = "fck", "sys_clk";
  422. dmas = <&sdma 76>;
  423. dma-names = "audio_tx";
  424. };
  425. };
  426. };
  427. };
  428. abb_mpu: regulator-abb-mpu {
  429. compatible = "ti,abb-v2";
  430. regulator-name = "abb_mpu";
  431. #address-cells = <0>;
  432. #size-cells = <0>;
  433. clocks = <&sys_clkin>;
  434. ti,settling-time = <50>;
  435. ti,clock-cycles = <16>;
  436. reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
  437. <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
  438. reg-names = "base-address", "int-address",
  439. "efuse-address", "ldo-address";
  440. ti,tranxdone-status-mask = <0x80>;
  441. /* LDOVBBMPU_MUX_CTRL */
  442. ti,ldovbb-override-mask = <0x400>;
  443. /* LDOVBBMPU_VSET_OUT */
  444. ti,ldovbb-vset-mask = <0x1F>;
  445. /*
  446. * NOTE: only FBB mode used but actual vset will
  447. * determine final biasing
  448. */
  449. ti,abb_info = <
  450. /*uV ABB efuse rbb_m fbb_m vset_m*/
  451. 1060000 0 0x0 0 0x02000000 0x01F00000
  452. 1250000 0 0x4 0 0x02000000 0x01F00000
  453. >;
  454. };
  455. abb_mm: regulator-abb-mm {
  456. compatible = "ti,abb-v2";
  457. regulator-name = "abb_mm";
  458. #address-cells = <0>;
  459. #size-cells = <0>;
  460. clocks = <&sys_clkin>;
  461. ti,settling-time = <50>;
  462. ti,clock-cycles = <16>;
  463. reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
  464. <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
  465. reg-names = "base-address", "int-address",
  466. "efuse-address", "ldo-address";
  467. ti,tranxdone-status-mask = <0x80000000>;
  468. /* LDOVBBMM_MUX_CTRL */
  469. ti,ldovbb-override-mask = <0x400>;
  470. /* LDOVBBMM_VSET_OUT */
  471. ti,ldovbb-vset-mask = <0x1F>;
  472. /*
  473. * NOTE: only FBB mode used but actual vset will
  474. * determine final biasing
  475. */
  476. ti,abb_info = <
  477. /*uV ABB efuse rbb_m fbb_m vset_m*/
  478. 1025000 0 0x0 0 0x02000000 0x01F00000
  479. 1120000 0 0x4 0 0x02000000 0x01F00000
  480. >;
  481. };
  482. };
  483. };
  484. &cpu_thermal {
  485. polling-delay = <500>; /* milliseconds */
  486. coefficients = <65 (-1791)>;
  487. };
  488. #include "omap5-l4.dtsi"
  489. #include "omap54xx-clocks.dtsi"
  490. &gpu_thermal {
  491. coefficients = <117 (-2992)>;
  492. };
  493. &core_thermal {
  494. coefficients = <0 2000>;
  495. };
  496. #include "omap5-l4-abe.dtsi"
  497. #include "omap54xx-clocks.dtsi"
  498. &prm {
  499. prm_dsp: prm@400 {
  500. compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
  501. reg = <0x400 0x100>;
  502. #reset-cells = <1>;
  503. };
  504. prm_core: prm@700 {
  505. compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
  506. reg = <0x700 0x100>;
  507. #reset-cells = <1>;
  508. };
  509. prm_iva: prm@1200 {
  510. compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
  511. reg = <0x1200 0x100>;
  512. #reset-cells = <1>;
  513. };
  514. prm_device: prm@1c00 {
  515. compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
  516. reg = <0x1c00 0x100>;
  517. #reset-cells = <1>;
  518. };
  519. };