omap5-l4.dtsi 70 KB

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  1. &l4_cfg { /* 0x4a000000 */
  2. compatible = "ti,omap5-l4-cfg", "simple-bus";
  3. reg = <0x4a000000 0x800>,
  4. <0x4a000800 0x800>,
  5. <0x4a001000 0x1000>;
  6. reg-names = "ap", "la", "ia0";
  7. #address-cells = <1>;
  8. #size-cells = <1>;
  9. ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
  10. <0x00080000 0x4a080000 0x080000>, /* segment 1 */
  11. <0x00100000 0x4a100000 0x080000>, /* segment 2 */
  12. <0x00180000 0x4a180000 0x080000>, /* segment 3 */
  13. <0x00200000 0x4a200000 0x080000>, /* segment 4 */
  14. <0x00280000 0x4a280000 0x080000>, /* segment 5 */
  15. <0x00300000 0x4a300000 0x080000>; /* segment 6 */
  16. segment@0 { /* 0x4a000000 */
  17. compatible = "simple-bus";
  18. #address-cells = <1>;
  19. #size-cells = <1>;
  20. ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
  21. <0x00001000 0x00001000 0x001000>, /* ap 1 */
  22. <0x00000800 0x00000800 0x000800>, /* ap 2 */
  23. <0x00002000 0x00002000 0x001000>, /* ap 3 */
  24. <0x00003000 0x00003000 0x001000>, /* ap 4 */
  25. <0x00004000 0x00004000 0x001000>, /* ap 5 */
  26. <0x00005000 0x00005000 0x001000>, /* ap 6 */
  27. <0x00056000 0x00056000 0x001000>, /* ap 7 */
  28. <0x00057000 0x00057000 0x001000>, /* ap 8 */
  29. <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
  30. <0x00058000 0x00058000 0x001000>, /* ap 10 */
  31. <0x00062000 0x00062000 0x001000>, /* ap 11 */
  32. <0x00063000 0x00063000 0x001000>, /* ap 12 */
  33. <0x00008000 0x00008000 0x002000>, /* ap 21 */
  34. <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
  35. <0x00066000 0x00066000 0x001000>, /* ap 23 */
  36. <0x00067000 0x00067000 0x001000>, /* ap 24 */
  37. <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
  38. <0x00060000 0x00060000 0x001000>, /* ap 70 */
  39. <0x00064000 0x00064000 0x001000>, /* ap 71 */
  40. <0x00065000 0x00065000 0x001000>, /* ap 72 */
  41. <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
  42. <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
  43. <0x00070000 0x00070000 0x004000>, /* ap 79 */
  44. <0x00074000 0x00074000 0x001000>, /* ap 80 */
  45. <0x00075000 0x00075000 0x001000>, /* ap 81 */
  46. <0x00076000 0x00076000 0x001000>, /* ap 82 */
  47. <0x00020000 0x00020000 0x020000>, /* ap 109 */
  48. <0x00040000 0x00040000 0x001000>, /* ap 110 */
  49. <0x00059000 0x00059000 0x001000>; /* ap 111 */
  50. target-module@2000 { /* 0x4a002000, ap 3 44.0 */
  51. compatible = "ti,sysc-omap4", "ti,sysc";
  52. reg = <0x2000 0x4>;
  53. reg-names = "rev";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. ranges = <0x0 0x2000 0x1000>;
  57. scm_core: scm@0 {
  58. compatible = "ti,omap5-scm-core", "simple-bus";
  59. reg = <0x0 0x1000>;
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. ranges = <0 0 0x800>;
  63. scm_conf: scm_conf@0 {
  64. compatible = "syscon";
  65. reg = <0x0 0x800>;
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. };
  69. };
  70. scm_padconf_core: scm@800 {
  71. compatible = "ti,omap5-scm-padconf-core",
  72. "simple-bus";
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. ranges = <0 0x800 0x800>;
  76. omap5_pmx_core: pinmux@40 {
  77. compatible = "ti,omap5-padconf",
  78. "pinctrl-single";
  79. reg = <0x40 0x01b6>;
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. #pinctrl-cells = <1>;
  83. #interrupt-cells = <1>;
  84. interrupt-controller;
  85. pinctrl-single,register-width = <16>;
  86. pinctrl-single,function-mask = <0x7fff>;
  87. };
  88. omap5_padconf_global: omap5_padconf_global@5a0 {
  89. compatible = "syscon",
  90. "simple-bus";
  91. reg = <0x5a0 0xec>;
  92. #address-cells = <1>;
  93. #size-cells = <1>;
  94. ranges = <0 0x5a0 0xec>;
  95. pbias_regulator: pbias_regulator@60 {
  96. compatible = "ti,pbias-omap5", "ti,pbias-omap";
  97. reg = <0x60 0x4>;
  98. syscon = <&omap5_padconf_global>;
  99. pbias_mmc_reg: pbias_mmc_omap5 {
  100. regulator-name = "pbias_mmc_omap5";
  101. regulator-min-microvolt = <1800000>;
  102. regulator-max-microvolt = <3300000>;
  103. };
  104. };
  105. };
  106. };
  107. };
  108. target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
  109. compatible = "ti,sysc-omap4", "ti,sysc";
  110. reg = <0x4000 0x4>;
  111. reg-names = "rev";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. ranges = <0x0 0x4000 0x1000>;
  115. cm_core_aon: cm_core_aon@0 {
  116. compatible = "ti,omap5-cm-core-aon",
  117. "simple-bus";
  118. reg = <0x0 0x2000>;
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. ranges = <0 0 0x1000>;
  122. cm_core_aon_clocks: clocks {
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. };
  126. cm_core_aon_clockdomains: clockdomains {
  127. };
  128. };
  129. };
  130. target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
  131. compatible = "ti,sysc-omap4", "ti,sysc";
  132. reg = <0x8000 0x4>;
  133. reg-names = "rev";
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. ranges = <0x0 0x8000 0x2000>;
  137. cm_core: cm_core@0 {
  138. compatible = "ti,omap5-cm-core", "simple-bus";
  139. reg = <0x0 0x2000>;
  140. #address-cells = <1>;
  141. #size-cells = <1>;
  142. ranges = <0 0 0x2000>;
  143. cm_core_clocks: clocks {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. };
  147. cm_core_clockdomains: clockdomains {
  148. };
  149. };
  150. };
  151. target-module@20000 { /* 0x4a020000, ap 109 08.0 */
  152. compatible = "ti,sysc-omap4", "ti,sysc";
  153. ti,hwmods = "usb_otg_ss";
  154. reg = <0x20000 0x4>,
  155. <0x20010 0x4>;
  156. reg-names = "rev", "sysc";
  157. ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
  158. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  159. <SYSC_IDLE_NO>,
  160. <SYSC_IDLE_SMART>,
  161. <SYSC_IDLE_SMART_WKUP>;
  162. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  163. <SYSC_IDLE_NO>,
  164. <SYSC_IDLE_SMART>,
  165. <SYSC_IDLE_SMART_WKUP>;
  166. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  167. clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
  168. clock-names = "fck";
  169. #address-cells = <1>;
  170. #size-cells = <1>;
  171. ranges = <0x0 0x20000 0x20000>;
  172. usb3: omap_dwc3@0 {
  173. compatible = "ti,dwc3";
  174. reg = <0x0 0x10000>;
  175. interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. utmi-mode = <2>;
  179. ranges = <0 0 0x20000>;
  180. dwc3: dwc3@10000 {
  181. compatible = "snps,dwc3";
  182. reg = <0x10000 0x10000>;
  183. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
  184. <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
  185. <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  186. interrupt-names = "peripheral",
  187. "host",
  188. "otg";
  189. phys = <&usb2_phy>, <&usb3_phy>;
  190. phy-names = "usb2-phy", "usb3-phy";
  191. dr_mode = "peripheral";
  192. };
  193. };
  194. };
  195. target-module@56000 { /* 0x4a056000, ap 7 02.0 */
  196. compatible = "ti,sysc-omap2", "ti,sysc";
  197. reg = <0x56000 0x4>,
  198. <0x5602c 0x4>,
  199. <0x56028 0x4>;
  200. reg-names = "rev", "sysc", "syss";
  201. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  202. SYSC_OMAP2_EMUFREE |
  203. SYSC_OMAP2_SOFTRESET |
  204. SYSC_OMAP2_AUTOIDLE)>;
  205. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  206. <SYSC_IDLE_NO>,
  207. <SYSC_IDLE_SMART>;
  208. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  209. <SYSC_IDLE_NO>,
  210. <SYSC_IDLE_SMART>;
  211. ti,syss-mask = <1>;
  212. /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
  213. clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
  214. clock-names = "fck";
  215. #address-cells = <1>;
  216. #size-cells = <1>;
  217. ranges = <0x0 0x56000 0x1000>;
  218. sdma: dma-controller@0 {
  219. compatible = "ti,omap4430-sdma", "ti,omap-sdma";
  220. reg = <0x0 0x1000>;
  221. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  222. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  223. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  224. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  225. #dma-cells = <1>;
  226. dma-channels = <32>;
  227. dma-requests = <127>;
  228. };
  229. };
  230. target-module@58000 { /* 0x4a058000, ap 10 06.0 */
  231. compatible = "ti,sysc";
  232. status = "disabled";
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. ranges = <0x00000000 0x00058000 0x00001000>,
  236. <0x00001000 0x00059000 0x00001000>,
  237. <0x00002000 0x0005a000 0x00001000>,
  238. <0x00003000 0x0005b000 0x00001000>;
  239. };
  240. target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
  241. compatible = "ti,sysc";
  242. status = "disabled";
  243. #address-cells = <1>;
  244. #size-cells = <1>;
  245. ranges = <0x0 0x5e000 0x2000>;
  246. };
  247. target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
  248. compatible = "ti,sysc-omap2", "ti,sysc";
  249. ti,hwmods = "usb_tll_hs";
  250. reg = <0x62000 0x4>,
  251. <0x62010 0x4>,
  252. <0x62014 0x4>;
  253. reg-names = "rev", "sysc", "syss";
  254. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  255. SYSC_OMAP2_ENAWAKEUP |
  256. SYSC_OMAP2_SOFTRESET |
  257. SYSC_OMAP2_AUTOIDLE)>;
  258. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  259. <SYSC_IDLE_NO>,
  260. <SYSC_IDLE_SMART>;
  261. ti,syss-mask = <1>;
  262. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  263. clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
  264. clock-names = "fck";
  265. #address-cells = <1>;
  266. #size-cells = <1>;
  267. ranges = <0x0 0x62000 0x1000>;
  268. usbhstll: usbhstll@0 {
  269. compatible = "ti,usbhs-tll";
  270. reg = <0x0 0x1000>;
  271. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  272. };
  273. };
  274. target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
  275. compatible = "ti,sysc-omap4", "ti,sysc";
  276. ti,hwmods = "usb_host_hs";
  277. reg = <0x64000 0x4>,
  278. <0x64010 0x4>;
  279. reg-names = "rev", "sysc";
  280. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  281. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  282. <SYSC_IDLE_NO>,
  283. <SYSC_IDLE_SMART>,
  284. <SYSC_IDLE_SMART_WKUP>;
  285. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  286. <SYSC_IDLE_NO>,
  287. <SYSC_IDLE_SMART>,
  288. <SYSC_IDLE_SMART_WKUP>;
  289. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  290. clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
  291. clock-names = "fck";
  292. #address-cells = <1>;
  293. #size-cells = <1>;
  294. ranges = <0x0 0x64000 0x1000>;
  295. usbhshost: usbhshost@0 {
  296. compatible = "ti,usbhs-host";
  297. reg = <0x0 0x800>;
  298. #address-cells = <1>;
  299. #size-cells = <1>;
  300. ranges = <0 0 0x1000>;
  301. clocks = <&l3init_60m_fclk>,
  302. <&xclk60mhsp1_ck>,
  303. <&xclk60mhsp2_ck>;
  304. clock-names = "refclk_60m_int",
  305. "refclk_60m_ext_p1",
  306. "refclk_60m_ext_p2";
  307. usbhsohci: ohci@800 {
  308. compatible = "ti,ohci-omap3";
  309. reg = <0x800 0x400>;
  310. interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
  311. remote-wakeup-connected;
  312. };
  313. usbhsehci: ehci@c00 {
  314. compatible = "ti,ehci-omap";
  315. reg = <0xc00 0x400>;
  316. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  317. };
  318. };
  319. };
  320. target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
  321. compatible = "ti,sysc-omap2", "ti,sysc";
  322. reg = <0x66000 0x4>,
  323. <0x66010 0x4>,
  324. <0x66014 0x4>;
  325. reg-names = "rev", "sysc", "syss";
  326. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  327. SYSC_OMAP2_SOFTRESET |
  328. SYSC_OMAP2_AUTOIDLE)>;
  329. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  330. <SYSC_IDLE_NO>,
  331. <SYSC_IDLE_SMART>;
  332. ti,syss-mask = <1>;
  333. /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
  334. clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
  335. clock-names = "fck";
  336. resets = <&prm_dsp 1>;
  337. reset-names = "rstctrl";
  338. #address-cells = <1>;
  339. #size-cells = <1>;
  340. ranges = <0x0 0x66000 0x1000>;
  341. mmu_dsp: mmu@0 {
  342. compatible = "ti,omap4-iommu";
  343. reg = <0x0 0x100>;
  344. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  345. #iommu-cells = <0>;
  346. };
  347. };
  348. target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
  349. compatible = "ti,sysc";
  350. status = "disabled";
  351. #address-cells = <1>;
  352. #size-cells = <1>;
  353. ranges = <0x0 0x70000 0x4000>;
  354. };
  355. target-module@75000 { /* 0x4a075000, ap 81 32.0 */
  356. compatible = "ti,sysc";
  357. status = "disabled";
  358. #address-cells = <1>;
  359. #size-cells = <1>;
  360. ranges = <0x0 0x75000 0x1000>;
  361. };
  362. };
  363. segment@80000 { /* 0x4a080000 */
  364. compatible = "simple-bus";
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
  368. <0x0005a000 0x000da000 0x001000>, /* ap 14 */
  369. <0x0005b000 0x000db000 0x001000>, /* ap 15 */
  370. <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
  371. <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
  372. <0x0005e000 0x000de000 0x001000>, /* ap 18 */
  373. <0x00060000 0x000e0000 0x001000>, /* ap 19 */
  374. <0x00061000 0x000e1000 0x001000>, /* ap 20 */
  375. <0x00074000 0x000f4000 0x001000>, /* ap 25 */
  376. <0x00075000 0x000f5000 0x001000>, /* ap 26 */
  377. <0x00076000 0x000f6000 0x001000>, /* ap 27 */
  378. <0x00077000 0x000f7000 0x001000>, /* ap 28 */
  379. <0x00036000 0x000b6000 0x001000>, /* ap 65 */
  380. <0x00037000 0x000b7000 0x001000>, /* ap 66 */
  381. <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
  382. <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
  383. <0x00000000 0x00080000 0x004000>, /* ap 83 */
  384. <0x00004000 0x00084000 0x001000>, /* ap 84 */
  385. <0x00005000 0x00085000 0x001000>, /* ap 85 */
  386. <0x00006000 0x00086000 0x001000>, /* ap 86 */
  387. <0x00007000 0x00087000 0x001000>, /* ap 87 */
  388. <0x00008000 0x00088000 0x001000>, /* ap 88 */
  389. <0x00010000 0x00090000 0x004000>, /* ap 89 */
  390. <0x00014000 0x00094000 0x001000>, /* ap 90 */
  391. <0x00015000 0x00095000 0x001000>, /* ap 91 */
  392. <0x00016000 0x00096000 0x001000>, /* ap 92 */
  393. <0x00017000 0x00097000 0x001000>, /* ap 93 */
  394. <0x00018000 0x00098000 0x001000>, /* ap 94 */
  395. <0x00020000 0x000a0000 0x004000>, /* ap 95 */
  396. <0x00024000 0x000a4000 0x001000>, /* ap 96 */
  397. <0x00025000 0x000a5000 0x001000>, /* ap 97 */
  398. <0x00026000 0x000a6000 0x001000>, /* ap 98 */
  399. <0x00027000 0x000a7000 0x001000>, /* ap 99 */
  400. <0x00028000 0x000a8000 0x001000>; /* ap 100 */
  401. target-module@0 { /* 0x4a080000, ap 83 28.0 */
  402. compatible = "ti,sysc-omap2", "ti,sysc";
  403. reg = <0x0 0x4>,
  404. <0x10 0x4>,
  405. <0x14 0x4>;
  406. reg-names = "rev", "sysc", "syss";
  407. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  408. SYSC_OMAP2_AUTOIDLE)>;
  409. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  410. <SYSC_IDLE_NO>,
  411. <SYSC_IDLE_SMART>;
  412. ti,syss-mask = <1>;
  413. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  414. clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
  415. clock-names = "fck";
  416. #address-cells = <1>;
  417. #size-cells = <1>;
  418. ranges = <0x00000000 0x00000000 0x00004000>,
  419. <0x00004000 0x00004000 0x00001000>,
  420. <0x00005000 0x00005000 0x00001000>,
  421. <0x00006000 0x00006000 0x00001000>,
  422. <0x00007000 0x00007000 0x00001000>;
  423. ocp2scp@0 {
  424. compatible = "ti,omap-ocp2scp";
  425. #address-cells = <1>;
  426. #size-cells = <1>;
  427. reg = <0 0x20>;
  428. };
  429. usb2_phy: usb2phy@4000 {
  430. compatible = "ti,omap-usb2";
  431. reg = <0x4000 0x7c>;
  432. syscon-phy-power = <&scm_conf 0x300>;
  433. clocks = <&usb_phy_cm_clk32k>,
  434. <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
  435. clock-names = "wkupclk", "refclk";
  436. #phy-cells = <0>;
  437. };
  438. usb3_phy: usb3phy@4400 {
  439. compatible = "ti,omap-usb3";
  440. reg = <0x4400 0x80>,
  441. <0x4800 0x64>,
  442. <0x4c00 0x40>;
  443. reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  444. syscon-phy-power = <&scm_conf 0x370>;
  445. clocks = <&usb_phy_cm_clk32k>,
  446. <&sys_clkin>,
  447. <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
  448. clock-names = "wkupclk",
  449. "sysclk",
  450. "refclk";
  451. #phy-cells = <0>;
  452. };
  453. };
  454. target-module@10000 { /* 0x4a090000, ap 89 36.0 */
  455. compatible = "ti,sysc-omap2", "ti,sysc";
  456. reg = <0x10000 0x4>,
  457. <0x10010 0x4>,
  458. <0x10014 0x4>;
  459. reg-names = "rev", "sysc", "syss";
  460. ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  461. SYSC_OMAP2_AUTOIDLE)>;
  462. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  463. <SYSC_IDLE_NO>,
  464. <SYSC_IDLE_SMART>;
  465. ti,syss-mask = <1>;
  466. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  467. clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
  468. clock-names = "fck";
  469. #address-cells = <1>;
  470. #size-cells = <1>;
  471. ranges = <0x00000000 0x00010000 0x00004000>,
  472. <0x00004000 0x00014000 0x00001000>,
  473. <0x00005000 0x00015000 0x00001000>,
  474. <0x00006000 0x00016000 0x00001000>,
  475. <0x00007000 0x00017000 0x00001000>;
  476. ocp2scp@0 {
  477. compatible = "ti,omap-ocp2scp";
  478. #address-cells = <1>;
  479. #size-cells = <1>;
  480. reg = <0x0 0x20>;
  481. };
  482. sata_phy: phy@6000 {
  483. compatible = "ti,phy-pipe3-sata";
  484. reg = <0x6000 0x80>, /* phy_rx */
  485. <0x6400 0x64>, /* phy_tx */
  486. <0x6800 0x40>; /* pll_ctrl */
  487. reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  488. syscon-phy-power = <&scm_conf 0x374>;
  489. clocks = <&sys_clkin>,
  490. <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
  491. clock-names = "sysclk", "refclk";
  492. #phy-cells = <0>;
  493. };
  494. };
  495. target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
  496. compatible = "ti,sysc";
  497. status = "disabled";
  498. #address-cells = <1>;
  499. #size-cells = <1>;
  500. ranges = <0x00000000 0x00020000 0x00004000>,
  501. <0x00004000 0x00024000 0x00001000>,
  502. <0x00005000 0x00025000 0x00001000>,
  503. <0x00006000 0x00026000 0x00001000>,
  504. <0x00007000 0x00027000 0x00001000>;
  505. };
  506. target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
  507. compatible = "ti,sysc";
  508. status = "disabled";
  509. #address-cells = <1>;
  510. #size-cells = <1>;
  511. ranges = <0x0 0x36000 0x1000>;
  512. };
  513. target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
  514. compatible = "ti,sysc";
  515. status = "disabled";
  516. #address-cells = <1>;
  517. #size-cells = <1>;
  518. ranges = <0x0 0x4d000 0x1000>;
  519. };
  520. target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
  521. compatible = "ti,sysc";
  522. status = "disabled";
  523. #address-cells = <1>;
  524. #size-cells = <1>;
  525. ranges = <0x0 0x59000 0x1000>;
  526. };
  527. target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
  528. compatible = "ti,sysc";
  529. status = "disabled";
  530. #address-cells = <1>;
  531. #size-cells = <1>;
  532. ranges = <0x0 0x5b000 0x1000>;
  533. };
  534. target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
  535. compatible = "ti,sysc";
  536. status = "disabled";
  537. #address-cells = <1>;
  538. #size-cells = <1>;
  539. ranges = <0x0 0x5d000 0x1000>;
  540. };
  541. target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
  542. compatible = "ti,sysc";
  543. status = "disabled";
  544. #address-cells = <1>;
  545. #size-cells = <1>;
  546. ranges = <0x0 0x60000 0x1000>;
  547. };
  548. target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
  549. compatible = "ti,sysc-omap4", "ti,sysc";
  550. reg = <0x74000 0x4>,
  551. <0x74010 0x4>;
  552. reg-names = "rev", "sysc";
  553. ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  554. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  555. <SYSC_IDLE_NO>,
  556. <SYSC_IDLE_SMART>;
  557. /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
  558. clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
  559. clock-names = "fck";
  560. #address-cells = <1>;
  561. #size-cells = <1>;
  562. ranges = <0x0 0x74000 0x1000>;
  563. mailbox: mailbox@0 {
  564. compatible = "ti,omap4-mailbox";
  565. reg = <0x0 0x200>;
  566. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  567. #mbox-cells = <1>;
  568. ti,mbox-num-users = <3>;
  569. ti,mbox-num-fifos = <8>;
  570. mbox_ipu: mbox_ipu {
  571. ti,mbox-tx = <0 0 0>;
  572. ti,mbox-rx = <1 0 0>;
  573. };
  574. mbox_dsp: mbox_dsp {
  575. ti,mbox-tx = <3 0 0>;
  576. ti,mbox-rx = <2 0 0>;
  577. };
  578. };
  579. };
  580. target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
  581. compatible = "ti,sysc-omap2", "ti,sysc";
  582. reg = <0x76000 0x4>,
  583. <0x76010 0x4>,
  584. <0x76014 0x4>;
  585. reg-names = "rev", "sysc", "syss";
  586. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  587. SYSC_OMAP2_ENAWAKEUP |
  588. SYSC_OMAP2_SOFTRESET |
  589. SYSC_OMAP2_AUTOIDLE)>;
  590. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  591. <SYSC_IDLE_NO>,
  592. <SYSC_IDLE_SMART>;
  593. ti,syss-mask = <1>;
  594. /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
  595. clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
  596. clock-names = "fck";
  597. #address-cells = <1>;
  598. #size-cells = <1>;
  599. ranges = <0x0 0x76000 0x1000>;
  600. hwspinlock: spinlock@0 {
  601. compatible = "ti,omap4-hwspinlock";
  602. reg = <0x0 0x1000>;
  603. #hwlock-cells = <1>;
  604. };
  605. };
  606. };
  607. segment@100000 { /* 0x4a100000 */
  608. compatible = "simple-bus";
  609. #address-cells = <1>;
  610. #size-cells = <1>;
  611. ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
  612. <0x00003000 0x00103000 0x001000>, /* ap 60 */
  613. <0x00008000 0x00108000 0x001000>, /* ap 61 */
  614. <0x00009000 0x00109000 0x001000>, /* ap 62 */
  615. <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
  616. <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
  617. <0x00040000 0x00140000 0x010000>, /* ap 101 */
  618. <0x00050000 0x00150000 0x001000>; /* ap 102 */
  619. target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
  620. compatible = "ti,sysc";
  621. status = "disabled";
  622. #address-cells = <1>;
  623. #size-cells = <1>;
  624. ranges = <0x0 0x2000 0x1000>;
  625. };
  626. target-module@8000 { /* 0x4a108000, ap 61 26.0 */
  627. compatible = "ti,sysc";
  628. status = "disabled";
  629. #address-cells = <1>;
  630. #size-cells = <1>;
  631. ranges = <0x0 0x8000 0x1000>;
  632. };
  633. target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
  634. compatible = "ti,sysc";
  635. status = "disabled";
  636. #address-cells = <1>;
  637. #size-cells = <1>;
  638. ranges = <0x0 0xa000 0x1000>;
  639. };
  640. target-module@40000 { /* 0x4a140000, ap 101 16.0 */
  641. compatible = "ti,sysc";
  642. status = "disabled";
  643. #address-cells = <1>;
  644. #size-cells = <1>;
  645. ranges = <0x0 0x40000 0x10000>;
  646. };
  647. };
  648. segment@180000 { /* 0x4a180000 */
  649. compatible = "simple-bus";
  650. #address-cells = <1>;
  651. #size-cells = <1>;
  652. };
  653. segment@200000 { /* 0x4a200000 */
  654. compatible = "simple-bus";
  655. #address-cells = <1>;
  656. #size-cells = <1>;
  657. ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
  658. <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
  659. <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
  660. <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
  661. <0x00006000 0x00206000 0x001000>, /* ap 33 */
  662. <0x00007000 0x00207000 0x001000>, /* ap 34 */
  663. <0x00004000 0x00204000 0x001000>, /* ap 35 */
  664. <0x00005000 0x00205000 0x001000>, /* ap 36 */
  665. <0x00012000 0x00212000 0x001000>, /* ap 37 */
  666. <0x00013000 0x00213000 0x001000>, /* ap 38 */
  667. <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
  668. <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
  669. <0x00010000 0x00210000 0x001000>, /* ap 41 */
  670. <0x00011000 0x00211000 0x001000>, /* ap 42 */
  671. <0x00016000 0x00216000 0x001000>, /* ap 43 */
  672. <0x00017000 0x00217000 0x001000>, /* ap 44 */
  673. <0x00014000 0x00214000 0x001000>, /* ap 45 */
  674. <0x00015000 0x00215000 0x001000>, /* ap 46 */
  675. <0x00018000 0x00218000 0x001000>, /* ap 47 */
  676. <0x00019000 0x00219000 0x001000>, /* ap 48 */
  677. <0x00020000 0x00220000 0x001000>, /* ap 49 */
  678. <0x00021000 0x00221000 0x001000>, /* ap 50 */
  679. <0x00026000 0x00226000 0x001000>, /* ap 51 */
  680. <0x00027000 0x00227000 0x001000>, /* ap 52 */
  681. <0x00028000 0x00228000 0x001000>, /* ap 53 */
  682. <0x00029000 0x00229000 0x001000>, /* ap 54 */
  683. <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
  684. <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
  685. <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
  686. <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
  687. <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
  688. <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
  689. <0x00024000 0x00224000 0x001000>, /* ap 75 */
  690. <0x00025000 0x00225000 0x001000>, /* ap 76 */
  691. <0x00002000 0x00202000 0x001000>, /* ap 103 */
  692. <0x00003000 0x00203000 0x001000>, /* ap 104 */
  693. <0x00008000 0x00208000 0x001000>, /* ap 105 */
  694. <0x00009000 0x00209000 0x001000>, /* ap 106 */
  695. <0x00022000 0x00222000 0x001000>, /* ap 107 */
  696. <0x00023000 0x00223000 0x001000>; /* ap 108 */
  697. target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
  698. compatible = "ti,sysc";
  699. status = "disabled";
  700. #address-cells = <1>;
  701. #size-cells = <1>;
  702. ranges = <0x0 0x2000 0x1000>;
  703. };
  704. target-module@4000 { /* 0x4a204000, ap 35 46.0 */
  705. compatible = "ti,sysc";
  706. status = "disabled";
  707. #address-cells = <1>;
  708. #size-cells = <1>;
  709. ranges = <0x0 0x4000 0x1000>;
  710. };
  711. target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
  712. compatible = "ti,sysc";
  713. status = "disabled";
  714. #address-cells = <1>;
  715. #size-cells = <1>;
  716. ranges = <0x0 0x6000 0x1000>;
  717. };
  718. target-module@8000 { /* 0x4a208000, ap 105 34.0 */
  719. compatible = "ti,sysc";
  720. status = "disabled";
  721. #address-cells = <1>;
  722. #size-cells = <1>;
  723. ranges = <0x0 0x8000 0x1000>;
  724. };
  725. target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
  726. compatible = "ti,sysc";
  727. status = "disabled";
  728. #address-cells = <1>;
  729. #size-cells = <1>;
  730. ranges = <0x0 0xa000 0x1000>;
  731. };
  732. target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
  733. compatible = "ti,sysc";
  734. status = "disabled";
  735. #address-cells = <1>;
  736. #size-cells = <1>;
  737. ranges = <0x0 0xc000 0x1000>;
  738. };
  739. target-module@10000 { /* 0x4a210000, ap 41 56.0 */
  740. compatible = "ti,sysc";
  741. status = "disabled";
  742. #address-cells = <1>;
  743. #size-cells = <1>;
  744. ranges = <0x0 0x10000 0x1000>;
  745. };
  746. target-module@12000 { /* 0x4a212000, ap 37 52.0 */
  747. compatible = "ti,sysc";
  748. status = "disabled";
  749. #address-cells = <1>;
  750. #size-cells = <1>;
  751. ranges = <0x0 0x12000 0x1000>;
  752. };
  753. target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
  754. compatible = "ti,sysc";
  755. status = "disabled";
  756. #address-cells = <1>;
  757. #size-cells = <1>;
  758. ranges = <0x0 0x14000 0x1000>;
  759. };
  760. target-module@16000 { /* 0x4a216000, ap 43 42.0 */
  761. compatible = "ti,sysc";
  762. status = "disabled";
  763. #address-cells = <1>;
  764. #size-cells = <1>;
  765. ranges = <0x0 0x16000 0x1000>;
  766. };
  767. target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
  768. compatible = "ti,sysc";
  769. status = "disabled";
  770. #address-cells = <1>;
  771. #size-cells = <1>;
  772. ranges = <0x0 0x18000 0x1000>;
  773. };
  774. target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
  775. compatible = "ti,sysc";
  776. status = "disabled";
  777. #address-cells = <1>;
  778. #size-cells = <1>;
  779. ranges = <0x0 0x1a000 0x1000>;
  780. };
  781. target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
  782. compatible = "ti,sysc";
  783. status = "disabled";
  784. #address-cells = <1>;
  785. #size-cells = <1>;
  786. ranges = <0x0 0x1c000 0x1000>;
  787. };
  788. target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
  789. compatible = "ti,sysc";
  790. status = "disabled";
  791. #address-cells = <1>;
  792. #size-cells = <1>;
  793. ranges = <0x0 0x1e000 0x1000>;
  794. };
  795. target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
  796. compatible = "ti,sysc";
  797. status = "disabled";
  798. #address-cells = <1>;
  799. #size-cells = <1>;
  800. ranges = <0x0 0x20000 0x1000>;
  801. };
  802. target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
  803. compatible = "ti,sysc";
  804. status = "disabled";
  805. #address-cells = <1>;
  806. #size-cells = <1>;
  807. ranges = <0x0 0x22000 0x1000>;
  808. };
  809. target-module@24000 { /* 0x4a224000, ap 75 48.0 */
  810. compatible = "ti,sysc";
  811. status = "disabled";
  812. #address-cells = <1>;
  813. #size-cells = <1>;
  814. ranges = <0x0 0x24000 0x1000>;
  815. };
  816. target-module@26000 { /* 0x4a226000, ap 51 24.0 */
  817. compatible = "ti,sysc";
  818. status = "disabled";
  819. #address-cells = <1>;
  820. #size-cells = <1>;
  821. ranges = <0x0 0x26000 0x1000>;
  822. };
  823. target-module@28000 { /* 0x4a228000, ap 53 38.0 */
  824. compatible = "ti,sysc";
  825. status = "disabled";
  826. #address-cells = <1>;
  827. #size-cells = <1>;
  828. ranges = <0x0 0x28000 0x1000>;
  829. };
  830. target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
  831. compatible = "ti,sysc";
  832. status = "disabled";
  833. #address-cells = <1>;
  834. #size-cells = <1>;
  835. ranges = <0x0 0x2a000 0x1000>;
  836. };
  837. };
  838. segment@280000 { /* 0x4a280000 */
  839. compatible = "simple-bus";
  840. #address-cells = <1>;
  841. #size-cells = <1>;
  842. };
  843. segment@300000 { /* 0x4a300000 */
  844. compatible = "simple-bus";
  845. #address-cells = <1>;
  846. #size-cells = <1>;
  847. };
  848. };
  849. &l4_per { /* 0x48000000 */
  850. compatible = "ti,omap5-l4-per", "simple-bus";
  851. reg = <0x48000000 0x800>,
  852. <0x48000800 0x800>,
  853. <0x48001000 0x400>,
  854. <0x48001400 0x400>,
  855. <0x48001800 0x400>,
  856. <0x48001c00 0x400>;
  857. reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
  858. #address-cells = <1>;
  859. #size-cells = <1>;
  860. ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
  861. <0x00200000 0x48200000 0x200000>; /* segment 1 */
  862. segment@0 { /* 0x48000000 */
  863. compatible = "simple-bus";
  864. #address-cells = <1>;
  865. #size-cells = <1>;
  866. ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
  867. <0x00001000 0x00001000 0x000400>, /* ap 1 */
  868. <0x00000800 0x00000800 0x000800>, /* ap 2 */
  869. <0x00020000 0x00020000 0x001000>, /* ap 3 */
  870. <0x00021000 0x00021000 0x001000>, /* ap 4 */
  871. <0x00032000 0x00032000 0x001000>, /* ap 5 */
  872. <0x00033000 0x00033000 0x001000>, /* ap 6 */
  873. <0x00034000 0x00034000 0x001000>, /* ap 7 */
  874. <0x00035000 0x00035000 0x001000>, /* ap 8 */
  875. <0x00036000 0x00036000 0x001000>, /* ap 9 */
  876. <0x00037000 0x00037000 0x001000>, /* ap 10 */
  877. <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
  878. <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
  879. <0x00055000 0x00055000 0x001000>, /* ap 13 */
  880. <0x00056000 0x00056000 0x001000>, /* ap 14 */
  881. <0x00057000 0x00057000 0x001000>, /* ap 15 */
  882. <0x00058000 0x00058000 0x001000>, /* ap 16 */
  883. <0x00059000 0x00059000 0x001000>, /* ap 17 */
  884. <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
  885. <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
  886. <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
  887. <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
  888. <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
  889. <0x00060000 0x00060000 0x001000>, /* ap 23 */
  890. <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
  891. <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
  892. <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
  893. <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
  894. <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
  895. <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
  896. <0x00070000 0x00070000 0x001000>, /* ap 30 */
  897. <0x00071000 0x00071000 0x001000>, /* ap 31 */
  898. <0x00072000 0x00072000 0x001000>, /* ap 32 */
  899. <0x00073000 0x00073000 0x001000>, /* ap 33 */
  900. <0x00061000 0x00061000 0x001000>, /* ap 34 */
  901. <0x00053000 0x00053000 0x001000>, /* ap 35 */
  902. <0x00054000 0x00054000 0x001000>, /* ap 36 */
  903. <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
  904. <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
  905. <0x00078000 0x00078000 0x001000>, /* ap 39 */
  906. <0x00079000 0x00079000 0x001000>, /* ap 40 */
  907. <0x00086000 0x00086000 0x001000>, /* ap 41 */
  908. <0x00087000 0x00087000 0x001000>, /* ap 42 */
  909. <0x00088000 0x00088000 0x001000>, /* ap 43 */
  910. <0x00089000 0x00089000 0x001000>, /* ap 44 */
  911. <0x00051000 0x00051000 0x001000>, /* ap 45 */
  912. <0x00052000 0x00052000 0x001000>, /* ap 46 */
  913. <0x00098000 0x00098000 0x001000>, /* ap 47 */
  914. <0x00099000 0x00099000 0x001000>, /* ap 48 */
  915. <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
  916. <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
  917. <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
  918. <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
  919. <0x00068000 0x00068000 0x001000>, /* ap 53 */
  920. <0x00069000 0x00069000 0x001000>, /* ap 54 */
  921. <0x00090000 0x00090000 0x002000>, /* ap 55 */
  922. <0x00092000 0x00092000 0x001000>, /* ap 56 */
  923. <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
  924. <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
  925. <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
  926. <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
  927. <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
  928. <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
  929. <0x00066000 0x00066000 0x001000>, /* ap 63 */
  930. <0x00067000 0x00067000 0x001000>, /* ap 64 */
  931. <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
  932. <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
  933. <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
  934. <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
  935. <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
  936. <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
  937. <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
  938. <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
  939. <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
  940. <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
  941. <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
  942. <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
  943. <0x00001400 0x00001400 0x000400>, /* ap 77 */
  944. <0x00001800 0x00001800 0x000400>, /* ap 78 */
  945. <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
  946. <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
  947. <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
  948. <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
  949. <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
  950. <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
  951. target-module@20000 { /* 0x48020000, ap 3 04.0 */
  952. compatible = "ti,sysc-omap2", "ti,sysc";
  953. reg = <0x20050 0x4>,
  954. <0x20054 0x4>,
  955. <0x20058 0x4>;
  956. reg-names = "rev", "sysc", "syss";
  957. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  958. SYSC_OMAP2_SOFTRESET |
  959. SYSC_OMAP2_AUTOIDLE)>;
  960. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  961. <SYSC_IDLE_NO>,
  962. <SYSC_IDLE_SMART>,
  963. <SYSC_IDLE_SMART_WKUP>;
  964. ti,syss-mask = <1>;
  965. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  966. clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
  967. clock-names = "fck";
  968. #address-cells = <1>;
  969. #size-cells = <1>;
  970. ranges = <0x0 0x20000 0x1000>;
  971. uart3: serial@0 {
  972. compatible = "ti,omap4-uart";
  973. reg = <0x0 0x100>;
  974. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  975. clock-frequency = <48000000>;
  976. };
  977. };
  978. target-module@32000 { /* 0x48032000, ap 5 3e.0 */
  979. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  980. reg = <0x32000 0x4>,
  981. <0x32010 0x4>;
  982. reg-names = "rev", "sysc";
  983. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  984. SYSC_OMAP4_SOFTRESET)>;
  985. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  986. <SYSC_IDLE_NO>,
  987. <SYSC_IDLE_SMART>,
  988. <SYSC_IDLE_SMART_WKUP>;
  989. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  990. clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
  991. clock-names = "fck";
  992. #address-cells = <1>;
  993. #size-cells = <1>;
  994. ranges = <0x0 0x32000 0x1000>;
  995. timer2: timer@0 {
  996. compatible = "ti,omap5430-timer";
  997. reg = <0x0 0x80>;
  998. clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
  999. clock-names = "fck";
  1000. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  1001. };
  1002. };
  1003. target-module@34000 { /* 0x48034000, ap 7 46.0 */
  1004. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  1005. reg = <0x34000 0x4>,
  1006. <0x34010 0x4>;
  1007. reg-names = "rev", "sysc";
  1008. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1009. SYSC_OMAP4_SOFTRESET)>;
  1010. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1011. <SYSC_IDLE_NO>,
  1012. <SYSC_IDLE_SMART>,
  1013. <SYSC_IDLE_SMART_WKUP>;
  1014. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1015. clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
  1016. clock-names = "fck";
  1017. #address-cells = <1>;
  1018. #size-cells = <1>;
  1019. ranges = <0x0 0x34000 0x1000>;
  1020. timer3: timer@0 {
  1021. compatible = "ti,omap5430-timer";
  1022. reg = <0x0 0x80>;
  1023. clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
  1024. clock-names = "fck";
  1025. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  1026. };
  1027. };
  1028. target-module@36000 { /* 0x48036000, ap 9 4e.0 */
  1029. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  1030. reg = <0x36000 0x4>,
  1031. <0x36010 0x4>;
  1032. reg-names = "rev", "sysc";
  1033. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1034. SYSC_OMAP4_SOFTRESET)>;
  1035. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1036. <SYSC_IDLE_NO>,
  1037. <SYSC_IDLE_SMART>,
  1038. <SYSC_IDLE_SMART_WKUP>;
  1039. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1040. clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
  1041. clock-names = "fck";
  1042. #address-cells = <1>;
  1043. #size-cells = <1>;
  1044. ranges = <0x0 0x36000 0x1000>;
  1045. timer4: timer@0 {
  1046. compatible = "ti,omap5430-timer";
  1047. reg = <0x0 0x80>;
  1048. clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
  1049. clock-names = "fck";
  1050. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  1051. };
  1052. };
  1053. target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
  1054. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  1055. reg = <0x3e000 0x4>,
  1056. <0x3e010 0x4>;
  1057. reg-names = "rev", "sysc";
  1058. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1059. SYSC_OMAP4_SOFTRESET)>;
  1060. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1061. <SYSC_IDLE_NO>,
  1062. <SYSC_IDLE_SMART>,
  1063. <SYSC_IDLE_SMART_WKUP>;
  1064. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1065. clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
  1066. clock-names = "fck";
  1067. #address-cells = <1>;
  1068. #size-cells = <1>;
  1069. ranges = <0x0 0x3e000 0x1000>;
  1070. timer9: timer@0 {
  1071. compatible = "ti,omap5430-timer";
  1072. reg = <0x0 0x80>;
  1073. clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
  1074. clock-names = "fck";
  1075. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  1076. ti,timer-pwm;
  1077. };
  1078. };
  1079. target-module@51000 { /* 0x48051000, ap 45 2e.0 */
  1080. compatible = "ti,sysc-omap2", "ti,sysc";
  1081. reg = <0x51000 0x4>,
  1082. <0x51010 0x4>,
  1083. <0x51114 0x4>;
  1084. reg-names = "rev", "sysc", "syss";
  1085. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1086. SYSC_OMAP2_SOFTRESET |
  1087. SYSC_OMAP2_AUTOIDLE)>;
  1088. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1089. <SYSC_IDLE_NO>,
  1090. <SYSC_IDLE_SMART>,
  1091. <SYSC_IDLE_SMART_WKUP>;
  1092. ti,syss-mask = <1>;
  1093. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1094. clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
  1095. <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
  1096. clock-names = "fck", "dbclk";
  1097. #address-cells = <1>;
  1098. #size-cells = <1>;
  1099. ranges = <0x0 0x51000 0x1000>;
  1100. gpio7: gpio@0 {
  1101. compatible = "ti,omap4-gpio";
  1102. reg = <0x0 0x200>;
  1103. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  1104. gpio-controller;
  1105. #gpio-cells = <2>;
  1106. interrupt-controller;
  1107. #interrupt-cells = <2>;
  1108. };
  1109. };
  1110. target-module@53000 { /* 0x48053000, ap 35 36.0 */
  1111. compatible = "ti,sysc-omap2", "ti,sysc";
  1112. reg = <0x53000 0x4>,
  1113. <0x53010 0x4>,
  1114. <0x53114 0x4>;
  1115. reg-names = "rev", "sysc", "syss";
  1116. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1117. SYSC_OMAP2_SOFTRESET |
  1118. SYSC_OMAP2_AUTOIDLE)>;
  1119. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1120. <SYSC_IDLE_NO>,
  1121. <SYSC_IDLE_SMART>,
  1122. <SYSC_IDLE_SMART_WKUP>;
  1123. ti,syss-mask = <1>;
  1124. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1125. clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
  1126. <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
  1127. clock-names = "fck", "dbclk";
  1128. #address-cells = <1>;
  1129. #size-cells = <1>;
  1130. ranges = <0x0 0x53000 0x1000>;
  1131. gpio8: gpio@0 {
  1132. compatible = "ti,omap4-gpio";
  1133. reg = <0x0 0x200>;
  1134. interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  1135. gpio-controller;
  1136. #gpio-cells = <2>;
  1137. interrupt-controller;
  1138. #interrupt-cells = <2>;
  1139. };
  1140. };
  1141. target-module@55000 { /* 0x48055000, ap 13 0e.0 */
  1142. compatible = "ti,sysc-omap2", "ti,sysc";
  1143. reg = <0x55000 0x4>,
  1144. <0x55010 0x4>,
  1145. <0x55114 0x4>;
  1146. reg-names = "rev", "sysc", "syss";
  1147. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1148. SYSC_OMAP2_SOFTRESET |
  1149. SYSC_OMAP2_AUTOIDLE)>;
  1150. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1151. <SYSC_IDLE_NO>,
  1152. <SYSC_IDLE_SMART>,
  1153. <SYSC_IDLE_SMART_WKUP>;
  1154. ti,syss-mask = <1>;
  1155. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1156. clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
  1157. <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
  1158. clock-names = "fck", "dbclk";
  1159. #address-cells = <1>;
  1160. #size-cells = <1>;
  1161. ranges = <0x0 0x55000 0x1000>;
  1162. gpio2: gpio@0 {
  1163. compatible = "ti,omap4-gpio";
  1164. reg = <0x0 0x200>;
  1165. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1166. gpio-controller;
  1167. #gpio-cells = <2>;
  1168. interrupt-controller;
  1169. #interrupt-cells = <2>;
  1170. };
  1171. };
  1172. target-module@57000 { /* 0x48057000, ap 15 06.0 */
  1173. compatible = "ti,sysc-omap2", "ti,sysc";
  1174. reg = <0x57000 0x4>,
  1175. <0x57010 0x4>,
  1176. <0x57114 0x4>;
  1177. reg-names = "rev", "sysc", "syss";
  1178. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1179. SYSC_OMAP2_SOFTRESET |
  1180. SYSC_OMAP2_AUTOIDLE)>;
  1181. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1182. <SYSC_IDLE_NO>,
  1183. <SYSC_IDLE_SMART>,
  1184. <SYSC_IDLE_SMART_WKUP>;
  1185. ti,syss-mask = <1>;
  1186. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1187. clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
  1188. <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
  1189. clock-names = "fck", "dbclk";
  1190. #address-cells = <1>;
  1191. #size-cells = <1>;
  1192. ranges = <0x0 0x57000 0x1000>;
  1193. gpio3: gpio@0 {
  1194. compatible = "ti,omap4-gpio";
  1195. reg = <0x0 0x200>;
  1196. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  1197. gpio-controller;
  1198. #gpio-cells = <2>;
  1199. interrupt-controller;
  1200. #interrupt-cells = <2>;
  1201. };
  1202. };
  1203. target-module@59000 { /* 0x48059000, ap 17 16.0 */
  1204. compatible = "ti,sysc-omap2", "ti,sysc";
  1205. reg = <0x59000 0x4>,
  1206. <0x59010 0x4>,
  1207. <0x59114 0x4>;
  1208. reg-names = "rev", "sysc", "syss";
  1209. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1210. SYSC_OMAP2_SOFTRESET |
  1211. SYSC_OMAP2_AUTOIDLE)>;
  1212. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1213. <SYSC_IDLE_NO>,
  1214. <SYSC_IDLE_SMART>,
  1215. <SYSC_IDLE_SMART_WKUP>;
  1216. ti,syss-mask = <1>;
  1217. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1218. clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
  1219. <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
  1220. clock-names = "fck", "dbclk";
  1221. #address-cells = <1>;
  1222. #size-cells = <1>;
  1223. ranges = <0x0 0x59000 0x1000>;
  1224. gpio4: gpio@0 {
  1225. compatible = "ti,omap4-gpio";
  1226. reg = <0x0 0x200>;
  1227. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  1228. gpio-controller;
  1229. #gpio-cells = <2>;
  1230. interrupt-controller;
  1231. #interrupt-cells = <2>;
  1232. };
  1233. };
  1234. target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
  1235. compatible = "ti,sysc-omap2", "ti,sysc";
  1236. reg = <0x5b000 0x4>,
  1237. <0x5b010 0x4>,
  1238. <0x5b114 0x4>;
  1239. reg-names = "rev", "sysc", "syss";
  1240. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1241. SYSC_OMAP2_SOFTRESET |
  1242. SYSC_OMAP2_AUTOIDLE)>;
  1243. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1244. <SYSC_IDLE_NO>,
  1245. <SYSC_IDLE_SMART>,
  1246. <SYSC_IDLE_SMART_WKUP>;
  1247. ti,syss-mask = <1>;
  1248. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1249. clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
  1250. <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
  1251. clock-names = "fck", "dbclk";
  1252. #address-cells = <1>;
  1253. #size-cells = <1>;
  1254. ranges = <0x0 0x5b000 0x1000>;
  1255. gpio5: gpio@0 {
  1256. compatible = "ti,omap4-gpio";
  1257. reg = <0x0 0x200>;
  1258. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  1259. gpio-controller;
  1260. #gpio-cells = <2>;
  1261. interrupt-controller;
  1262. #interrupt-cells = <2>;
  1263. };
  1264. };
  1265. target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
  1266. compatible = "ti,sysc-omap2", "ti,sysc";
  1267. reg = <0x5d000 0x4>,
  1268. <0x5d010 0x4>,
  1269. <0x5d114 0x4>;
  1270. reg-names = "rev", "sysc", "syss";
  1271. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1272. SYSC_OMAP2_SOFTRESET |
  1273. SYSC_OMAP2_AUTOIDLE)>;
  1274. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1275. <SYSC_IDLE_NO>,
  1276. <SYSC_IDLE_SMART>,
  1277. <SYSC_IDLE_SMART_WKUP>;
  1278. ti,syss-mask = <1>;
  1279. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1280. clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
  1281. <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
  1282. clock-names = "fck", "dbclk";
  1283. #address-cells = <1>;
  1284. #size-cells = <1>;
  1285. ranges = <0x0 0x5d000 0x1000>;
  1286. gpio6: gpio@0 {
  1287. compatible = "ti,omap4-gpio";
  1288. reg = <0x0 0x200>;
  1289. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  1290. gpio-controller;
  1291. #gpio-cells = <2>;
  1292. interrupt-controller;
  1293. #interrupt-cells = <2>;
  1294. };
  1295. };
  1296. target-module@60000 { /* 0x48060000, ap 23 24.0 */
  1297. compatible = "ti,sysc-omap2", "ti,sysc";
  1298. reg = <0x60000 0x8>,
  1299. <0x60010 0x8>,
  1300. <0x60090 0x8>;
  1301. reg-names = "rev", "sysc", "syss";
  1302. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  1303. SYSC_OMAP2_ENAWAKEUP |
  1304. SYSC_OMAP2_SOFTRESET |
  1305. SYSC_OMAP2_AUTOIDLE)>;
  1306. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1307. <SYSC_IDLE_NO>,
  1308. <SYSC_IDLE_SMART>,
  1309. <SYSC_IDLE_SMART_WKUP>;
  1310. ti,syss-mask = <1>;
  1311. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1312. clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
  1313. clock-names = "fck";
  1314. #address-cells = <1>;
  1315. #size-cells = <1>;
  1316. ranges = <0x0 0x60000 0x1000>;
  1317. i2c3: i2c@0 {
  1318. compatible = "ti,omap4-i2c";
  1319. reg = <0x0 0x100>;
  1320. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  1321. #address-cells = <1>;
  1322. #size-cells = <0>;
  1323. };
  1324. };
  1325. target-module@66000 { /* 0x48066000, ap 63 4c.0 */
  1326. compatible = "ti,sysc-omap2", "ti,sysc";
  1327. reg = <0x66050 0x4>,
  1328. <0x66054 0x4>,
  1329. <0x66058 0x4>;
  1330. reg-names = "rev", "sysc", "syss";
  1331. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1332. SYSC_OMAP2_SOFTRESET |
  1333. SYSC_OMAP2_AUTOIDLE)>;
  1334. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1335. <SYSC_IDLE_NO>,
  1336. <SYSC_IDLE_SMART>,
  1337. <SYSC_IDLE_SMART_WKUP>;
  1338. ti,syss-mask = <1>;
  1339. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1340. clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
  1341. clock-names = "fck";
  1342. #address-cells = <1>;
  1343. #size-cells = <1>;
  1344. ranges = <0x0 0x66000 0x1000>;
  1345. uart5: serial@0 {
  1346. compatible = "ti,omap4-uart";
  1347. reg = <0x0 0x100>;
  1348. interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  1349. clock-frequency = <48000000>;
  1350. };
  1351. };
  1352. target-module@68000 { /* 0x48068000, ap 53 54.0 */
  1353. compatible = "ti,sysc-omap2", "ti,sysc";
  1354. reg = <0x68050 0x4>,
  1355. <0x68054 0x4>,
  1356. <0x68058 0x4>;
  1357. reg-names = "rev", "sysc", "syss";
  1358. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1359. SYSC_OMAP2_SOFTRESET |
  1360. SYSC_OMAP2_AUTOIDLE)>;
  1361. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1362. <SYSC_IDLE_NO>,
  1363. <SYSC_IDLE_SMART>,
  1364. <SYSC_IDLE_SMART_WKUP>;
  1365. ti,syss-mask = <1>;
  1366. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1367. clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
  1368. clock-names = "fck";
  1369. #address-cells = <1>;
  1370. #size-cells = <1>;
  1371. ranges = <0x0 0x68000 0x1000>;
  1372. uart6: serial@0 {
  1373. compatible = "ti,omap4-uart";
  1374. reg = <0x0 0x100>;
  1375. interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  1376. clock-frequency = <48000000>;
  1377. };
  1378. };
  1379. target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
  1380. compatible = "ti,sysc-omap2", "ti,sysc";
  1381. reg = <0x6a050 0x4>,
  1382. <0x6a054 0x4>,
  1383. <0x6a058 0x4>;
  1384. reg-names = "rev", "sysc", "syss";
  1385. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1386. SYSC_OMAP2_SOFTRESET |
  1387. SYSC_OMAP2_AUTOIDLE)>;
  1388. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1389. <SYSC_IDLE_NO>,
  1390. <SYSC_IDLE_SMART>,
  1391. <SYSC_IDLE_SMART_WKUP>;
  1392. ti,syss-mask = <1>;
  1393. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1394. clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
  1395. clock-names = "fck";
  1396. #address-cells = <1>;
  1397. #size-cells = <1>;
  1398. ranges = <0x0 0x6a000 0x1000>;
  1399. uart1: serial@0 {
  1400. compatible = "ti,omap4-uart";
  1401. reg = <0x0 0x100>;
  1402. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  1403. clock-frequency = <48000000>;
  1404. };
  1405. };
  1406. target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
  1407. compatible = "ti,sysc-omap2", "ti,sysc";
  1408. reg = <0x6c050 0x4>,
  1409. <0x6c054 0x4>,
  1410. <0x6c058 0x4>;
  1411. reg-names = "rev", "sysc", "syss";
  1412. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1413. SYSC_OMAP2_SOFTRESET |
  1414. SYSC_OMAP2_AUTOIDLE)>;
  1415. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1416. <SYSC_IDLE_NO>,
  1417. <SYSC_IDLE_SMART>,
  1418. <SYSC_IDLE_SMART_WKUP>;
  1419. ti,syss-mask = <1>;
  1420. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1421. clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
  1422. clock-names = "fck";
  1423. #address-cells = <1>;
  1424. #size-cells = <1>;
  1425. ranges = <0x0 0x6c000 0x1000>;
  1426. uart2: serial@0 {
  1427. compatible = "ti,omap4-uart";
  1428. reg = <0x0 0x100>;
  1429. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  1430. clock-frequency = <48000000>;
  1431. };
  1432. };
  1433. target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
  1434. compatible = "ti,sysc-omap2", "ti,sysc";
  1435. reg = <0x6e050 0x4>,
  1436. <0x6e054 0x4>,
  1437. <0x6e058 0x4>;
  1438. reg-names = "rev", "sysc", "syss";
  1439. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  1440. SYSC_OMAP2_SOFTRESET |
  1441. SYSC_OMAP2_AUTOIDLE)>;
  1442. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1443. <SYSC_IDLE_NO>,
  1444. <SYSC_IDLE_SMART>,
  1445. <SYSC_IDLE_SMART_WKUP>;
  1446. ti,syss-mask = <1>;
  1447. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1448. clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
  1449. clock-names = "fck";
  1450. #address-cells = <1>;
  1451. #size-cells = <1>;
  1452. ranges = <0x0 0x6e000 0x1000>;
  1453. uart4: serial@0 {
  1454. compatible = "ti,omap4-uart";
  1455. reg = <0x0 0x100>;
  1456. interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  1457. clock-frequency = <48000000>;
  1458. };
  1459. };
  1460. target-module@70000 { /* 0x48070000, ap 30 14.0 */
  1461. compatible = "ti,sysc-omap2", "ti,sysc";
  1462. reg = <0x70000 0x8>,
  1463. <0x70010 0x8>,
  1464. <0x70090 0x8>;
  1465. reg-names = "rev", "sysc", "syss";
  1466. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  1467. SYSC_OMAP2_ENAWAKEUP |
  1468. SYSC_OMAP2_SOFTRESET |
  1469. SYSC_OMAP2_AUTOIDLE)>;
  1470. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1471. <SYSC_IDLE_NO>,
  1472. <SYSC_IDLE_SMART>,
  1473. <SYSC_IDLE_SMART_WKUP>;
  1474. ti,syss-mask = <1>;
  1475. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1476. clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
  1477. clock-names = "fck";
  1478. #address-cells = <1>;
  1479. #size-cells = <1>;
  1480. ranges = <0x0 0x70000 0x1000>;
  1481. i2c1: i2c@0 {
  1482. compatible = "ti,omap4-i2c";
  1483. reg = <0x0 0x100>;
  1484. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  1485. #address-cells = <1>;
  1486. #size-cells = <0>;
  1487. };
  1488. };
  1489. target-module@72000 { /* 0x48072000, ap 32 1c.0 */
  1490. compatible = "ti,sysc-omap2", "ti,sysc";
  1491. reg = <0x72000 0x8>,
  1492. <0x72010 0x8>,
  1493. <0x72090 0x8>;
  1494. reg-names = "rev", "sysc", "syss";
  1495. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  1496. SYSC_OMAP2_ENAWAKEUP |
  1497. SYSC_OMAP2_SOFTRESET |
  1498. SYSC_OMAP2_AUTOIDLE)>;
  1499. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1500. <SYSC_IDLE_NO>,
  1501. <SYSC_IDLE_SMART>,
  1502. <SYSC_IDLE_SMART_WKUP>;
  1503. ti,syss-mask = <1>;
  1504. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1505. clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
  1506. clock-names = "fck";
  1507. #address-cells = <1>;
  1508. #size-cells = <1>;
  1509. ranges = <0x0 0x72000 0x1000>;
  1510. i2c2: i2c@0 {
  1511. compatible = "ti,omap4-i2c";
  1512. reg = <0x0 0x100>;
  1513. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  1514. #address-cells = <1>;
  1515. #size-cells = <0>;
  1516. };
  1517. };
  1518. target-module@78000 { /* 0x48078000, ap 39 12.0 */
  1519. compatible = "ti,sysc";
  1520. status = "disabled";
  1521. #address-cells = <1>;
  1522. #size-cells = <1>;
  1523. ranges = <0x0 0x78000 0x1000>;
  1524. };
  1525. target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
  1526. compatible = "ti,sysc-omap2", "ti,sysc";
  1527. reg = <0x7a000 0x8>,
  1528. <0x7a010 0x8>,
  1529. <0x7a090 0x8>;
  1530. reg-names = "rev", "sysc", "syss";
  1531. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  1532. SYSC_OMAP2_ENAWAKEUP |
  1533. SYSC_OMAP2_SOFTRESET |
  1534. SYSC_OMAP2_AUTOIDLE)>;
  1535. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1536. <SYSC_IDLE_NO>,
  1537. <SYSC_IDLE_SMART>,
  1538. <SYSC_IDLE_SMART_WKUP>;
  1539. ti,syss-mask = <1>;
  1540. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1541. clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
  1542. clock-names = "fck";
  1543. #address-cells = <1>;
  1544. #size-cells = <1>;
  1545. ranges = <0x0 0x7a000 0x1000>;
  1546. i2c4: i2c@0 {
  1547. compatible = "ti,omap4-i2c";
  1548. reg = <0x0 0x100>;
  1549. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  1550. #address-cells = <1>;
  1551. #size-cells = <0>;
  1552. };
  1553. };
  1554. target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
  1555. compatible = "ti,sysc-omap2", "ti,sysc";
  1556. reg = <0x7c000 0x8>,
  1557. <0x7c010 0x8>,
  1558. <0x7c090 0x8>;
  1559. reg-names = "rev", "sysc", "syss";
  1560. ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  1561. SYSC_OMAP2_ENAWAKEUP |
  1562. SYSC_OMAP2_SOFTRESET |
  1563. SYSC_OMAP2_AUTOIDLE)>;
  1564. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1565. <SYSC_IDLE_NO>,
  1566. <SYSC_IDLE_SMART>,
  1567. <SYSC_IDLE_SMART_WKUP>;
  1568. ti,syss-mask = <1>;
  1569. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1570. clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
  1571. clock-names = "fck";
  1572. #address-cells = <1>;
  1573. #size-cells = <1>;
  1574. ranges = <0x0 0x7c000 0x1000>;
  1575. i2c5: i2c@0 {
  1576. compatible = "ti,omap4-i2c";
  1577. reg = <0x0 0x100>;
  1578. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  1579. #address-cells = <1>;
  1580. #size-cells = <0>;
  1581. };
  1582. };
  1583. target-module@86000 { /* 0x48086000, ap 41 5e.0 */
  1584. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  1585. reg = <0x86000 0x4>,
  1586. <0x86010 0x4>;
  1587. reg-names = "rev", "sysc";
  1588. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1589. SYSC_OMAP4_SOFTRESET)>;
  1590. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1591. <SYSC_IDLE_NO>,
  1592. <SYSC_IDLE_SMART>,
  1593. <SYSC_IDLE_SMART_WKUP>;
  1594. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1595. clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
  1596. clock-names = "fck";
  1597. #address-cells = <1>;
  1598. #size-cells = <1>;
  1599. ranges = <0x0 0x86000 0x1000>;
  1600. timer10: timer@0 {
  1601. compatible = "ti,omap5430-timer";
  1602. reg = <0x0 0x80>;
  1603. clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
  1604. clock-names = "fck";
  1605. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  1606. ti,timer-pwm;
  1607. };
  1608. };
  1609. target-module@88000 { /* 0x48088000, ap 43 66.0 */
  1610. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  1611. reg = <0x88000 0x4>,
  1612. <0x88010 0x4>;
  1613. reg-names = "rev", "sysc";
  1614. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1615. SYSC_OMAP4_SOFTRESET)>;
  1616. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1617. <SYSC_IDLE_NO>,
  1618. <SYSC_IDLE_SMART>,
  1619. <SYSC_IDLE_SMART_WKUP>;
  1620. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1621. clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
  1622. clock-names = "fck";
  1623. #address-cells = <1>;
  1624. #size-cells = <1>;
  1625. ranges = <0x0 0x88000 0x1000>;
  1626. timer11: timer@0 {
  1627. compatible = "ti,omap5430-timer";
  1628. reg = <0x0 0x80>;
  1629. clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
  1630. clock-names = "fck";
  1631. interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  1632. ti,timer-pwm;
  1633. };
  1634. };
  1635. rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
  1636. compatible = "ti,sysc-omap2", "ti,sysc";
  1637. reg = <0x91fe0 0x4>,
  1638. <0x91fe4 0x4>;
  1639. reg-names = "rev", "sysc";
  1640. ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
  1641. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1642. <SYSC_IDLE_NO>;
  1643. /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
  1644. clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
  1645. clock-names = "fck";
  1646. #address-cells = <1>;
  1647. #size-cells = <1>;
  1648. ranges = <0x0 0x90000 0x2000>;
  1649. rng: rng@0 {
  1650. compatible = "ti,omap4-rng";
  1651. reg = <0x0 0x2000>;
  1652. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  1653. };
  1654. };
  1655. target-module@98000 { /* 0x48098000, ap 47 08.0 */
  1656. compatible = "ti,sysc-omap4", "ti,sysc";
  1657. reg = <0x98000 0x4>,
  1658. <0x98010 0x4>;
  1659. reg-names = "rev", "sysc";
  1660. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1661. SYSC_OMAP4_SOFTRESET)>;
  1662. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1663. <SYSC_IDLE_NO>,
  1664. <SYSC_IDLE_SMART>,
  1665. <SYSC_IDLE_SMART_WKUP>;
  1666. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1667. clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
  1668. clock-names = "fck";
  1669. #address-cells = <1>;
  1670. #size-cells = <1>;
  1671. ranges = <0x0 0x98000 0x1000>;
  1672. mcspi1: spi@0 {
  1673. compatible = "ti,omap4-mcspi";
  1674. reg = <0x0 0x200>;
  1675. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  1676. #address-cells = <1>;
  1677. #size-cells = <0>;
  1678. ti,spi-num-cs = <4>;
  1679. dmas = <&sdma 35>,
  1680. <&sdma 36>,
  1681. <&sdma 37>,
  1682. <&sdma 38>,
  1683. <&sdma 39>,
  1684. <&sdma 40>,
  1685. <&sdma 41>,
  1686. <&sdma 42>;
  1687. dma-names = "tx0", "rx0", "tx1", "rx1",
  1688. "tx2", "rx2", "tx3", "rx3";
  1689. };
  1690. };
  1691. target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
  1692. compatible = "ti,sysc-omap4", "ti,sysc";
  1693. reg = <0x9a000 0x4>,
  1694. <0x9a010 0x4>;
  1695. reg-names = "rev", "sysc";
  1696. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1697. SYSC_OMAP4_SOFTRESET)>;
  1698. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1699. <SYSC_IDLE_NO>,
  1700. <SYSC_IDLE_SMART>,
  1701. <SYSC_IDLE_SMART_WKUP>;
  1702. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1703. clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
  1704. clock-names = "fck";
  1705. #address-cells = <1>;
  1706. #size-cells = <1>;
  1707. ranges = <0x0 0x9a000 0x1000>;
  1708. mcspi2: spi@0 {
  1709. compatible = "ti,omap4-mcspi";
  1710. reg = <0x0 0x200>;
  1711. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  1712. #address-cells = <1>;
  1713. #size-cells = <0>;
  1714. ti,spi-num-cs = <2>;
  1715. dmas = <&sdma 43>,
  1716. <&sdma 44>,
  1717. <&sdma 45>,
  1718. <&sdma 46>;
  1719. dma-names = "tx0", "rx0", "tx1", "rx1";
  1720. };
  1721. };
  1722. target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
  1723. compatible = "ti,sysc-omap4", "ti,sysc";
  1724. reg = <0x9c000 0x4>,
  1725. <0x9c010 0x4>;
  1726. reg-names = "rev", "sysc";
  1727. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1728. SYSC_OMAP4_SOFTRESET)>;
  1729. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1730. <SYSC_IDLE_NO>,
  1731. <SYSC_IDLE_SMART>,
  1732. <SYSC_IDLE_SMART_WKUP>;
  1733. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1734. <SYSC_IDLE_NO>,
  1735. <SYSC_IDLE_SMART>,
  1736. <SYSC_IDLE_SMART_WKUP>;
  1737. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  1738. clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
  1739. clock-names = "fck";
  1740. #address-cells = <1>;
  1741. #size-cells = <1>;
  1742. ranges = <0x0 0x9c000 0x1000>;
  1743. mmc1: mmc@0 {
  1744. compatible = "ti,omap4-hsmmc";
  1745. reg = <0x0 0x400>;
  1746. interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  1747. ti,dual-volt;
  1748. ti,needs-special-reset;
  1749. dmas = <&sdma 61>, <&sdma 62>;
  1750. dma-names = "tx", "rx";
  1751. pbias-supply = <&pbias_mmc_reg>;
  1752. };
  1753. };
  1754. target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
  1755. compatible = "ti,sysc";
  1756. status = "disabled";
  1757. #address-cells = <1>;
  1758. #size-cells = <1>;
  1759. ranges = <0x0 0xa2000 0x1000>;
  1760. };
  1761. target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
  1762. compatible = "ti,sysc";
  1763. status = "disabled";
  1764. #address-cells = <1>;
  1765. #size-cells = <1>;
  1766. ranges = <0x00000000 0x000a4000 0x00001000>,
  1767. <0x00001000 0x000a5000 0x00001000>;
  1768. };
  1769. target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
  1770. compatible = "ti,sysc";
  1771. status = "disabled";
  1772. #address-cells = <1>;
  1773. #size-cells = <1>;
  1774. ranges = <0x0 0xa8000 0x4000>;
  1775. };
  1776. target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
  1777. compatible = "ti,sysc-omap4", "ti,sysc";
  1778. reg = <0xad000 0x4>,
  1779. <0xad010 0x4>;
  1780. reg-names = "rev", "sysc";
  1781. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1782. SYSC_OMAP4_SOFTRESET)>;
  1783. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1784. <SYSC_IDLE_NO>,
  1785. <SYSC_IDLE_SMART>,
  1786. <SYSC_IDLE_SMART_WKUP>;
  1787. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1788. <SYSC_IDLE_NO>,
  1789. <SYSC_IDLE_SMART>,
  1790. <SYSC_IDLE_SMART_WKUP>;
  1791. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1792. clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
  1793. clock-names = "fck";
  1794. #address-cells = <1>;
  1795. #size-cells = <1>;
  1796. ranges = <0x0 0xad000 0x1000>;
  1797. mmc3: mmc@0 {
  1798. compatible = "ti,omap4-hsmmc";
  1799. reg = <0x0 0x400>;
  1800. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  1801. ti,needs-special-reset;
  1802. dmas = <&sdma 77>, <&sdma 78>;
  1803. dma-names = "tx", "rx";
  1804. };
  1805. };
  1806. target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
  1807. compatible = "ti,sysc";
  1808. status = "disabled";
  1809. #address-cells = <1>;
  1810. #size-cells = <1>;
  1811. ranges = <0x0 0xb2000 0x1000>;
  1812. };
  1813. target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
  1814. compatible = "ti,sysc-omap4", "ti,sysc";
  1815. reg = <0xb4000 0x4>,
  1816. <0xb4010 0x4>;
  1817. reg-names = "rev", "sysc";
  1818. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1819. SYSC_OMAP4_SOFTRESET)>;
  1820. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1821. <SYSC_IDLE_NO>,
  1822. <SYSC_IDLE_SMART>,
  1823. <SYSC_IDLE_SMART_WKUP>;
  1824. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1825. <SYSC_IDLE_NO>,
  1826. <SYSC_IDLE_SMART>,
  1827. <SYSC_IDLE_SMART_WKUP>;
  1828. /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
  1829. clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
  1830. clock-names = "fck";
  1831. #address-cells = <1>;
  1832. #size-cells = <1>;
  1833. ranges = <0x0 0xb4000 0x1000>;
  1834. mmc2: mmc@0 {
  1835. compatible = "ti,omap4-hsmmc";
  1836. reg = <0x0 0x400>;
  1837. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1838. ti,needs-special-reset;
  1839. dmas = <&sdma 47>, <&sdma 48>;
  1840. dma-names = "tx", "rx";
  1841. };
  1842. };
  1843. target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
  1844. compatible = "ti,sysc-omap4", "ti,sysc";
  1845. reg = <0xb8000 0x4>,
  1846. <0xb8010 0x4>;
  1847. reg-names = "rev", "sysc";
  1848. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1849. SYSC_OMAP4_SOFTRESET)>;
  1850. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1851. <SYSC_IDLE_NO>,
  1852. <SYSC_IDLE_SMART>,
  1853. <SYSC_IDLE_SMART_WKUP>;
  1854. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1855. clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
  1856. clock-names = "fck";
  1857. #address-cells = <1>;
  1858. #size-cells = <1>;
  1859. ranges = <0x0 0xb8000 0x1000>;
  1860. mcspi3: spi@0 {
  1861. compatible = "ti,omap4-mcspi";
  1862. reg = <0x0 0x200>;
  1863. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  1864. #address-cells = <1>;
  1865. #size-cells = <0>;
  1866. ti,spi-num-cs = <2>;
  1867. dmas = <&sdma 15>, <&sdma 16>;
  1868. dma-names = "tx0", "rx0";
  1869. };
  1870. };
  1871. target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
  1872. compatible = "ti,sysc-omap4", "ti,sysc";
  1873. reg = <0xba000 0x4>,
  1874. <0xba010 0x4>;
  1875. reg-names = "rev", "sysc";
  1876. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1877. SYSC_OMAP4_SOFTRESET)>;
  1878. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1879. <SYSC_IDLE_NO>,
  1880. <SYSC_IDLE_SMART>,
  1881. <SYSC_IDLE_SMART_WKUP>;
  1882. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1883. clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
  1884. clock-names = "fck";
  1885. #address-cells = <1>;
  1886. #size-cells = <1>;
  1887. ranges = <0x0 0xba000 0x1000>;
  1888. mcspi4: spi@0 {
  1889. compatible = "ti,omap4-mcspi";
  1890. reg = <0x0 0x200>;
  1891. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  1892. #address-cells = <1>;
  1893. #size-cells = <0>;
  1894. ti,spi-num-cs = <1>;
  1895. dmas = <&sdma 70>, <&sdma 71>;
  1896. dma-names = "tx0", "rx0";
  1897. };
  1898. };
  1899. target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
  1900. compatible = "ti,sysc-omap4", "ti,sysc";
  1901. reg = <0xd1000 0x4>,
  1902. <0xd1010 0x4>;
  1903. reg-names = "rev", "sysc";
  1904. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1905. SYSC_OMAP4_SOFTRESET)>;
  1906. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1907. <SYSC_IDLE_NO>,
  1908. <SYSC_IDLE_SMART>,
  1909. <SYSC_IDLE_SMART_WKUP>;
  1910. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1911. <SYSC_IDLE_NO>,
  1912. <SYSC_IDLE_SMART>,
  1913. <SYSC_IDLE_SMART_WKUP>;
  1914. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1915. clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
  1916. clock-names = "fck";
  1917. #address-cells = <1>;
  1918. #size-cells = <1>;
  1919. ranges = <0x0 0xd1000 0x1000>;
  1920. mmc4: mmc@0 {
  1921. compatible = "ti,omap4-hsmmc";
  1922. reg = <0x0 0x400>;
  1923. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  1924. ti,needs-special-reset;
  1925. dmas = <&sdma 57>, <&sdma 58>;
  1926. dma-names = "tx", "rx";
  1927. };
  1928. };
  1929. target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
  1930. compatible = "ti,sysc-omap4", "ti,sysc";
  1931. reg = <0xd5000 0x4>,
  1932. <0xd5010 0x4>;
  1933. reg-names = "rev", "sysc";
  1934. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  1935. SYSC_OMAP4_SOFTRESET)>;
  1936. ti,sysc-midle = <SYSC_IDLE_FORCE>,
  1937. <SYSC_IDLE_NO>,
  1938. <SYSC_IDLE_SMART>,
  1939. <SYSC_IDLE_SMART_WKUP>;
  1940. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1941. <SYSC_IDLE_NO>,
  1942. <SYSC_IDLE_SMART>,
  1943. <SYSC_IDLE_SMART_WKUP>;
  1944. /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
  1945. clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
  1946. clock-names = "fck";
  1947. #address-cells = <1>;
  1948. #size-cells = <1>;
  1949. ranges = <0x0 0xd5000 0x1000>;
  1950. mmc5: mmc@0 {
  1951. compatible = "ti,omap4-hsmmc";
  1952. reg = <0x0 0x400>;
  1953. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  1954. ti,needs-special-reset;
  1955. dmas = <&sdma 59>, <&sdma 60>;
  1956. dma-names = "tx", "rx";
  1957. };
  1958. };
  1959. };
  1960. segment@200000 { /* 0x48200000 */
  1961. compatible = "simple-bus";
  1962. #address-cells = <1>;
  1963. #size-cells = <1>;
  1964. };
  1965. };
  1966. &l4_wkup { /* 0x4ae00000 */
  1967. compatible = "ti,omap5-l4-wkup", "simple-bus";
  1968. reg = <0x4ae00000 0x800>,
  1969. <0x4ae00800 0x800>,
  1970. <0x4ae01000 0x1000>;
  1971. reg-names = "ap", "la", "ia0";
  1972. #address-cells = <1>;
  1973. #size-cells = <1>;
  1974. ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
  1975. <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
  1976. <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
  1977. segment@0 { /* 0x4ae00000 */
  1978. compatible = "simple-bus";
  1979. #address-cells = <1>;
  1980. #size-cells = <1>;
  1981. ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
  1982. <0x00001000 0x00001000 0x001000>, /* ap 1 */
  1983. <0x00000800 0x00000800 0x000800>, /* ap 2 */
  1984. <0x00006000 0x00006000 0x002000>, /* ap 3 */
  1985. <0x00008000 0x00008000 0x001000>, /* ap 4 */
  1986. <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
  1987. <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
  1988. <0x00004000 0x00004000 0x001000>, /* ap 17 */
  1989. <0x00005000 0x00005000 0x001000>, /* ap 18 */
  1990. <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
  1991. <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
  1992. target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
  1993. compatible = "ti,sysc-omap2", "ti,sysc";
  1994. ti,hwmods = "counter_32k";
  1995. reg = <0x4000 0x4>,
  1996. <0x4010 0x4>;
  1997. reg-names = "rev", "sysc";
  1998. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  1999. <SYSC_IDLE_NO>;
  2000. /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
  2001. clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
  2002. clock-names = "fck";
  2003. #address-cells = <1>;
  2004. #size-cells = <1>;
  2005. ranges = <0x0 0x4000 0x1000>;
  2006. counter32k: counter@0 {
  2007. compatible = "ti,omap-counter32k";
  2008. reg = <0x0 0x40>;
  2009. };
  2010. };
  2011. target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
  2012. compatible = "ti,sysc-omap4", "ti,sysc";
  2013. reg = <0x6000 0x4>;
  2014. reg-names = "rev";
  2015. #address-cells = <1>;
  2016. #size-cells = <1>;
  2017. ranges = <0x0 0x6000 0x2000>;
  2018. prm: prm@0 {
  2019. compatible = "ti,omap5-prm", "simple-bus";
  2020. reg = <0x0 0x2000>;
  2021. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  2022. #address-cells = <1>;
  2023. #size-cells = <1>;
  2024. ranges = <0 0 0x2000>;
  2025. prm_clocks: clocks {
  2026. #address-cells = <1>;
  2027. #size-cells = <0>;
  2028. };
  2029. prm_clockdomains: clockdomains {
  2030. };
  2031. };
  2032. };
  2033. target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
  2034. compatible = "ti,sysc-omap4", "ti,sysc";
  2035. reg = <0xa000 0x4>;
  2036. reg-names = "rev";
  2037. #address-cells = <1>;
  2038. #size-cells = <1>;
  2039. ranges = <0x0 0xa000 0x1000>;
  2040. scrm: scrm@0 {
  2041. compatible = "ti,omap5-scrm";
  2042. reg = <0x0 0x1000>;
  2043. scrm_clocks: clocks {
  2044. #address-cells = <1>;
  2045. #size-cells = <0>;
  2046. };
  2047. scrm_clockdomains: clockdomains {
  2048. };
  2049. };
  2050. };
  2051. target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
  2052. compatible = "ti,sysc-omap4", "ti,sysc";
  2053. reg = <0xc000 0x4>;
  2054. reg-names = "rev";
  2055. #address-cells = <1>;
  2056. #size-cells = <1>;
  2057. ranges = <0x0 0xc000 0x1000>;
  2058. omap5_pmx_wkup: pinmux@840 {
  2059. compatible = "ti,omap5-padconf",
  2060. "pinctrl-single";
  2061. reg = <0x840 0x003c>;
  2062. #address-cells = <1>;
  2063. #size-cells = <0>;
  2064. #pinctrl-cells = <1>;
  2065. #interrupt-cells = <1>;
  2066. interrupt-controller;
  2067. pinctrl-single,register-width = <16>;
  2068. pinctrl-single,function-mask = <0x7fff>;
  2069. };
  2070. omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
  2071. compatible = "ti,omap5-scm-wkup-pad-conf",
  2072. "simple-bus";
  2073. reg = <0xda0 0x60>;
  2074. #address-cells = <1>;
  2075. #size-cells = <1>;
  2076. ranges = <0 0 0x60>;
  2077. scm_wkup_pad_conf: scm_conf@0 {
  2078. compatible = "syscon", "simple-bus";
  2079. reg = <0x0 0x60>;
  2080. #address-cells = <1>;
  2081. #size-cells = <1>;
  2082. ranges = <0 0x0 0x60>;
  2083. scm_wkup_pad_conf_clocks: clocks@0 {
  2084. #address-cells = <1>;
  2085. #size-cells = <0>;
  2086. };
  2087. };
  2088. };
  2089. };
  2090. };
  2091. segment@10000 { /* 0x4ae10000 */
  2092. compatible = "simple-bus";
  2093. #address-cells = <1>;
  2094. #size-cells = <1>;
  2095. ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
  2096. <0x00001000 0x00011000 0x001000>, /* ap 6 */
  2097. <0x00004000 0x00014000 0x001000>, /* ap 7 */
  2098. <0x00005000 0x00015000 0x001000>, /* ap 8 */
  2099. <0x00008000 0x00018000 0x001000>, /* ap 9 */
  2100. <0x00009000 0x00019000 0x001000>, /* ap 10 */
  2101. <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
  2102. <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
  2103. target-module@0 { /* 0x4ae10000, ap 5 10.0 */
  2104. compatible = "ti,sysc-omap2", "ti,sysc";
  2105. reg = <0x0 0x4>,
  2106. <0x10 0x4>,
  2107. <0x114 0x4>;
  2108. reg-names = "rev", "sysc", "syss";
  2109. ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  2110. SYSC_OMAP2_SOFTRESET |
  2111. SYSC_OMAP2_AUTOIDLE)>;
  2112. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  2113. <SYSC_IDLE_NO>,
  2114. <SYSC_IDLE_SMART>,
  2115. <SYSC_IDLE_SMART_WKUP>;
  2116. ti,syss-mask = <1>;
  2117. /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
  2118. clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
  2119. <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
  2120. clock-names = "fck", "dbclk";
  2121. #address-cells = <1>;
  2122. #size-cells = <1>;
  2123. ranges = <0x0 0x0 0x1000>;
  2124. gpio1: gpio@0 {
  2125. compatible = "ti,omap4-gpio";
  2126. reg = <0x0 0x200>;
  2127. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  2128. ti,gpio-always-on;
  2129. gpio-controller;
  2130. #gpio-cells = <2>;
  2131. interrupt-controller;
  2132. #interrupt-cells = <2>;
  2133. };
  2134. };
  2135. target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
  2136. compatible = "ti,sysc-omap2", "ti,sysc";
  2137. reg = <0x4000 0x4>,
  2138. <0x4010 0x4>,
  2139. <0x4014 0x4>;
  2140. reg-names = "rev", "sysc", "syss";
  2141. ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
  2142. SYSC_OMAP2_SOFTRESET)>;
  2143. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  2144. <SYSC_IDLE_NO>,
  2145. <SYSC_IDLE_SMART>,
  2146. <SYSC_IDLE_SMART_WKUP>;
  2147. ti,syss-mask = <1>;
  2148. /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
  2149. clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
  2150. clock-names = "fck";
  2151. #address-cells = <1>;
  2152. #size-cells = <1>;
  2153. ranges = <0x0 0x4000 0x1000>;
  2154. wdt2: wdt@0 {
  2155. compatible = "ti,omap5-wdt", "ti,omap3-wdt";
  2156. reg = <0x0 0x80>;
  2157. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  2158. };
  2159. };
  2160. target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
  2161. compatible = "ti,sysc-omap4-timer", "ti,sysc";
  2162. ti,hwmods = "timer1";
  2163. reg = <0x8000 0x4>,
  2164. <0x8010 0x4>;
  2165. reg-names = "rev", "sysc";
  2166. ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
  2167. SYSC_OMAP4_SOFTRESET)>;
  2168. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  2169. <SYSC_IDLE_NO>,
  2170. <SYSC_IDLE_SMART>,
  2171. <SYSC_IDLE_SMART_WKUP>;
  2172. /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
  2173. clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
  2174. clock-names = "fck";
  2175. #address-cells = <1>;
  2176. #size-cells = <1>;
  2177. ranges = <0x0 0x8000 0x1000>;
  2178. timer1: timer@0 {
  2179. compatible = "ti,omap5430-timer";
  2180. reg = <0x0 0x80>;
  2181. clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
  2182. clock-names = "fck";
  2183. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  2184. ti,timer-alwon;
  2185. };
  2186. };
  2187. target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
  2188. compatible = "ti,sysc-omap2", "ti,sysc";
  2189. reg = <0xc000 0x4>,
  2190. <0xc010 0x4>;
  2191. reg-names = "rev", "sysc";
  2192. ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
  2193. SYSC_OMAP2_SOFTRESET)>;
  2194. ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  2195. <SYSC_IDLE_NO>,
  2196. <SYSC_IDLE_SMART>;
  2197. /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
  2198. clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
  2199. clock-names = "fck";
  2200. #address-cells = <1>;
  2201. #size-cells = <1>;
  2202. ranges = <0x0 0xc000 0x1000>;
  2203. keypad: keypad@0 {
  2204. compatible = "ti,omap4-keypad";
  2205. reg = <0x0 0x400>;
  2206. };
  2207. };
  2208. };
  2209. segment@20000 { /* 0x4ae20000 */
  2210. compatible = "simple-bus";
  2211. #address-cells = <1>;
  2212. #size-cells = <1>;
  2213. ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
  2214. <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
  2215. <0x00000000 0x00020000 0x001000>, /* ap 21 */
  2216. <0x00001000 0x00021000 0x001000>, /* ap 22 */
  2217. <0x00002000 0x00022000 0x001000>, /* ap 23 */
  2218. <0x00003000 0x00023000 0x001000>, /* ap 24 */
  2219. <0x00007000 0x00027000 0x000400>, /* ap 25 */
  2220. <0x00008000 0x00028000 0x000800>, /* ap 26 */
  2221. <0x00009000 0x00029000 0x000100>, /* ap 27 */
  2222. <0x00008800 0x00028800 0x000200>, /* ap 28 */
  2223. <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
  2224. target-module@0 { /* 0x4ae20000, ap 21 04.0 */
  2225. compatible = "ti,sysc";
  2226. status = "disabled";
  2227. #address-cells = <1>;
  2228. #size-cells = <1>;
  2229. ranges = <0x0 0x0 0x1000>;
  2230. };
  2231. target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
  2232. compatible = "ti,sysc";
  2233. status = "disabled";
  2234. #address-cells = <1>;
  2235. #size-cells = <1>;
  2236. ranges = <0x0 0x2000 0x1000>;
  2237. };
  2238. target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
  2239. compatible = "ti,sysc";
  2240. status = "disabled";
  2241. #address-cells = <1>;
  2242. #size-cells = <1>;
  2243. ranges = <0x00000000 0x00006000 0x00001000>,
  2244. <0x00001000 0x00007000 0x00000400>,
  2245. <0x00002000 0x00008000 0x00000800>,
  2246. <0x00002800 0x00008800 0x00000200>,
  2247. <0x00002a00 0x00008a00 0x00000100>,
  2248. <0x00003000 0x00009000 0x00000100>;
  2249. };
  2250. };
  2251. };